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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-10-11 17:57:18 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-10-11 17:57:18 +0000
commit82d5cb36c37aa9de158a47397de802b181d0abd6 (patch)
tree0c734a4c26beaff9caac57c4749aeb618905d963
parent980fa49caf3343cb3bc098ab97bff184a83c82d7 (diff)
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F4x PLL clock checking fixed. According to RM0090 the value of PLLN may be between 64 and 432.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4740 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index ce01b9ce0..a8f61cf62 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -986,7 +986,7 @@
/**
* @brief STM32_PLLN field.
*/
-#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) || \
+#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
defined(__DOXYGEN__)
#define STM32_PLLN (STM32_PLLN_VALUE << 6)
#else