git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3042 35acf78f-673a-0410-8e92-d51de3d6d3f4

10 files changed, 1371 insertions, 153 deletions

diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h
index 0ed6eed8b..ac3ae4187 100644
--- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h
+++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h
@@ -38,14 +38,14 @@
  * @brief   Enables the PAL subsystem.

  */

 #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

-#define HAL_USE_PAL                 TRUE

+#define HAL_USE_PAL                 FALSE

 #endif

 

 /**

  * @brief   Enables the ADC subsystem.

  */

 #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

-#define HAL_USE_ADC                 TRUE

+#define HAL_USE_ADC                 FALSE

 #endif

 

 /**

@@ -94,7 +94,7 @@
  * @brief   Enables the PWM subsystem.

  */

 #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

-#define HAL_USE_PWM                 TRUE

+#define HAL_USE_PWM                 FALSE

 #endif

 

 /**

@@ -108,7 +108,7 @@
  * @brief   Enables the SERIAL subsystem.

  */

 #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

-#define HAL_USE_SERIAL              TRUE

+#define HAL_USE_SERIAL              FALSE

 #endif

 

 /**

@@ -122,7 +122,7 @@
  * @brief   Enables the SPI subsystem.

  */

 #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

-#define HAL_USE_SPI                 TRUE

+#define HAL_USE_SPI                 FALSE

 #endif

 

 /**

diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c
index ff9c4ec70..a56f81efa 100644
--- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c
+++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c
@@ -22,135 +22,6 @@
 #include "hal.h"

 #include "test.h"

 

-static void pwmpcb(PWMDriver *pwmp);

-static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n);

-static void spicb(SPIDriver *spip);

-

-/* Total number of channels to be sampled by a single ADC operation.*/

-#define ADC_GRP1_NUM_CHANNELS   2

-

-/* Depth of the conversion buffer, channels are sampled four times each.*/

-#define ADC_GRP1_BUF_DEPTH      4

-

-/*

- * ADC samples buffer.

- */

-static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];

-

-/*

- * ADC conversion group.

- * Mode:        Linear buffer, 4 samples of 2 channels, SW triggered.

- * Channels:    IN10   (41.5 cycles sample time)

- *              Sensor (239.5 cycles sample time)

- */

-static const ADCConversionGroup adcgrpcfg = {

-  FALSE,

-  ADC_GRP1_NUM_CHANNELS,

-  adccb,

-  /* HW dependent part.*/

-  0,

-  ADC_CR2_TSVREFE,

-  ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5),

-  0,

-  ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),

-  0,

-  ADC_SQR3_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR)

-};

-

-/*

- * PWM configuration structure.

- * Cyclic callback enabled, channels 3 and 4 enabled without callbacks,

- * the active state is a logic one.

- */

-static PWMConfig pwmcfg = {

-  10000,                                    /* 10KHz PWM clock frequency.   */

-  10000,                                    /* PWM period 1S (in ticks).    */

-  pwmpcb,

-  {

-    {PWM_OUTPUT_DISABLED, NULL},

-    {PWM_OUTPUT_DISABLED, NULL},

-    {PWM_OUTPUT_ACTIVE_HIGH, NULL},

-    {PWM_OUTPUT_ACTIVE_HIGH, NULL}

-  },

-  /* HW dependent part.*/

-  0,

-#if STM32_PWM_USE_ADVANCED

-  0

-#endif

-};

-

-/*

- * SPI configuration structure.

- * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first.

- * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA.

- */

-static const SPIConfig spicfg = {

-  spicb,

-  /* HW dependent part.*/

-  GPIOA,

-  GPIOA_SPI1NSS,

-  SPI_CR1_DFF

-};

-

-/*

- * PWM cyclic callback.

- * A new ADC conversion is started.

- */

-static void pwmpcb(PWMDriver *pwmp) {

-

-  (void)pwmp;

-

-  /* Starts an asynchronous ADC conversion operation, the conversion

-     will be executed in parallel to the current PWM cycle and will

-     terminate before the next PWM cycle.*/

-  chSysLockFromIsr();

-  adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH);

-  chSysUnlockFromIsr();

-}

-

-/*

- * ADC end conversion callback.

- * The PWM channels are reprogrammed using the latest ADC samples.

- * The latest samples are transmitted into a single SPI transaction.

- */

-void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) {

-

-  (void) buffer; (void) n;

-  /* Note, only in the ADC_COMPLETE state because the ADC driver fires an

-     intermediate callback when the buffer is half full.*/

-  if (adcp->state == ADC_COMPLETE) {

-    adcsample_t avg_ch1, avg_ch2;

-

-    /* Calculates the average values from the ADC samples.*/

-    avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4;

-    avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4;

-

-    chSysLockFromIsr();

-

-    /* Changes the channels pulse width, the change will be effective

-       starting from the next cycle.*/

-    pwmEnableChannelI(&PWMD3, 2, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch1));

-    pwmEnableChannelI(&PWMD3, 3, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch2));

-

-    /* SPI slave selection and transmission start.*/

-    spiSelectI(&SPID1);

-    spiStartSendI(&SPID1, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples);

-

-    chSysUnlockFromIsr();

-  }

-}

-

-/*

- * SPI end transfer callback.

- */

-static void spicb(SPIDriver *spip) {

-

-  /* On transfer end just releases the slave select line.*/

-  chSysLockFromIsr();

-  spiUnselectI(spip);

-  chSysUnlockFromIsr();

-}

-

 /*

  * This is a periodic thread that does absolutely nothing except increasing

  * a seconds counter.

@@ -184,27 +55,27 @@ int main(void) {
   /*

    * Activates the serial driver 1 using the driver default configuration.

    */

-  sdStart(&SD1, NULL);

+//  sdStart(&SD1, NULL);

 

   /*

    * If the user button is pressed after the reset then the test suite is

    * executed immediately before activating the various device drivers in

    * order to not alter the benchmark scores.

    */

-  if (palReadPad(GPIOA, GPIOA_BUTTON))

-    TestThread(&SD1);

+//  if (palReadPad(GPIOA, GPIOA_BUTTON))

+//    TestThread(&SD1);

 

   /*

    * Initializes the SPI driver 1.

    */

-  spiStart(&SPID1, &spicfg);

+//  spiStart(&SPID1, &spicfg);

 

   /*

    * Initializes the ADC driver 1.

    * The pin PC0 on the port GPIOC is programmed as analog input.

    */

-  adcStart(&ADCD1, NULL);

-  palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG);

+//  adcStart(&ADCD1, NULL);

+//  palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG);

 

   /*

    * Initializes the PWM driver 1, re-routes the TIM3 outputs, programs the

@@ -212,10 +83,10 @@ int main(void) {
    * Note, the AFIO access routes the TIM3 output pins on the PC6...PC9

    * where the LEDs are connected.

    */

-  pwmStart(&PWMD3, &pwmcfg);

-  AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_0 | AFIO_MAPR_TIM3_REMAP_1;

-  palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4),

-                  PAL_MODE_STM32_ALTERNATE_PUSHPULL);

+//  pwmStart(&PWMD3, &pwmcfg);

+//  AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_0 | AFIO_MAPR_TIM3_REMAP_1;

+//  palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4),

+//                  PAL_MODE_STM32_ALTERNATE_PUSHPULL);

 

   /*

    * Creates the example thread.

@@ -229,8 +100,8 @@ int main(void) {
    * driver 1.

    */

   while (TRUE) {

-    if (palReadPad(GPIOA, GPIOA_BUTTON))

-      TestThread(&SD1);

+//    if (palReadPad(GPIOA, GPIOA_BUTTON))

+//      TestThread(&SD1);

     chThdSleepMilliseconds(500);

   }

 }

diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h
index 0461fd201..e063a7cb7 100644
--- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h
+++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h
@@ -19,7 +19,7 @@
 */

 

 /*

- * STM32 drivers configuration.

+ * STM32L1xx drivers configuration.

  * The following settings override the default settings present in

  * the various device driver implementation headers.

  * Note that the settings for each driver only have effect if the whole

@@ -35,14 +35,15 @@
 /*

  * HAL driver system settings.

  */

+#define STM32_VOS                           STM32_VOS_1P8

+#define STM32_MSIRANGE                      STM32_MSIRANGE_2M

 #define STM32_SW                            STM32_SW_PLL

-#define STM32_PLLSRC                        STM32_PLLSRC_HSE

-#define STM32_PLLXTPRE                      STM32_PLLXTPRE_DIV1

-#define STM32_PLLMUL_VALUE                  3

+#define STM32_PLLSRC                        STM32_PLLSRC_HSI

+#define STM32_PLLMUL_VALUE                  6

+#define STM32_PLLDIV_VALUE                  3

 #define STM32_HPRE                          STM32_HPRE_DIV1

 #define STM32_PPRE1                         STM32_PPRE1_DIV1

 #define STM32_PPRE2                         STM32_PPRE2_DIV1

-#define STM32_ADCPRE                        STM32_ADCPRE_DIV2

 #define STM32_MCO                           STM32_MCO_NOCLOCK

 

 /*

diff --git a/os/hal/platforms/STM32/hal_lld_f103.h b/os/hal/platforms/STM32/hal_lld_f103.h
index 1f11da249..4421663a0 100644
--- a/os/hal/platforms/STM32/hal_lld_f103.h
+++ b/os/hal/platforms/STM32/hal_lld_f103.h
@@ -260,6 +260,7 @@
     (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)

 #error "invalid STM32_PLLXTPRE value specified"

 #endif

+

 /**

  * @brief   PLLMUL field.

  */

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
new file mode 100644
index 000000000..956ad9fcc
--- /dev/null
+++ b/os/hal/platforms/STM32L1xx/hal_lld.c
@@ -0,0 +1,97 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    STM32L1xx/hal_lld.c

+ * @brief   STM32L1xx HAL subsystem low level driver source.

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+#define AIRCR_VECTKEY           0x05FA0000

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level HAL driver initialization.

+ *

+ * @notapi

+ */

+void hal_lld_init(void) {

+

+  /* Reset of all peripherals.*/

+  RCC->APB1RSTR = 0xFFFFFFFF;

+  RCC->APB2RSTR = 0xFFFFFFFF;

+  RCC->APB1RSTR = 0;

+  RCC->APB2RSTR = 0;

+

+  /* SysTick initialization using the system clock.*/

+  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

+  SysTick->VAL = 0;

+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

+                  SysTick_CTRL_ENABLE_Msk |

+                  SysTick_CTRL_TICKINT_Msk;

+

+#if defined(STM32_DMA_REQUIRED)

+  dmaInit();

+#endif

+}

+

+/**

+ * @brief   STM32L1xx clocks and PLL initialization.

+ * @note    All the involved constants come from the file @p board.h.

+ * @note    This function must be invoked only after the system reset.

+ *

+ * @special

+ */

+#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)

+/*

+ * Clocks initialization for the LD, MD and HD sub-families.

+ */

+void stm32_clock_init(void) {

+

+}

+#else

+void stm32_clock_init(void) {}

+#endif

+

+/** @} */

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
new file mode 100644
index 000000000..4559d7fb8
--- /dev/null
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -0,0 +1,499 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    STM32L1xx/hal_lld.h

+ * @brief   STM32L1xx HAL subsystem low level driver header.

+ * @pre     This module requires the following macros to be defined in the

+ *          @p board.h file:

+ *          - STM32_LSECLK.

+ *          - STM32_HSECLK.

+ *          .

+ *          One of the following macros must also be defined:

+ *          - STM32L1XX_MD for Ultra Low Power Medium-density devices.

+ *          .

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#ifndef _HAL_LLD_H_

+#define _HAL_LLD_H_

+

+/* Tricks required to make the TRUE/FALSE declaration inside the library

+   compatible.*/

+#undef FALSE

+#undef TRUE

+#include "stm32l1xx.h"

+#define FALSE 0

+#define TRUE (!FALSE)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Platform name.

+ */

+#define PLATFORM_NAME           "STM32L Ultra Low Power Medium Density"

+

+#define STM32_HSICLK            16000000    /**< High speed internal clock. */

+#define STM32_LSICLK            38000       /**< Low speed internal clock.  */

+

+/* PWR_CR register bits definitions.*/

+#define STM32_VOS_1P2           (1 << 11)   /**< Core voltage 1.2 Volts.    */

+#define STM32_VOS_1P5           (2 << 11)   /**< Core voltage 1.5 Volts.    */

+#define STM32_VOS_1P8           (3 << 11)   /**< Core voltage 1.8 Volts.    */

+

+/* RCC_CFGR register bits definitions.*/

+#define STM32_SW_MSI            (0 << 0)    /**< SYSCLK source is MSI.      */

+#define STM32_SW_HSI            (1 << 0)    /**< SYSCLK source is HSI.      */

+#define STM32_SW_HSE            (2 << 0)    /**< SYSCLK source is HSE.      */

+#define STM32_SW_PLL            (3 << 0)    /**< SYSCLK source is PLL.      */

+

+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */

+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */

+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */

+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */

+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */

+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */

+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */

+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */

+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */

+

+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */

+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */

+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */

+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */

+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */

+

+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */

+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */

+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */

+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */

+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */

+

+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */

+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */

+

+#define STM32_MCO_NOCLOCK       (0 << 24)   /**< No clock on MCO pin.       */

+#define STM32_MCO_SYSCLK        (1 << 24)   /**< SYSCLK on MCO pin.         */

+#define STM32_MCO_HSI           (2 << 24)   /**< HSI clock on MCO pin.      */

+#define STM32_MCO_MSI           (3 << 24)   /**< MSI clock on MCO pin.      */

+#define STM32_MCO_HSE           (4 << 24)   /**< HSE clock on MCO pin.      */

+#define STM32_MCO_PLL           (5 << 24)   /**< PLL clock on MCO pin.      */

+#define STM32_MCO_LSI           (6 << 24)   /**< LSI clock on MCO pin.      */

+#define STM32_MCO_LSE           (7 << 24)   /**< LSE clock on MCO pin.      */

+

+/* RCC_ICSCR register bits definitions.*/

+#define STM32_MSIRANGE_64K      (0 << 13)   /* 64KHz nominal.               */

+#define STM32_MSIRANGE_128K     (1 << 13)   /* 128KHz nominal.              */

+#define STM32_MSIRANGE_256K     (2 << 13)   /* 256KHz nominal.              */

+#define STM32_MSIRANGE_512K     (3 << 13)   /* 512KHz nominal.              */

+#define STM32_MSIRANGE_1M       (4 << 13)   /* 1MHz nominal.                */

+#define STM32_MSIRANGE_2M       (5 << 13)   /* 2MHz nominal.                */

+#define STM32_MSIRANGE_4M       (6 << 13)   /* 4MHz nominal.                */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Core voltage selection.

+ * @note    This setting affects all the performance and clock related

+ *          settings, the maximum performance is only obtainable selecting

+ *          the maximum voltage.

+ */

+#if !defined(STM32_VOS) || defined(__DOXYGEN__)

+#define STM32_VOS                   STM32_VOS_1P8

+#endif

+

+/**

+ * @brief   MSI frequency setting.

+ */

+#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)

+#define STM32_MSIRANGE              STM32_MSIRANGE_2M

+#endif

+

+/**

+ * @brief   Main clock source selection.

+ * @note    If the selected clock source is not the PLL then the PLL is not

+ *          initialized and started.

+ * @note    The default value is calculated for a 32MHz system clock from

+ *          the internal 16MHz HSI clock.

+ */

+#if !defined(STM32_SW) || defined(__DOXYGEN__)

+#define STM32_SW                    STM32_SW_PLL

+#endif

+

+/**

+ * @brief   Clock source for the PLL.

+ * @note    This setting has only effect if the PLL is selected as the

+ *          system clock source.

+ * @note    The default value is calculated for a 32MHz system clock from

+ *          the internal 16MHz HSI clock.

+ */

+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)

+#define STM32_PLLSRC                STM32_PLLSRC_HSI

+#endif

+

+/**

+ * @brief   PLL multiplier value.

+ * @note    The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.

+ * @note    The default value is calculated for a 32MHz system clock from

+ *          the internal 16MHz HSI clock.

+ */

+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLMUL_VALUE          6

+#endif

+

+/**

+ * @brief   PLL divider value.

+ * @note    The allowed values are 2, 3, 4.

+ * @note    The default value is calculated for a 32MHz system clock from

+ *          the internal 16MHz HSI clock.

+ */

+#if !defined(STM32_DIVMUL_VALUE) || defined(__DOXYGEN__)

+#define STM32_DIVMUL_VALUE          3

+#endif

+

+/**

+ * @brief   AHB prescaler value.

+ * @note    The default value is calculated for a 32MHz system clock from

+ *          the internal 16MHz HSI clock.

+ */

+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)

+#define STM32_HPRE                  STM32_HPRE_DIV1

+#endif

+

+/**

+ * @brief   APB1 prescaler value.

+ */

+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)

+#define STM32_PPRE1                 STM32_PPRE1_DIV1

+#endif

+

+/**

+ * @brief   APB2 prescaler value.

+ */

+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)

+#define STM32_PPRE2                 STM32_PPRE2_DIV1

+#endif

+

+/**

+ * @brief   MCO pin setting.

+ */

+#if !defined(STM32_MCO) || defined(__DOXYGEN__)

+#define STM32_MCO                   STM32_MCO_NOCLOCK

+#endif

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/* Voltage related limits.*/

+#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)

+/**

+ * @brief   Maximum HSECLK at current voltage setting.

+ */

+#define STM32_HSECLK_MAX            32000000

+

+/**

+ * @brief   Maximum SYSCLK at current voltage setting.

+ */

+#define STM32_SYSCLK_MAX            32000000

+

+/**

+ * @brief   Maximum PLLCLKOUT at current voltage setting.

+ */

+#define STM32_PLLCLKOUT_MAX         96000000

+

+/**

+ * @brief   Maximum frequency not requiring a wait state for flash accesses.

+ */

+#define STM32_0WS_THRESHOLD         16000000

+

+/**

+ * @brief   HSI availability at current voltage settings.

+ */

+#define STM32_HSI_AVAILABLE         TRUE

+

+#elif STM32_VOS == STM32_VOS_1P5

+#define STM32_HSECLK_MAX            16000000

+#define STM32_SYSCLK_MAX            16000000

+#define STM32_PLLCLKOUT_MAX         48000000

+#define STM32_0WS_THRESHOLD         8000000

+#define STM32_HSI_AVAILABLE         TRUE

+#elif STM32_VOS == STM32_VOS_1P2

+#define STM32_HSECLK_MAX            4000000

+#define STM32_SYSCLK_MAX            4000000

+#define STM32_PLLCLKOUT_MAX         24000000

+#define STM32_0WS_THRESHOLD         2000000

+#define STM32_HSI_AVAILABLE         FALSE

+#else

+#error "invalid STM32_VOS value specified"

+#endif

+

+#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)

+#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"

+#endif

+

+#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)

+#error "STM32_LSECLK outside acceptable range (1...1000KHz)"

+#endif

+

+/**

+ * @brief   PLLMUL field.

+ */

+#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)

+#define STM32_PLLMUL                (0 << 18)

+#elif STM32_PLLMUL_VALUE == 4

+#define STM32_PLLMUL                (1 << 18)

+#elif STM32_PLLMUL_VALUE == 6

+#define STM32_PLLMUL                (2 << 18)

+#elif STM32_PLLMUL_VALUE == 8

+#define STM32_PLLMUL                (3 << 18)

+#elif STM32_PLLMUL_VALUE == 12

+#define STM32_PLLMUL                (4 << 18)

+#elif STM32_PLLMUL_VALUE == 16

+#define STM32_PLLMUL                (5 << 18)

+#elif STM32_PLLMUL_VALUE == 24

+#define STM32_PLLMUL                (6 << 18)

+#elif STM32_PLLMUL_VALUE == 32

+#define STM32_PLLMUL                (7 << 18)

+#elif STM32_PLLMUL_VALUE == 48

+#define STM32_PLLMUL                (8 << 18)

+#else

+#error "invalid STM32_PLLMUL_VALUE value specified"

+#endif

+

+/**

+ * @brief   PLLDIV field.

+ */

+#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)

+#define STM32_PLLDIV                (1 << 22)

+#elif STM32_PLLDIV_VALUE == 3

+#define STM32_PLLDIV                (2 << 22)

+#elif STM32_PLLDIV_VALUE == 4

+#define STM32_PLLDIV                (3 << 22)

+#else

+#error "invalid STM32_PLLDIV_VALUE value specified"

+#endif

+

+/**

+ * @brief   PLL input clock frequency.

+ */

+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

+#define STM32_PLLCLKIN              STM32_HSECLK

+#elif STM32_PLLSRC == STM32_PLLSRC_HSI

+/* Verifies the HSI clock availability if the PLL used and requires HSI as

+   input.*/

+#if !STM32_HSI_AVAILABLE && (STM32_SW == STM32_SW_PLL)

+#error "HSI clock not available in low voltage mode (1.2V)."

+#endif

+#define STM32_PLLCLKIN              STM32_HSICLK

+#else

+#error "invalid STM32_PLLSRC value specified"

+#endif

+

+/* PLL input frequency range check.*/

+#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)

+#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"

+#endif

+

+/**

+ * @brief   PLL VCO frequency.

+ */

+#define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)

+

+/* PLL output frequency range check.*/

+#if (STM32_PLLVCO < 6000000) || (STM32_PLLVCO > 96000000)

+#error "STM32_PLLVCO outside acceptable range (6...96MHz)"

+#endif

+

+/**

+ * @brief   PLL output clock frequency.

+ */

+#define STM32_PLLCLKOUT             (STM32_PLLVCO / STM32_PLLDIV_VALUE)

+

+/* PLL output frequency range check.*/

+#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)

+#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"

+#endif

+

+/**

+ * @brief   System clock source.

+ */

+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)

+#define STM32_SYSCLK                STM32_PLLCLKOUT

+#elif (STM32_SW == STM32_SW_MSI)

+#define STM32_SYSCLK                STM32_MSICLK

+#elif (STM32_SW == STM32_SW_HSI)

+#define STM32_SYSCLK                STM32_HSICLK

+#elif (STM32_SW == STM32_SW_HSE)

+#define STM32_SYSCLK                STM32_HSECLK

+#else

+#error "invalid STM32_SYSCLK_SW value specified"

+#endif

+

+/* Check on the system clock.*/

+#if STM32_SYSCLK > STM32_SYSCLK_MAX

+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"

+#endif

+

+/**

+ * @brief   AHB frequency.

+ */

+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)

+#define STM32_HCLK                  (STM32_SYSCLK / 1)

+#elif STM32_HPRE == STM32_HPRE_DIV2

+#define STM32_HCLK                  (STM32_SYSCLK / 2)

+#elif STM32_HPRE == STM32_HPRE_DIV4

+#define STM32_HCLK                  (STM32_SYSCLK / 4)

+#elif STM32_HPRE == STM32_HPRE_DIV8

+#define STM32_HCLK                  (STM32_SYSCLK / 8)

+#elif STM32_HPRE == STM32_HPRE_DIV16

+#define STM32_HCLK                  (STM32_SYSCLK / 16)

+#elif STM32_HPRE == STM32_HPRE_DIV64

+#define STM32_HCLK                  (STM32_SYSCLK / 64)

+#elif STM32_HPRE == STM32_HPRE_DIV128

+#define STM32_HCLK                  (STM32_SYSCLK / 128)

+#elif STM32_HPRE == STM32_HPRE_DIV256

+#define STM32_HCLK                  (STM32_SYSCLK / 256)

+#elif STM32_HPRE == STM32_HPRE_DIV512

+#define STM32_HCLK                  (STM32_SYSCLK / 512)

+#else

+#error "invalid STM32_HPRE value specified"

+#endif

+

+/* AHB frequency check.*/

+#if STM32_HCLK > STM32_SYSCLK_MAX

+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"

+#endif

+

+/**

+ * @brief   APB1 frequency.

+ */

+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK1                 (STM32_HCLK / 1)

+#elif STM32_PPRE1 == STM32_PPRE1_DIV2

+#define STM32_PCLK1                 (STM32_HCLK / 2)

+#elif STM32_PPRE1 == STM32_PPRE1_DIV4

+#define STM32_PCLK1                 (STM32_HCLK / 4)

+#elif STM32_PPRE1 == STM32_PPRE1_DIV8

+#define STM32_PCLK1                 (STM32_HCLK / 8)

+#elif STM32_PPRE1 == STM32_PPRE1_DIV16

+#define STM32_PCLK1                 (STM32_HCLK / 16)

+#else

+#error "invalid STM32_PPRE1 value specified"

+#endif

+

+/* APB1 frequency check.*/

+#if STM32_PCLK2 > STM32_SYSCLK_MAX

+#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)"

+#endif

+

+/**

+ * @brief   APB2 frequency.

+ */

+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

+#define STM32_PCLK2                 (STM32_HCLK / 1)

+#elif STM32_PPRE2 == STM32_PPRE2_DIV2

+#define STM32_PCLK2                 (STM32_HCLK / 2)

+#elif STM32_PPRE2 == STM32_PPRE2_DIV4

+#define STM32_PCLK2                 (STM32_HCLK / 4)

+#elif STM32_PPRE2 == STM32_PPRE2_DIV8

+#define STM32_PCLK2                 (STM32_HCLK / 8)

+#elif STM32_PPRE2 == STM32_PPRE2_DIV16

+#define STM32_PCLK2                 (STM32_HCLK / 16)

+#else

+#error "invalid STM32_PPRE2 value specified"

+#endif

+

+/* APB2 frequency check.*/

+#if STM32_PCLK2 > STM32_SYSCLK_MAX

+#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)"

+#endif

+

+/**

+ * @brief   ADC frequency.

+ */

+#define STM32_ADCCLK                STM32_HSICLK

+

+/**

+ * @brief   USB frequency.

+ */

+#define STM32_USBCLK                (STM32_PLLVCO / 2)

+

+/**

+ * @brief   Timers 2, 3, 4, 6, 7 clock.

+ */

+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)

+#else

+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)

+#endif

+

+/**

+ * @brief   Timers 9, 10, 11 clock.

+ */

+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)

+#else

+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)

+#endif

+

+/**

+ * @brief   Flash settings.

+ */

+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)

+#define STM32_FLASHBITS1            0x00000000

+#else

+#define STM32_FLASHBITS1            0x00000004

+#define STM32_FLASHBITS2            0x00000003

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+/* STM32 DMA support code.*/

+#include "stm32_dma.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void hal_lld_init(void);

+  void stm32_clock_init(void);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _HAL_LLD_H_ */

+

+/** @} */

diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk
index df1229bbc..f870811fc 100644
--- a/os/hal/platforms/STM32L1xx/platform.mk
+++ b/os/hal/platforms/STM32L1xx/platform.mk
@@ -1,5 +1,6 @@
 # List of all the STM32 platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c

 

 # Required include directories

 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32L1xx

diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c
new file mode 100644
index 000000000..2232df448
--- /dev/null
+++ b/os/hal/platforms/STM32L1xx/stm32_dma.c
@@ -0,0 +1,468 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    stm32_dma.c

+ * @brief   STM32 DMA helper driver code.

+ *

+ * @addtogroup STM32_DMA

+ * @details DMA sharing helper driver. In the STM32 the DMA channels are a

+ *          shared resource, this driver allows to allocate and free DMA

+ *          channels at runtime in order to allow all the other device

+ *          drivers to coordinate the access to the resource.

+ * @note    The DMA ISR handlers are all declared into this module because

+ *          sharing, the various device drivers can associate a callback to

+ *          IRSs when allocating channels.

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   DMA ISR redirector type.

+ */

+typedef struct {

+  stm32_dmaisr_t        dmaisrfunc;

+  void                  *dmaisrparam;

+} dma_isr_redir_t;

+

+static uint32_t dmamsk1;

+static dma_isr_redir_t dma1[7];

+

+#if STM32_HAS_DMA2

+static uint32_t dmamsk2;

+static dma_isr_redir_t dma2[5];

+#endif

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   DMA1 channel 1 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_1 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_1);

+  if (dma1[0].dmaisrfunc)

+    dma1[0].dmaisrfunc(dma1[0].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 2 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_2 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_2);

+  if (dma1[1].dmaisrfunc)

+    dma1[1].dmaisrfunc(dma1[1].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 3 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_3 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_3);

+  if (dma1[2].dmaisrfunc)

+    dma1[2].dmaisrfunc(dma1[2].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 4 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_4 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_4);

+  if (dma1[3].dmaisrfunc)

+    dma1[3].dmaisrfunc(dma1[3].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 5 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_5 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_5);

+  if (dma1[4].dmaisrfunc)

+    dma1[4].dmaisrfunc(dma1[4].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 6 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_6 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_6);

+  if (dma1[5].dmaisrfunc)

+    dma1[5].dmaisrfunc(dma1[5].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 channel 7 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_7 * 4);

+  dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_7);

+  if (dma1[6].dmaisrfunc)

+    dma1[6].dmaisrfunc(dma1[6].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)

+/**

+ * @brief   DMA2 channel 1 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_1 * 4);

+  dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_1);

+  if (dma2[0].dmaisrfunc)

+    dma2[0].dmaisrfunc(dma2[0].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 channel 2 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_2 * 4);

+  dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_2);

+  if (dma2[1].dmaisrfunc)

+    dma2[1].dmaisrfunc(dma2[1].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 channel 3 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_3 * 4);

+  dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_3);

+  if (dma2[2].dmaisrfunc)

+    dma2[2].dmaisrfunc(dma2[2].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)

+/**

+ * @brief   DMA2 channel 4 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4);

+  dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_4);

+  if (dma2[3].dmaisrfunc)

+    dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 channel 5 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4);

+  dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5);

+  if (dma2[4].dmaisrfunc)

+    dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr);

+

+  CH_IRQ_EPILOGUE();

+}

+

+#else /* !STM32F10X_CL */

+/**

+ * @brief   DMA2 channels 4 and 5 shared interrupt handler.

+ * @note    This IRQ is shared between DMA2 channels 4 and 5 so it is a

+ *          bit less efficient because an extra check.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {

+  uint32_t isr;

+

+  CH_IRQ_PROLOGUE();

+

+  /* Check on channel 4.*/

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4);

+  if (isr & DMA_ISR_GIF1) {

+    dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5);

+    if (dma2[3].dmaisrfunc)

+      dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr);

+  }

+

+  /* Check on channel 5.*/

+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4);

+  if (isr & DMA_ISR_GIF1) {

+    dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5);

+    if (dma2[4].dmaisrfunc)

+      dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr);

+  }

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* !STM32F10X_CL */

+#endif /* STM32_HAS_DMA2 */

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   STM32 DMA helper initialization.

+ *

+ * @init

+ */

+void dmaInit(void) {

+  int i;

+

+  dmamsk1 = 0;

+  for (i = STM32_DMA_CHANNEL_7; i >= STM32_DMA_CHANNEL_1; i--) {

+    dmaDisableChannel(STM32_DMA1, i);

+    dma1[i].dmaisrfunc = NULL;

+  }

+  STM32_DMA1->IFCR = 0xFFFFFFFF;

+#if STM32_HAS_DMA2

+  dmamsk2 = 0;

+  for (i = STM32_DMA_CHANNEL_5; i >= STM32_DMA_CHANNEL_1; i--) {

+    dmaDisableChannel(STM32_DMA2, i);

+    dma2[i].dmaisrfunc = NULL;

+  }

+  STM32_DMA1->IFCR = 0xFFFFFFFF;

+#endif

+}

+

+/**

+ * @brief   Allocates a DMA channel.

+ * @details The channel is allocated and, if required, the DMA clock enabled.

+ *          Trying to allocate a channel already allocated is an illegal

+ *          operation and is trapped if assertions are enabled.

+ * @pre     The channel must not be already in use.

+ * @post    The channel is allocated and the default ISR handler redirected

+ *          to the specified function.

+ * @post    The channel must be freed using @p dmaRelease() before it can

+ *          be reused with another peripheral.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dma       DMA controller id

+ * @param[in] channel   requested channel id

+ * @param[in] func      handling function pointer, can be @p NULL

+ * @param[in] param     a parameter to be passed to the handling function

+ * @return              The operation status.

+ * @retval FALSE        operation successfully allocated.

+ * @retval TRUE         the channel was already in use.

+ *

+ * @special

+ */

+void dmaAllocate(uint32_t dma, uint32_t channel,

+                 stm32_dmaisr_t func, void *param) {

+

+  chDbgCheck(func != NULL, "dmaAllocate");

+

+#if STM32_HAS_DMA2

+  switch (dma) {

+  case STM32_DMA1_ID:

+#else

+  (void)dma;

+#endif

+    /* Check if the channel is already taken.*/

+    chDbgAssert((dmamsk1 & (1 << channel)) == 0,

+                "dmaAllocate(), #1", "already allocated");

+

+    /* If the DMA unit was idle then the clock is enabled.*/

+    if (dmamsk1 == 0) {

+      RCC->AHBENR |= RCC_AHBENR_DMA1EN;

+      DMA1->IFCR = 0x0FFFFFFF;

+    }

+

+    dmamsk1 |= 1 << channel;

+    dma1[channel].dmaisrfunc  = func;

+    dma1[channel].dmaisrparam = param;

+#if STM32_HAS_DMA2

+    break;

+  case STM32_DMA2_ID:

+    /* Check if the channel is already taken.*/

+    chDbgAssert((dmamsk2 & (1 << channel)) == 0,

+                "dmaAllocate(), #2", "already allocated");

+

+    /* If the DMA unit was idle then the clock is enabled.*/

+    if (dmamsk2 == 0) {

+      RCC->AHBENR |= RCC_AHBENR_DMA2EN;

+      DMA2->IFCR = 0x0FFFFFFF;

+    }

+

+    dmamsk2 |= 1 << channel;

+    dma2[channel].dmaisrfunc  = func;

+    dma2[channel].dmaisrparam = param;

+    break;

+  }

+#endif

+}

+

+/**

+ * @brief   Releases a DMA channel.

+ * @details The channel is freed and, if required, the DMA clock disabled.

+ *          Trying to release a unallocated channel is an illegal operation

+ *          and is trapped if assertions are enabled.

+ * @pre     The channel must have been allocated using @p dmaRequest().

+ * @post    The channel is again available.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dma       DMA controller id

+ * @param[in] channel   requested channel id

+ *

+ * @special

+ */

+void dmaRelease(uint32_t dma, uint32_t channel) {

+

+#if STM32_HAS_DMA2

+  switch (dma) {

+  case STM32_DMA1_ID:

+#else

+  (void)dma;

+#endif

+    /* Check if the channel is not taken.*/

+    chDbgAssert((dmamsk1 & (1 << channel)) != 0,

+                "dmaRelease(), #1", "not allocated");

+

+    dma1[channel].dmaisrfunc = NULL;

+    dmamsk1 &= ~(1 << channel);

+    if (dmamsk1 == 0)

+      RCC->AHBENR &= ~RCC_AHBENR_DMA1EN;

+#if STM32_HAS_DMA2

+    break;

+  case STM32_DMA2_ID:

+    /* Check if the channel is not taken.*/

+    chDbgAssert((dmamsk2 & (1 << channel)) != 0,

+                "dmaRelease(), #2", "not allocated");

+

+    dma2[channel].dmaisrfunc = NULL;

+    dmamsk2 &= ~(1 << channel);

+    if (dmamsk2 == 0)

+      RCC->AHBENR &= ~RCC_AHBENR_DMA2EN;

+    break;

+  }

+#endif

+}

+

+#endif /* STM32_DMA_REQUIRED */

+

+/** @} */

diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h
new file mode 100644
index 000000000..66a2f8c69
--- /dev/null
+++ b/os/hal/platforms/STM32L1xx/stm32_dma.h
@@ -0,0 +1,280 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    stm32_dma.h

+ * @brief   STM32 DMA helper driver header.

+ * @note    This file requires definitions from the ST STM32 header file

+ *          stm3232f10x.h.

+ *

+ * @addtogroup STM32_DMA

+ * @{

+ */

+

+#ifndef _STM32_DMA_H_

+#define _STM32_DMA_H_

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/** @brief DMA1 identifier.*/

+#define STM32_DMA1_ID 0

+

+/** @brief DMA2 identifier.*/

+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)

+#define STM32_DMA2_ID 1

+#endif

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   STM32 DMA channel memory structure type.

+ */

+typedef struct {

+  volatile uint32_t     CCR;

+  volatile uint32_t     CNDTR;

+  volatile uint32_t     CPAR;

+  volatile uint32_t     CMAR;

+  volatile uint32_t     dummy;

+} stm32_dma_channel_t;

+

+/**

+ * @brief   STM32 DMA subsystem memory structure type.

+ * @note    This structure has been redefined here because it is convenient to

+ *          have the channels organized as an array, the ST header does not

+ *          do that.

+ */

+typedef struct {

+  volatile uint32_t     ISR;

+  volatile uint32_t     IFCR;

+  stm32_dma_channel_t   channels[7];

+} stm32_dma_t;

+

+/**

+ * @brief   STM32 DMA ISR function type.

+ *

+ * @param[in] p         parameter for the registered function

+ * @param[in] flags     pre-shifted content of the ISR register

+ */

+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/** DMA1 registers block numeric address.*/

+#define STM32_DMA1_BASE         (AHBPERIPH_BASE + 0x0000)

+/** Pointer to the DMA1 registers block.*/

+#define STM32_DMA1              ((stm32_dma_t *)STM32_DMA1_BASE)

+/** Pointer to the DMA1 channel 1 registers block.*/

+#define STM32_DMA1_CH1          (&STM32_DMA1->channels[0])

+/** Pointer to the DMA1 channel 2 registers block.*/

+#define STM32_DMA1_CH2          (&STM32_DMA1->channels[1])

+/** Pointer to the DMA1 channel 3 registers block.*/

+#define STM32_DMA1_CH3          (&STM32_DMA1->channels[2])

+/** Pointer to the DMA1 channel 4 registers block.*/

+#define STM32_DMA1_CH4          (&STM32_DMA1->channels[3])

+/** Pointer to the DMA1 channel 5 registers block.*/

+#define STM32_DMA1_CH5          (&STM32_DMA1->channels[4])

+/** Pointer to the DMA1 channel 6 registers block.*/

+#define STM32_DMA1_CH6          (&STM32_DMA1->channels[5])

+/** Pointer to the DMA1 channel 7 registers block.*/

+#define STM32_DMA1_CH7          (&STM32_DMA1->channels[6])

+

+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)

+/** DMA2 registers block numeric address.*/

+#define STM32_DMA2_BASE         (AHBPERIPH_BASE + 0x0400)

+/** Pointer to the DMA2 registers block.*/

+#define STM32_DMA2              ((stm32_dma_t *)STM32_DMA2_BASE)

+/** Pointer to the DMA2 channel 1 registers block.*/

+#define STM32_DMA2_CH1          (&STM32_DMA2->channels[0])

+/** Pointer to the DMA2 channel 2 registers block.*/

+#define STM32_DMA2_CH2          (&STM32_DMA2->channels[1])

+/** Pointer to the DMA2 channel 3 registers block.*/

+#define STM32_DMA2_CH3          (&STM32_DMA2->channels[2])

+/** Pointer to the DMA2 channel 4 registers block.*/

+#define STM32_DMA2_CH4          (&STM32_DMA2->channels[3])

+/** Pointer to the DMA2 channel 5 registers block.*/

+#define STM32_DMA2_CH5          (&STM32_DMA2->channels[4])

+#endif

+

+#define STM32_DMA_CHANNEL_1     0       /**< @brief DMA channel 1.          */

+#define STM32_DMA_CHANNEL_2     1       /**< @brief DMA channel 2.          */

+#define STM32_DMA_CHANNEL_3     2       /**< @brief DMA channel 3.          */

+#define STM32_DMA_CHANNEL_4     3       /**< @brief DMA channel 4.          */

+#define STM32_DMA_CHANNEL_5     4       /**< @brief DMA channel 5.          */

+#define STM32_DMA_CHANNEL_6     5       /**< @brief DMA channel 6.          */

+#define STM32_DMA_CHANNEL_7     6       /**< @brief DMA channel 7.          */

+

+/**

+ * @brief   Associates a peripheral data register to a DMA channel.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmachp    dmachp to a stm32_dma_channel_t structure

+ * @param[in] cpar      value to be written in the CPAR register

+ *

+ * @special

+ */

+#define dmaChannelSetPeripheral(dmachp, cpar) {                             \

+  (dmachp)->CPAR  = (uint32_t)(cpar);                                       \

+}

+

+/**

+ * @brief   DMA channel setup by channel pointer.

+ * @note    This macro does not change the CPAR register because that register

+ *          value does not change frequently, it usually points to a peripheral

+ *          data register.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmachp    dmachp to a stm32_dma_channel_t structure

+ * @param[in] cndtr     value to be written in the CNDTR register

+ * @param[in] cmar      value to be written in the CMAR register

+ * @param[in] ccr       value to be written in the CCR register

+ *

+ * @special

+ */

+#define dmaChannelSetup(dmachp, cndtr, cmar, ccr) {                         \

+  (dmachp)->CNDTR = (uint32_t)(cndtr);                                      \

+  (dmachp)->CMAR  = (uint32_t)(cmar);                                       \

+  (dmachp)->CCR   = (uint32_t)(ccr);                                        \

+}

+

+/**

+ * @brief   DMA channel enable by channel pointer.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmachp    dmachp to a stm32_dma_channel_t structure

+ *

+ * @special

+ */

+#define dmaChannelEnable(dmachp) {                                          \

+  (dmachp)->CCR |= DMA_CCR1_EN;                                             \

+}

+

+

+/**

+ * @brief   DMA channel disable by channel pointer.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmachp    dmachp to a stm32_dma_channel_t structure

+ *

+ * @special

+ */

+#define dmaChannelDisable(dmachp) {                                         \

+  (dmachp)->CCR = 0;                                                        \

+}

+

+/**

+ * @brief   DMA channel setup by channel ID.

+ * @note    This macro does not change the CPAR register because that register

+ *          value does not change frequently, it usually points to a peripheral

+ *          data register.

+ * @note    Channels are numbered from 0 to 6, use the appropriate macro

+ *          as parameter.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmap      pointer to a stm32_dma_t structure

+ * @param[in] ch        channel number

+ * @param[in] cndtr     value to be written in the CNDTR register

+ * @param[in] cmar      value to be written in the CMAR register

+ * @param[in] ccr       value to be written in the CCR register

+ *

+ * @special

+ */

+#define dmaSetupChannel(dmap, ch, cndtr, cmar, ccr) {                       \

+  dmaChannelSetup(&(dmap)->channels[ch], (cndtr), (cmar), (ccr));           \

+}

+

+/**

+ * @brief   DMA channel enable by channel ID.

+ * @note    Channels are numbered from 0 to 6, use the appropriate macro

+ *          as parameter.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmap      pointer to a stm32_dma_t structure

+ * @param[in] ch        channel number

+ *

+ * @special

+ */

+#define dmaEnableChannel(dmap, ch) {                                        \

+  dmaChannelEnable(&(dmap)->channels[ch]);                                  \

+}

+

+/**

+ * @brief   DMA channel disable by channel ID.

+ * @note    Channels are numbered from 0 to 6, use the appropriate macro

+ *          as parameter.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmap      pointer to a stm32_dma_t structure

+ * @param[in] ch        channel number

+ *

+ * @special

+ */

+#define dmaDisableChannel(dmap, ch) {                                       \

+  dmaChannelDisable(&(dmap)->channels[ch]);                                 \

+}

+

+/**

+ * @brief   DMA channel interrupt sources clear.

+ * @details Sets the appropriate CGIF bit into the IFCR register in order to

+ *          withdraw all the pending interrupt bits from the ISR register.

+ * @note    Channels are numbered from 0 to 6, use the appropriate macro

+ *          as parameter.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmap      pointer to a stm32_dma_t structure

+ * @param[in] ch        channel number

+ *

+ * @special

+ */

+#define dmaClearChannel(dmap, ch){                                          \

+  (dmap)->IFCR = 1 << ((ch) * 4);                                           \

+}

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void dmaInit(void);

+  void dmaAllocate(uint32_t dma, uint32_t channel,

+                   stm32_dmaisr_t func, void *param);

+  void dmaRelease(uint32_t dma, uint32_t channel);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _STM32_DMA_H_ */

+

+/** @} */

diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h
index b9fd50aaf..88464e5da 100644
--- a/os/hal/platforms/STM32L1xx/stm32l1xx.h
+++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h
@@ -191,7 +191,7 @@ typedef enum IRQn
   */

 

 #include "core_cm3.h"

-#include "system_stm32l1xx.h"

+/*#include "system_stm32l1xx.h"*/

 #include <stdint.h>

 

 /** @addtogroup Exported_types