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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-19 11:38:40 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-19 11:38:40 +0000 |
| commit | 72858cb49d82d0e04de168f2348c4243c4f50c69 (patch) | |
| tree | f0abce086476968bb9661179b767753c375b00c1 | |
| parent | f6f45f52012c5bd0ab890978737381df08e404a0 (diff) | |
| download | ChibiOS-72858cb49d82d0e04de168f2348c4243c4f50c69.tar.gz ChibiOS-72858cb49d82d0e04de168f2348c4243c4f50c69.tar.bz2 ChibiOS-72858cb49d82d0e04de168f2348c4243c4f50c69.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5265 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | demos/PPC-SPC560B-GCC/mcuconf.h | 4 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/hal_lld.h | 32 |
2 files changed, 18 insertions, 18 deletions
diff --git a/demos/PPC-SPC560B-GCC/mcuconf.h b/demos/PPC-SPC560B-GCC/mcuconf.h index 5eec57f62..2cc803460 100644 --- a/demos/PPC-SPC560B-GCC/mcuconf.h +++ b/demos/PPC-SPC560B-GCC/mcuconf.h @@ -31,11 +31,11 @@ #define SPC5_NO_INIT FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
#define SPC5_DISABLE_WATCHDOG TRUE
-#define SPC5_XOSCDIV_VALUE 1
-#define SPC5_IRCDIV_VALUE 1
#define SPC5_FMPLL0_IDF_VALUE 1
#define SPC5_FMPLL0_NDIV_VALUE 32
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_XOSCDIV_VALUE 1
+#define SPC5_IRCDIV_VALUE 1
#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h index a0294a731..8c4a9a3b4 100644 --- a/os/hal/platforms/SPC560BCxx/hal_lld.h +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -244,22 +244,6 @@ #endif
/**
- * @brief XOSC divider value.
- * @note The allowed range is 1...32.
- */
-#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_XOSCDIV_VALUE 1
-#endif
-
-/**
- * @brief Fast IRC divider value.
- * @note The allowed range is 1...32.
- */
-#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_IRCDIV_VALUE 1
-#endif
-
-/**
* @brief FMPLL0 IDF divider value.
* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/
@@ -284,6 +268,22 @@ #endif
/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
* @brief Peripherals Set 1 clock divider value.
* @note Zero means disabled clock.
*/
|