git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@232 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 105 insertions, 114 deletions

diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile
index 2de43bf20..dc01e39e3 100644
--- a/demos/ARMCM3-STM32F103-GCC/Makefile
+++ b/demos/ARMCM3-STM32F103-GCC/Makefile
@@ -71,8 +71,7 @@ SRC = ../../ports/ARMCM3/chcore.c \
       board.c main.c

 

 # List ASM source files here

-ASMSRC =

-#../../ports/ARMCM3/crt0.s

+ASMSRC = ../../ports/ARMCM3/crt0.s

 

 # List all user directories here

 UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3

@@ -109,7 +108,7 @@ OBJS	= $(ASMOBJS) $(COBJS)
 LIBS    = $(DLIBS) $(ULIBS)

 MCFLAGS = -mcpu=$(MCU) -mthumb

 

-ASFLAGS = $(MCFLAGS) -mthumb -Wa,-amhls=$(<:.s=.lst) $(ADEFS)

+ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS)

 CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS)

 LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)

 ODFLAGS	= -x --syms

diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld
new file mode 100644
index 000000000..2ddc2aab4
--- /dev/null
+++ b/demos/ARMCM3-STM32F103-GCC/ch.ld
@@ -0,0 +1,80 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/*

+ * ST32F103 memory setup.

+ */

+__main_stack_size__	= 0x0100;

+__process_stack_size__	= 0x0100;

+__stacks_total_size__	= __main_stack_size__ + __process_stack_size__;

+

+MEMORY

+{

+	flash : org = 0x08000000, len = 128k

+	ram : org = 0x20000000, len = 20k

+}

+

+__ram_start__		= ORIGIN(ram);

+__ram_size__		= LENGTH(ram);

+__ram_end__		= __ram_start__ + __ram_size__;

+

+SECTIONS

+{

+	. = 0;

+

+	.text :

+	{

+		_text = .;

+		*(.text);

+		*(.rodata);

+		*(.rodata*);

+		*(.glue_7t);

+		*(.glue_7);

+		. = ALIGN(4);

+		_etext = .;

+	} > flash

+

+	_textdata = _etext;

+

+	.data :

+	{

+		_data = .;

+		*(.data)

+		. = ALIGN(4);

+		*(.ramtext)

+		. = ALIGN(4);

+		_edata = .;

+	} > ram AT > flash

+

+	.bss :

+	{

+		_bss_start = .;

+		*(.bss)

+		. = ALIGN(4);

+		*(COMMON)

+		. = ALIGN(4);

+		_bss_end = .;

+	} > ram    

+}

+

+PROVIDE(end = .);

+_end 			= .;

+

+__heap_base__		= _end;

+__heap_end__		= __ram_end__ - __stacks_total_size__;

diff --git a/ports/ARM7-AT91SAM7X/crt0.s b/ports/ARM7-AT91SAM7X/crt0.s
index dbe9db079..2afc9ef21 100644
--- a/ports/ARM7-AT91SAM7X/crt0.s
+++ b/ports/ARM7-AT91SAM7X/crt0.s
@@ -21,8 +21,6 @@
  * Generic ARM startup file for ChibiOS/RT (Atmel variant).

  */

 

-.extern _main

-

 .set    MODE_USR, 0x10

 .set    MODE_FIQ, 0x11

 .set    MODE_IRQ, 0x12

diff --git a/ports/ARM7-LPC214x/crt0.s b/ports/ARM7-LPC214x/crt0.s
index 91aec34b6..3f288b256 100644
--- a/ports/ARM7-LPC214x/crt0.s
+++ b/ports/ARM7-LPC214x/crt0.s
@@ -21,8 +21,6 @@
  * Generic ARM startup file for ChibiOS/RT.

  */

 

-.extern _main

-

 .set    MODE_USR, 0x10

 .set    MODE_FIQ, 0x11

 .set    MODE_IRQ, 0x12

diff --git a/ports/ARMCM3/crt0.s b/ports/ARMCM3/crt0.s
index 91aec34b6..8be43d6a3 100644
--- a/ports/ARMCM3/crt0.s
+++ b/ports/ARMCM3/crt0.s
@@ -18,89 +18,31 @@
 */

 

 /*

- * Generic ARM startup file for ChibiOS/RT.

+ * Generic ARM-CortexM3 startup file for ChibiOS/RT.

  */

 

-.extern _main

-

-.set    MODE_USR, 0x10

-.set    MODE_FIQ, 0x11

-.set    MODE_IRQ, 0x12

-.set    MODE_SVC, 0x13

-.set    MODE_ABT, 0x17

-.set    MODE_UND, 0x1B

-.set    MODE_SYS, 0x1F

-

-.equ    I_BIT, 0x80

-.equ    F_BIT, 0x40

+.set    CONTROL_MODE_PRIVILEGED, 0

+.set    CONTROL_MODE_UNPRIVILEGED, 1

+.set    CONTROL_USE_MSP, 0

+.set    CONTROL_USE_PSP, 0

 

 .text

-.code 32

-.balign 4

-/*

- * System entry points.

- */

-_start:

-        b       ResetHandler

-        ldr     pc, _undefined

-        ldr     pc, _swi

-        ldr     pc, _prefetch

-        ldr     pc, _abort

-        nop

-        ldr     pc, [pc,#-0xFF0]        /* VIC - IRQ Vector Register */

-        ldr     pc, _fiq

-

-_undefined:

-        .word   UndHandler

-_swi:

-        .word   SwiHandler

-_prefetch:

-        .word   PrefetchHandler

-_abort:

-        .word   AbortHandler

-_fiq:

-        .word   FiqHandler

-        .word   0

-        .word   0

-        .word   0

+.balign 2

+.syntax unified

 

 /*

  * Reset handler.

  */

+.global ResetHandler

 ResetHandler:

         /*

          * Stack pointers initialization.

          */

         ldr     r0, =__ram_end__

-        /* Undefined */

-        msr     CPSR_c, #MODE_UND | I_BIT | F_BIT

-        mov     sp, r0

-        ldr     r1, =__und_stack_size__

-        sub     r0, r0, r1

-        /* Abort */

-        msr     CPSR_c, #MODE_ABT | I_BIT | F_BIT

-        mov     sp, r0

-        ldr     r1, =__abt_stack_size__

+        ldr     r1, =__main_stack_size__

         sub     r0, r0, r1

-        /* FIQ */

-        msr     CPSR_c, #MODE_FIQ | I_BIT | F_BIT

-        mov     sp, r0

-        ldr     r1, =__fiq_stack_size__

-        sub     r0, r0, r1

-        /* IRQ */

-        msr     CPSR_c, #MODE_IRQ | I_BIT | F_BIT

-        mov     sp, r0

-        ldr     r1, =__irq_stack_size__

-        sub     r0, r0, r1

-        /* Supervisor */

-        msr     CPSR_c, #MODE_SVC | I_BIT | F_BIT

-        mov     sp, r0

-        ldr     r1, =__svc_stack_size__

-        sub     r0, r0, r1

-        /* System */

-        msr     CPSR_c, #MODE_SYS | I_BIT | F_BIT

-        mov     sp, r0

-//        ldr     r1, =__sys_stack_size__

+        msr     PSP, r0

+//        ldr     r1, =__process_stack_size__

 //        sub     r0, r0, r1

         /*

          * Data initialization.

@@ -109,11 +51,12 @@ ResetHandler:
         ldr     r1, =_textdata

         ldr     r2, =_data

         ldr     r3, =_edata

-dataloop:

+dloop:

         cmp     r2, r3

+        ittt    lo

         ldrlo   r0, [r1], #4

         strlo   r0, [r2], #4

-        blo     dataloop

+        blo     dloop

         /*

          * BSS initialization.

          * NOTE: It assumes that the BSS size is a multiple of 4.

@@ -121,14 +64,20 @@ dataloop:
         mov     r0, #0

         ldr     r1, =_bss_start

         ldr     r2, =_bss_end

-bssloop:

+bloop:

         cmp     r1, r2

+        itt     lo

         strlo   r0, [r1], #4

-        blo     bssloop

+        blo     bloop

+        /*

+         * Switches to the Process Stack and disables the interrupts globally.

+         */

+        mov     r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP

+        msr     CONTROL, r0

+        cpsid   i

         /*

          * Application-provided HW initialization routine.

          */

-#ifndef THUMB_NO_INTERWORKING

         bl      hwinit

         /*

          * main(0, NULL).

@@ -137,36 +86,3 @@ bssloop:
         mov     r1, r0

         bl      main

         bl      chSysHalt

-#else

-        add     r0, pc, #1

-        bx      r0

-.code 16

-        bl      hwinit

-        mov     r0, #0

-        mov     r1, r0

-        bl      main

-        bl      chSysHalt

-.code 32

-#endif

-

-.weak UndHandler

-.globl UndHandler

-UndHandler:

-

-.weak SwiHandler

-.globl SwiHandler

-SwiHandler:

-

-.weak PrefetchHandler

-.globl PrefetchHandler

-PrefetchHandler:

-

-.weak AbortHandler

-.globl AbortHandler

-AbortHandler:

-

-.weak FiqHandler

-.globl FiqHandler

-FiqHandler:

-

-.loop: b        .loop