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authoredolomb <none@example.com>2018-02-20 10:04:59 +0000
committeredolomb <none@example.com>2018-02-20 10:04:59 +0000
commit6497cd272ac8f7b6e4dfd67c44ac8790e4092526 (patch)
treed3afd50ca666beea24bc10cc55049389f2b58466
parent69076b40bdf6567ae03951cc8f73de9cb55b383e (diff)
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Changed SPI's frequency
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11518 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--testhal/ATSAMA5D2/FLEX-SPI/main.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/testhal/ATSAMA5D2/FLEX-SPI/main.c b/testhal/ATSAMA5D2/FLEX-SPI/main.c
index 7a2fbc2bf..077d6c1f9 100644
--- a/testhal/ATSAMA5D2/FLEX-SPI/main.c
+++ b/testhal/ATSAMA5D2/FLEX-SPI/main.c
@@ -23,17 +23,17 @@ static uint8_t txbuf[BUFFER_SIZE];
static uint8_t rxbuf[BUFFER_SIZE];
/*
- * SPI high speed configuration (83MHz (MCK/3/2), CPHA=0, CPOL=0, MSb first).
+ * SPI high speed configuration (peripheral clock / 3 = 27,6 Mhz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig hs_spicfg = {
NULL, /* callback if present */
0, /* cs pad number */
SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */
- SPI_CSR_SCBR(1) /* csr */
+ SPI_CSR_SCBR(3) /* csr */
};
/*
- * SPI low speed configuration (83MHz / 166 = 500KHz, CPHA=0, CPOL=0, MSb first).
+ * SPI low speed configuration (peripheral clock / 166 = 500KHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
NULL, /* callback if present */
@@ -55,11 +55,9 @@ static THD_FUNCTION(spi_thread_1, p) {
spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */
palClearLine(LINE_LED_RED); /* LED ON. */
spiStart(&FSPID2, &hs_spicfg); /* Setup transfer parameters. */
- spiSelect(&FSPID2);
spiExchange(&FSPID2, BUFFER_SIZE,
txbuf, rxbuf); /* Atomic transfer operations. */
cacheInvalidateRegion(&rxbuf, sizeof(rxbuf));
- spiUnselect(&FSPID2);
spiReleaseBus(&FSPID2); /* Ownership release. */
}
}
@@ -77,11 +75,9 @@ static THD_FUNCTION(spi_thread_2, p) {
spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */
palSetLine(LINE_LED_RED); /* LED OFF. */
spiStart(&FSPID2, &ls_spicfg); /* Setup transfer parameters. */
- spiSelect(&FSPID2);
spiExchange(&FSPID2, 512,
txbuf, rxbuf); /* Atomic transfer operations. */
cacheInvalidateRegion(&rxbuf, sizeof(rxbuf));
- spiUnselect(&FSPID2);
spiReleaseBus(&FSPID2); /* Ownership release. */
}
}