git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8278 35acf78f-673a-0410-8e92-d51de3d6d3f4

9 files changed, 95 insertions, 22 deletions

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
index 94668b13e..b7c90bd0e 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
@@ -18,8 +18,13 @@
 */

 

 /*

- * ST32F746xG memory setup.

- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.

+ * ST32F746xG generic setup.

+ * 

+ * RAM0 - Data, Heap.

+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.

+ *

+ * Notes:

+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.

  */

 MEMORY

 {

@@ -47,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
 REGION_ALIAS("DATA_RAM", ram0);

 

 /* RAM region to be used for BSS segment.*/

-REGION_ALIAS("BSS_RAM", ram0);

+REGION_ALIAS("BSS_RAM", ram3);

 

 /* RAM region to be used for the default heap.*/

 REGION_ALIAS("HEAP_RAM", ram0);

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
index 03d2e1478..d4fa6ca8a 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
@@ -18,8 +18,14 @@
 */

 

 /*

- * ST32F746xG memory setup.

- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.

+ * ST32F746xG Ethernet setup.

+ * 

+ * RAM1 - Data, Heap.

+ * RAM2 - ETH.

+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.

+ *

+ * Notes:

+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.

  */

 MEMORY

 {

@@ -46,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
 REGION_ALIAS("DATA_RAM", ram1);

 

 /* RAM region to be used for BSS segment.*/

-REGION_ALIAS("BSS_RAM", ram1);

+REGION_ALIAS("BSS_RAM", ram3);

 

 /* RAM region to be used for the default heap.*/

 REGION_ALIAS("HEAP_RAM", ram1);

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
new file mode 100644
index 000000000..21ba81fed
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
@@ -0,0 +1,68 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.

+

+    This file is part of ChibiOS.

+

+    ChibiOS is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/*

+ * ST32F746xG maximum RAM setup.

+ * 

+ * RAM0 - Data, BSS, Heap.

+ * RAM3 - Main Stack, Process Stack, NOCACHE, ETH.

+ *

+ * Notes:

+ * BSS is placed in cached RAM, DMA buffers management is delegated to the

+ * application code. This setup maximizes the linear RAM available to BSS and

+ * Heap.

+ */

+MEMORY

+{

+    flash       : org = 0x08000000, len = 1M

+    flash_itcm  : org = 0x00200000, len = 1M

+    ram0        : org = 0x20010000, len = 256k    /* SRAM1 + SRAM2 */

+    ram1        : org = 0x20010000, len = 240k    /* SRAM1 */

+    ram2        : org = 0x2004C000, len = 16k     /* SRAM2 */

+    ram3        : org = 0x20000000, len = 64k     /* DTCM-RAM */

+    ram4        : org = 0x00000000, len = 16k     /* ITCM-RAM */

+    ram5        : org = 0x40024000, len = 4k      /* BCKP SRAM */

+    ram6        : org = 0x00000000, len = 0

+    ram7        : org = 0x00000000, len = 0

+}

+

+/* RAM region to be used for Main stack. This stack accommodates the processing

+   of all exceptions and interrupts*/

+REGION_ALIAS("MAIN_STACK_RAM", ram3);

+

+/* RAM region to be used for the process stack. This is the stack used by

+   the main() function.*/

+REGION_ALIAS("PROCESS_STACK_RAM", ram3);

+

+/* RAM region to be used for data segment.*/

+REGION_ALIAS("DATA_RAM", ram0);

+

+/* RAM region to be used for BSS segment.*/

+REGION_ALIAS("BSS_RAM", ram0);

+

+/* RAM region to be used for the default heap.*/

+REGION_ALIAS("HEAP_RAM", ram0);

+

+/* RAM region to be used for nocache segment.*/

+REGION_ALIAS("NOCACHE_RAM", ram3);

+

+/* RAM region to be used for eth segment.*/

+REGION_ALIAS("ETH_RAM", ram3);

+

+INCLUDE ld/rules_STM32F7xx.ld

diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/main.c b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
index d0e810201..150a7d260 100644
--- a/testhal/STM32/STM32F7xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
@@ -52,10 +52,15 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
 size_t nx = 0, ny = 0;

 static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {

 

+#if 0

   /* DMA buffer invalidation because data cache, only invalidating the

-     half buffer just filled.*/

+     half buffer just filled.

+     Only required if the ADC buffer is placed in a cache-able area.*/

   dmaBufferInvalidate(buffer,

                       n * adcp->grpp->num_channels * sizeof (adcsample_t));

+#else

+  (void)adcp;

+#endif

 

   /* Updating counters.*/

   if (samples1 == buffer) {

diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
index d691c84b6..dad6a515f 100644
--- a/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
+++ b/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
@@ -88,6 +88,7 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE

 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL

 #define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL48CLK

+#define STM32_SRAM2_NOCACHE                 FALSE

 

 /*

  * ADC driver system settings.

diff --git a/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
index 351e3eb80..5678eaca6 100644
--- a/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
+++ b/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
@@ -88,6 +88,7 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE

 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL

 #define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL48CLK

+#define STM32_SRAM2_NOCACHE                 FALSE

 

 /*

  * ADC driver system settings.

diff --git a/testhal/STM32/STM32F7xx/SPI/main.c b/testhal/STM32/STM32F7xx/SPI/main.c
index 7632ca393..547e49501 100644
--- a/testhal/STM32/STM32F7xx/SPI/main.c
+++ b/testhal/STM32/STM32F7xx/SPI/main.c
@@ -55,14 +55,7 @@ static const SPIConfig ls_spicfg = {
  */

 #define SPI_BUFFERS_SIZE    128U

 

-#if defined(__GNUC__)

-__attribute__((aligned (32)))

-#endif

 static uint8_t txbuf[SPI_BUFFERS_SIZE];

-

-#if defined(__GNUC__)

-__attribute__((aligned (32)))

-#endif

 static uint8_t rxbuf[SPI_BUFFERS_SIZE];

 

 /*===========================================================================*/

@@ -87,7 +80,6 @@ static THD_FUNCTION(spi_thread_1, p) {
     /* Preparing data buffer and flushing cache.*/

     for (i = 0; i < SPI_BUFFERS_SIZE; i++)

       txbuf[i] = (uint8_t)i;

-    dmaBufferFlush(txbuf, SPI_BUFFERS_SIZE);

 

     /* Slave selection and data exchange.*/

     spiSelect(&SPID2);

@@ -95,9 +87,6 @@ static THD_FUNCTION(spi_thread_1, p) {
     spiUnselect(&SPID2);

 

 #if defined(SPI_LOOPBACK)

-    /* Invalidating cache over the buffer then checking the

-       loopback result.*/

-    dmaBufferInvalidate(rxbuf, SPI_BUFFERS_SIZE);

     if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)

       chSysHalt("loopback failure");

 #endif

@@ -125,7 +114,6 @@ static THD_FUNCTION(spi_thread_2, p) {
     /* Preparing data buffer and flushing cache.*/

     for (i = 0; i < SPI_BUFFERS_SIZE; i++)

       txbuf[i] = (uint8_t)(128U + i);

-    dmaBufferFlush(txbuf, SPI_BUFFERS_SIZE);

 

     /* Slave selection and data exchange.*/

     spiSelect(&SPID2);

@@ -133,9 +121,6 @@ static THD_FUNCTION(spi_thread_2, p) {
     spiUnselect(&SPID2);

 

 #if defined(SPI_LOOPBACK)

-    /* Invalidating cache over the buffer then checking the

-       loopback result.*/

-    dmaBufferInvalidate(rxbuf, SPI_BUFFERS_SIZE);

     if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)

       chSysHalt("loopback failure");

 #endif

diff --git a/testhal/STM32/STM32F7xx/SPI/mcuconf.h b/testhal/STM32/STM32F7xx/SPI/mcuconf.h
index d1452e162..9a7ac538a 100644
--- a/testhal/STM32/STM32F7xx/SPI/mcuconf.h
+++ b/testhal/STM32/STM32F7xx/SPI/mcuconf.h
@@ -88,6 +88,7 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE

 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL

 #define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL48CLK

+#define STM32_SRAM2_NOCACHE                 FALSE

 

 /*

  * ADC driver system settings.

diff --git a/testhal/STM32/STM32F7xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F7xx/USB_CDC/mcuconf.h
index 8931b4ffe..5eae8dff9 100644
--- a/testhal/STM32/STM32F7xx/USB_CDC/mcuconf.h
+++ b/testhal/STM32/STM32F7xx/USB_CDC/mcuconf.h
@@ -88,6 +88,7 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE

 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL

 #define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL48CLK

+#define STM32_SRAM2_NOCACHE                 FALSE

 

 /*

  * ADC driver system settings.