Added demo STM32/RT-STM32L031K6-NUCLEO32

Added board files for STM32 Nucleo32 L031K6

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9413 35acf78f-673a-0410-8e92-d51de3d6d3f4

13 files changed, 3674 insertions, 0 deletions

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/.cproject b/demos/STM32/RT-STM32L031K6-NUCLEO32/.cproject
new file mode 100644
index 000000000..ea504de04
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/.cproject
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>

+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">

+	<storageModule moduleId="org.eclipse.cdt.core.settings">

+		<cconfiguration id="0.603687198">

+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.603687198" moduleId="org.eclipse.cdt.core.settings" name="Default">

+				<externalSettings/>

+				<extensions>

+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>

+				</extensions>

+			</storageModule>

+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">

+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.603687198" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">

+					<folderInfo id="0.603687198." name="/" resourcePath="">

+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.586709963" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">

+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.586709963.1446538340" name=""/>

+							<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1490952991" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1134067298" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.1927705259" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1013764026" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.1367371861" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1824820452" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+							<tool id="org.eclipse.cdt.build.core.settings.holder.1584496456" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">

+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1781547795" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>

+							</tool>

+						</toolChain>

+					</folderInfo>

+				</configuration>

+			</storageModule>

+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>

+		</cconfiguration>

+	</storageModule>

+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">

+		<project id="RT-STM32L053R8-NUCLEO.null.1004513353" name="RT-STM32L053R8-NUCLEO"/>

+	</storageModule>

+	<storageModule moduleId="scannerConfiguration">

+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>

+		<scannerConfigBuildInfo instanceId="0.603687198">

+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>

+		</scannerConfigBuildInfo>

+	</storageModule>

+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>

+	<storageModule moduleId="refreshScope" versionNumber="2">

+		<configuration configurationName="Default">

+			<resource resourceType="PROJECT" workspacePath="/RT-STM32L053R8-NUCLEO"/>

+		</configuration>

+	</storageModule>

+</cproject>

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/.project b/demos/STM32/RT-STM32L031K6-NUCLEO32/.project
new file mode 100644
index 000000000..cde752ade
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/.project
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<projectDescription>

+	<name>RT-STM32L031K6-NUCLEO32</name>

+	<comment></comment>

+	<projects>

+	</projects>

+	<buildSpec>

+		<buildCommand>

+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>

+			<triggers>clean,full,incremental,</triggers>

+			<arguments>

+			</arguments>

+		</buildCommand>

+		<buildCommand>

+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>

+			<triggers>full,incremental,</triggers>

+			<arguments>

+			</arguments>

+		</buildCommand>

+	</buildSpec>

+	<natures>

+		<nature>org.eclipse.cdt.core.cnature</nature>

+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>

+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>

+	</natures>

+	<linkedResources>

+		<link>

+			<name>board</name>

+			<type>2</type>

+			<location>C:/ChibiStudio/chibios_trunk/os/hal/boards/ST_NUCLEO32_L031K6</location>

+		</link>

+		<link>

+			<name>os</name>

+			<type>2</type>

+			<locationURI>CHIBIOS/os</locationURI>

+		</link>

+		<link>

+			<name>test</name>

+			<type>2</type>

+			<locationURI>CHIBIOS/test</locationURI>

+		</link>

+	</linkedResources>

+</projectDescription>

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/Makefile b/demos/STM32/RT-STM32L031K6-NUCLEO32/Makefile
new file mode 100644
index 000000000..6f39bd6da
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/Makefile
@@ -0,0 +1,218 @@
+##############################################################################

+# Build global options

+# NOTE: Can be overridden externally.

+#

+

+# Compiler options here.

+ifeq ($(USE_OPT),)

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16

+endif

+

+# C specific options here (added to USE_OPT).

+ifeq ($(USE_COPT),)

+  USE_COPT = 

+endif

+

+# C++ specific options here (added to USE_OPT).

+ifeq ($(USE_CPPOPT),)

+  USE_CPPOPT = -fno-rtti

+endif

+

+# Enable this if you want the linker to remove unused code and data

+ifeq ($(USE_LINK_GC),)

+  USE_LINK_GC = yes

+endif

+

+# Linker extra options here.

+ifeq ($(USE_LDOPT),)

+  USE_LDOPT = 

+endif

+

+# Enable this if you want link time optimizations (LTO)

+ifeq ($(USE_LTO),)

+  USE_LTO = yes

+endif

+

+# If enabled, this option allows to compile the application in THUMB mode.

+ifeq ($(USE_THUMB),)

+  USE_THUMB = yes

+endif

+

+# Enable this if you want to see the full log while compiling.

+ifeq ($(USE_VERBOSE_COMPILE),)

+  USE_VERBOSE_COMPILE = no

+endif

+

+# If enabled, this option makes the build process faster by not compiling

+# modules not used in the current configuration.

+ifeq ($(USE_SMART_BUILD),)

+  USE_SMART_BUILD = yes

+endif

+

+#

+# Build global options

+##############################################################################

+

+##############################################################################

+# Architecture or project specific options

+#

+

+# Stack size to be allocated to the Cortex-M process stack. This stack is

+# the stack used by the main() thread.

+ifeq ($(USE_PROCESS_STACKSIZE),)

+  USE_PROCESS_STACKSIZE = 0x200

+endif

+

+# Stack size to the allocated to the Cortex-M main/exceptions stack. This

+# stack is used for processing interrupts and exceptions.

+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)

+  USE_EXCEPTIONS_STACKSIZE = 0x400

+endif

+

+# Enables the use of FPU (no, softfp, hard).

+ifeq ($(USE_FPU),)

+  USE_FPU = no

+endif

+

+#

+# Architecture or project specific options

+##############################################################################

+

+##############################################################################

+# Project, sources and paths

+#

+

+# Define project name here

+PROJECT = ch

+

+# Imported source files and paths

+CHIBIOS = ../../..

+# Startup files.

+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk

+# HAL-OSAL files (optional).

+include $(CHIBIOS)/os/hal/hal.mk

+include $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/platform.mk

+include $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L031K6/board.mk

+include $(CHIBIOS)/os/hal/osal/rt/osal.mk

+# RTOS files (optional).

+include $(CHIBIOS)/os/rt/rt.mk

+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk

+# Other files (optional).

+include $(CHIBIOS)/test/rt/test.mk

+

+# Define linker script file here

+LDSCRIPT= $(STARTUPLD)/STM32L031x6.ld

+

+# C sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CSRC = $(STARTUPSRC) \

+       $(KERNSRC) \

+       $(PORTSRC) \

+       $(OSALSRC) \

+       $(HALSRC) \

+       $(PLATFORMSRC) \

+       $(BOARDSRC) \

+       $(TESTSRC) \

+       main.c

+

+# C++ sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CPPSRC =

+

+# C sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACSRC =

+

+# C++ sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACPPSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCPPSRC =

+

+# List ASM source files here

+ASMSRC =

+ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)

+

+INCDIR = $(CHIBIOS)/os/license \

+         $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \

+         $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \

+         $(CHIBIOS)/os/various

+

+#

+# Project, sources and paths

+##############################################################################

+

+##############################################################################

+# Compiler settings

+#

+

+MCU  = cortex-m0

+

+#TRGT = arm-elf-

+TRGT = arm-none-eabi-

+CC   = $(TRGT)gcc

+CPPC = $(TRGT)g++

+# Enable loading with g++ only if you need C++ runtime support.

+# NOTE: You can use C++ even without C++ support if you are careful. C++

+#       runtime support makes code size explode.

+LD   = $(TRGT)gcc

+#LD   = $(TRGT)g++

+CP   = $(TRGT)objcopy

+AS   = $(TRGT)gcc -x assembler-with-cpp

+AR   = $(TRGT)ar

+OD   = $(TRGT)objdump

+SZ   = $(TRGT)size

+HEX  = $(CP) -O ihex

+BIN  = $(CP) -O binary

+

+# ARM-specific options here

+AOPT =

+

+# THUMB-specific options here

+TOPT = -mthumb -DTHUMB

+

+# Define C warning options here

+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes

+

+# Define C++ warning options here

+CPPWARN = -Wall -Wextra -Wundef

+

+#

+# Compiler settings

+##############################################################################

+

+##############################################################################

+# Start of user section

+#

+

+# List all user C define here, like -D_DEBUG=1

+UDEFS =

+

+# Define ASM defines here

+UADEFS =

+

+# List all user directories here

+UINCDIR =

+

+# List the user directory to look for the libraries here

+ULIBDIR =

+

+# List all user libraries here

+ULIBS =

+

+#

+# End of user defines

+##############################################################################

+

+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC

+include $(RULESPATH)/rules.mk

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/chconf.h b/demos/STM32/RT-STM32L031K6-NUCLEO32/chconf.h
new file mode 100644
index 000000000..4d33c071b
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/chconf.h
@@ -0,0 +1,520 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/chconf.h

+ * @brief   Configuration file template.

+ * @details A copy of this file must be placed in each project directory, it

+ *          contains the application specific kernel settings.

+ *

+ * @addtogroup config

+ * @details Kernel related settings and hooks.

+ * @{

+ */

+

+#ifndef CHCONF_H

+#define CHCONF_H

+

+#define _CHIBIOS_RT_CONF_

+

+/*===========================================================================*/

+/**

+ * @name System timers settings

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   System time counter resolution.

+ * @note    Allowed values are 16 or 32 bits.

+ */

+#define CH_CFG_ST_RESOLUTION                16

+

+/**

+ * @brief   System tick frequency.

+ * @details Frequency of the system timer that drives the system ticks. This

+ *          setting also defines the system tick time unit.

+ */

+#define CH_CFG_ST_FREQUENCY                 1000

+

+/**

+ * @brief   Time delta constant for the tick-less mode.

+ * @note    If this value is zero then the system uses the classic

+ *          periodic tick. This value represents the minimum number

+ *          of ticks that is safe to specify in a timeout directive.

+ *          The value one is not valid, timeouts are rounded up to

+ *          this value.

+ */

+#define CH_CFG_ST_TIMEDELTA                 2

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel parameters and options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Round robin interval.

+ * @details This constant is the number of system ticks allowed for the

+ *          threads before preemption occurs. Setting this value to zero

+ *          disables the preemption for threads with equal priority and the

+ *          round robin becomes cooperative. Note that higher priority

+ *          threads can still preempt, the kernel is always preemptive.

+ * @note    Disabling the round robin preemption makes the kernel more compact

+ *          and generally faster.

+ * @note    The round robin preemption is not supported in tickless mode and

+ *          must be set to zero in that case.

+ */

+#define CH_CFG_TIME_QUANTUM                 0

+

+/**

+ * @brief   Managed RAM size.

+ * @details Size of the RAM area to be managed by the OS. If set to zero

+ *          then the whole available RAM is used. The core memory is made

+ *          available to the heap allocator and/or can be used directly through

+ *          the simplified core memory allocator.

+ *

+ * @note    In order to let the OS manage the whole RAM the linker script must

+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.

+ * @note    Requires @p CH_CFG_USE_MEMCORE.

+ */

+#define CH_CFG_MEMCORE_SIZE                 0

+

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread. The application @p main()

+ *          function becomes the idle thread and must implement an

+ *          infinite loop.

+ */

+#define CH_CFG_NO_IDLE_THREAD               FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Performance options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   OS optimization.

+ * @details If enabled then time efficient rather than space efficient code

+ *          is used when two possible implementations exist.

+ *

+ * @note    This is not related to the compiler optimization options.

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_OPTIMIZE_SPEED               TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Subsystem options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Time Measurement APIs.

+ * @details If enabled then the time measurement APIs are included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_TM                       FALSE

+

+/**

+ * @brief   Threads registry APIs.

+ * @details If enabled then the registry APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_REGISTRY                 TRUE

+

+/**

+ * @brief   Threads synchronization APIs.

+ * @details If enabled then the @p chThdWait() function is included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_WAITEXIT                 TRUE

+

+/**

+ * @brief   Semaphores APIs.

+ * @details If enabled then the Semaphores APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_SEMAPHORES               TRUE

+

+/**

+ * @brief   Semaphores queuing mode.

+ * @details If enabled then the threads are enqueued on semaphores by

+ *          priority rather than in FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE

+

+/**

+ * @brief   Mutexes APIs.

+ * @details If enabled then the mutexes APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MUTEXES                  TRUE

+

+/**

+ * @brief   Enables recursive behavior on mutexes.

+ * @note    Recursive mutexes are heavier and have an increased

+ *          memory footprint.

+ *

+ * @note    The default is @p FALSE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE

+

+/**

+ * @brief   Conditional Variables APIs.

+ * @details If enabled then the conditional variables APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_CONDVARS                 TRUE

+

+/**

+ * @brief   Conditional Variables APIs with timeout.

+ * @details If enabled then the conditional variables APIs with timeout

+ *          specification are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_CONDVARS.

+ */

+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE

+

+/**

+ * @brief   Events Flags APIs.

+ * @details If enabled then the event flags APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_EVENTS                   TRUE

+

+/**

+ * @brief   Events Flags APIs with timeout.

+ * @details If enabled then the events APIs with timeout specification

+ *          are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_EVENTS.

+ */

+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE

+

+/**

+ * @brief   Synchronous Messages APIs.

+ * @details If enabled then the synchronous messages APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MESSAGES                 TRUE

+

+/**

+ * @brief   Synchronous Messages queuing mode.

+ * @details If enabled then messages are served by priority rather than in

+ *          FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_MESSAGES.

+ */

+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE

+

+/**

+ * @brief   Mailboxes APIs.

+ * @details If enabled then the asynchronous messages (mailboxes) APIs are

+ *          included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_MAILBOXES                TRUE

+

+/**

+ * @brief   Core Memory Manager APIs.

+ * @details If enabled then the core memory manager APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMCORE                  TRUE

+

+/**

+ * @brief   Heap Allocator APIs.

+ * @details If enabled then the memory heap allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or

+ *          @p CH_CFG_USE_SEMAPHORES.

+ * @note    Mutexes are recommended.

+ */

+#define CH_CFG_USE_HEAP                     TRUE

+

+/**

+ * @brief   Memory Pools Allocator APIs.

+ * @details If enabled then the memory pools allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMPOOLS                 TRUE

+

+/**

+ * @brief   Dynamic Threads APIs.

+ * @details If enabled then the dynamic threads creation APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_WAITEXIT.

+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.

+ */

+#define CH_CFG_USE_DYNAMIC                  TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Debug options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Debug option, kernel statistics.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_STATISTICS                   FALSE

+

+/**

+ * @brief   Debug option, system state check.

+ * @details If enabled the correct call protocol for system APIs is checked

+ *          at runtime.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_SYSTEM_STATE_CHECK           FALSE

+

+/**

+ * @brief   Debug option, parameters checks.

+ * @details If enabled then the checks on the API functions input

+ *          parameters are activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_CHECKS                FALSE

+

+/**

+ * @brief   Debug option, consistency checks.

+ * @details If enabled then all the assertions in the kernel code are

+ *          activated. This includes consistency checks inside the kernel,

+ *          runtime anomalies and port-defined checks.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_ASSERTS               FALSE

+

+/**

+ * @brief   Debug option, trace buffer.

+ * @details If enabled then the trace buffer is activated.

+ *

+ * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED.

+ */

+#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_DISABLED

+

+/**

+ * @brief   Trace buffer entries.

+ * @note    The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is

+ *          different from @p CH_DBG_TRACE_MASK_DISABLED.

+ */

+#define CH_DBG_TRACE_BUFFER_SIZE            128

+

+/**

+ * @brief   Debug option, stack checks.

+ * @details If enabled then a runtime stack check is performed.

+ *

+ * @note    The default is @p FALSE.

+ * @note    The stack check is performed in a architecture/port dependent way.

+ *          It may not be implemented or some ports.

+ * @note    The default failure mode is to halt the system with the global

+ *          @p panic_msg variable set to @p NULL.

+ */

+#define CH_DBG_ENABLE_STACK_CHECK           FALSE

+

+/**

+ * @brief   Debug option, stacks initialization.

+ * @details If enabled then the threads working area is filled with a byte

+ *          value when a thread is created. This can be useful for the

+ *          runtime measurement of the used stack.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_FILL_THREADS                 FALSE

+

+/**

+ * @brief   Debug option, threads profiling.

+ * @details If enabled then a field is added to the @p thread_t structure that

+ *          counts the system ticks occurred while executing the thread.

+ *

+ * @note    The default is @p FALSE.

+ * @note    This debug option is not currently compatible with the

+ *          tickless mode.

+ */

+#define CH_DBG_THREADS_PROFILING            FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel hooks

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Threads descriptor structure extension.

+ * @details User fields added to the end of the @p thread_t structure.

+ */

+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \

+  /* Add threads custom fields here.*/

+

+/**

+ * @brief   Threads initialization hook.

+ * @details User initialization code added to the @p chThdInit() API.

+ *

+ * @note    It is invoked from within @p chThdInit() and implicitly from all

+ *          the threads creation APIs.

+ */

+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \

+  /* Add threads initialization code here.*/                                \

+}

+

+/**

+ * @brief   Threads finalization hook.

+ * @details User finalization code added to the @p chThdExit() API.

+ */

+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \

+  /* Add threads finalization code here.*/                                  \

+}

+

+/**

+ * @brief   Context switch hook.

+ * @details This hook is invoked just before switching between threads.

+ */

+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \

+  /* Context switch code here.*/                                            \

+}

+

+/**

+ * @brief   ISR enter hook.

+ */

+#define CH_CFG_IRQ_PROLOGUE_HOOK() {                                        \

+  /* IRQ prologue code here.*/                                              \

+}

+

+/**

+ * @brief   ISR exit hook.

+ */

+#define CH_CFG_IRQ_EPILOGUE_HOOK() {                                        \

+  /* IRQ epilogue code here.*/                                              \

+}

+

+/**

+ * @brief   Idle thread enter hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to activate a power saving mode.

+ */

+#define CH_CFG_IDLE_ENTER_HOOK() {                                          \

+  /* Idle-enter code here.*/                                                \

+}

+

+/**

+ * @brief   Idle thread leave hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to deactivate a power saving mode.

+ */

+#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \

+  /* Idle-leave code here.*/                                                \

+}

+

+/**

+ * @brief   Idle Loop hook.

+ * @details This hook is continuously invoked by the idle thread loop.

+ */

+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \

+  /* Idle loop code here.*/                                                 \

+}

+

+/**

+ * @brief   System tick event hook.

+ * @details This hook is invoked in the system tick handler immediately

+ *          after processing the virtual timers queue.

+ */

+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \

+  /* System tick event code here.*/                                         \

+}

+

+/**

+ * @brief   System halt hook.

+ * @details This hook is invoked in case to a system halting error before

+ *          the system is halted.

+ */

+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \

+  /* System halt code here.*/                                               \

+}

+

+/**

+ * @brief   Trace hook.

+ * @details This hook is invoked each time a new record is written in the

+ *          trace buffer.

+ */

+#define CH_CFG_TRACE_HOOK(tep) {                                            \

+  /* Trace code here.*/                                                     \

+}

+

+/** @} */

+

+/*===========================================================================*/

+/* Port-specific settings (override port settings defaulted in chcore.h).    */

+/*===========================================================================*/

+

+#endif  /* CHCONF_H */

+

+/** @} */

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/debug/RT-STM32L031K6-NUCLEO32 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32L031K6-NUCLEO32/debug/RT-STM32L031K6-NUCLEO32 (OpenOCD, Flash and Run).launch
new file mode 100644
index 000000000..4bfc29a5f
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/debug/RT-STM32L031K6-NUCLEO32 (OpenOCD, Flash and Run).launch
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>

+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">

+<stringAttribute key="bad_container_name" value="\RT-STM32L031K6-NUCLEO32\debug"/>

+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20&#13;&#10;monitor reset init&#13;&#10;monitor sleep 50&#13;&#10;"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>

+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>

+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>

+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>

+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>

+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>

+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>

+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>

+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>

+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>

+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>

+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>

+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>

+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>

+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>

+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>

+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32L031K6-NUCLEO32"/>

+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>

+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.603687198"/>

+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">

+<listEntry value="/RT-STM32L031K6-NUCLEO32"/>

+</listAttribute>

+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">

+<listEntry value="4"/>

+</listAttribute>

+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">

+<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>

+</listAttribute>

+</launchConfiguration>

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/halconf.h b/demos/STM32/RT-STM32L031K6-NUCLEO32/halconf.h
new file mode 100644
index 000000000..1bdd0f844
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/halconf.h
@@ -0,0 +1,381 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/halconf.h

+ * @brief   HAL configuration header.

+ * @details HAL configuration file, this file allows to enable or disable the

+ *          various device drivers from your application. You may also use

+ *          this file in order to override the device drivers default settings.

+ *

+ * @addtogroup HAL_CONF

+ * @{

+ */

+

+#ifndef HALCONF_H

+#define HALCONF_H

+

+#include "mcuconf.h"

+

+/**

+ * @brief   Enables the PAL subsystem.

+ */

+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

+#define HAL_USE_PAL                 TRUE

+#endif

+

+/**

+ * @brief   Enables the ADC subsystem.

+ */

+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

+#define HAL_USE_ADC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the CAN subsystem.

+ */

+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)

+#define HAL_USE_CAN                 FALSE

+#endif

+

+/**

+ * @brief   Enables the DAC subsystem.

+ */

+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)

+#define HAL_USE_DAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EXT subsystem.

+ */

+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)

+#define HAL_USE_EXT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the I2C subsystem.

+ */

+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

+#define HAL_USE_I2C                 FALSE

+#endif

+

+/**

+ * @brief   Enables the I2S subsystem.

+ */

+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)

+#define HAL_USE_I2S                 FALSE

+#endif

+

+/**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MAC subsystem.

+ */

+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

+#define HAL_USE_MAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MMC_SPI subsystem.

+ */

+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_MMC_SPI             FALSE

+#endif

+

+/**

+ * @brief   Enables the PWM subsystem.

+ */

+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

+#define HAL_USE_PWM                 FALSE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)

+#define HAL_USE_RTC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL subsystem.

+ */

+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL              TRUE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB          FALSE

+#endif

+

+/**

+ * @brief   Enables the SPI subsystem.

+ */

+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_SPI                 FALSE

+#endif

+

+/**

+ * @brief   Enables the UART subsystem.

+ */

+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

+#define HAL_USE_UART                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                 FALSE

+#endif

+

+/**

+ * @brief   Enables the WDG subsystem.

+ */

+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)

+#define HAL_USE_WDG                 FALSE

+#endif

+

+/*===========================================================================*/

+/* ADC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

+#define ADC_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define ADC_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* CAN driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Sleep mode related APIs inclusion switch.

+ */

+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)

+#define CAN_USE_SLEEP_MODE          TRUE

+#endif

+

+/*===========================================================================*/

+/* I2C driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* MAC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)

+#define MAC_USE_ZERO_COPY           FALSE

+#endif

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)

+#define MAC_USE_EVENTS              TRUE

+#endif

+

+/*===========================================================================*/

+/* MMC_SPI driver related settings.                                          */

+/*===========================================================================*/

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ *          This option is recommended also if the SPI driver does not

+ *          use a DMA channel and heavily loads the CPU.

+ */

+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)

+#define MMC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intervals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY              100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT             FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SERIAL driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Default bit rate.

+ * @details Configuration parameter, this is the baud rate selected for the

+ *          default configuration.

+ */

+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

+#define SERIAL_DEFAULT_BITRATE      38400

+#endif

+

+/**

+ * @brief   Serial buffers size.

+ * @details Configuration parameter, you can change the depth of the queue

+ *          buffers depending on the requirements of your application.

+ * @note    The default is 16 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_BUFFERS_SIZE         16

+#endif

+

+/*===========================================================================*/

+/* SERIAL_USB driver related setting.                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   Serial over USB buffers size.

+ * @details Configuration parameter, the buffer size must be a multiple of

+ *          the USB data endpoint maximum packet size.

+ * @note    The default is 256 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_SIZE     256

+#endif

+

+/**

+ * @brief   Serial over USB number of buffers.

+ * @note    The default is 2 buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_NUMBER   2

+#endif

+

+/*===========================================================================*/

+/* SPI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)

+#define SPI_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define SPI_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* UART driver related settings.                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)

+#define UART_USE_WAIT               FALSE

+#endif

+

+/**

+ * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define UART_USE_MUTUAL_EXCLUSION   FALSE

+#endif

+

+/*===========================================================================*/

+/* USB driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)

+#define USB_USE_WAIT                FALSE

+#endif

+

+#endif /* HALCONF_H */

+

+/** @} */

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/main.c b/demos/STM32/RT-STM32L031K6-NUCLEO32/main.c
new file mode 100644
index 000000000..e8272659a
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/main.c
@@ -0,0 +1,72 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#include "ch.h"

+#include "hal.h"

+#include "ch_test.h"

+

+/*

+ * Green LED blinker thread, times are in milliseconds.

+ */

+static THD_WORKING_AREA(waThread1, 128);

+static THD_FUNCTION(Thread1, arg) {

+

+  (void)arg;

+  chRegSetThreadName("blinker");

+  palSetLineMode(LINE_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);

+  while (true) {

+    palClearLine(LINE_LED_GREEN);

+    chThdSleepMilliseconds(500);

+    palSetLine(LINE_LED_GREEN);

+    chThdSleepMilliseconds(500);

+  }

+}

+

+/*

+ * Application entry point.

+ */

+int main(void) {

+

+  /*

+   * System initializations.

+   * - HAL initialization, this also initializes the configured device drivers

+   *   and performs the board-specific initializations.

+   * - Kernel initialization, the main() function becomes a thread and the

+   *   RTOS is active.

+   */

+  halInit();

+  chSysInit();

+

+  /*

+   * Activates the serial driver 2 using the driver default configuration.

+   */

+  sdStart(&SD2, NULL);

+

+  /*

+   * Creates the blinker thread.

+   */

+  chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);

+

+  /*

+   * Normal main() thread activity, in this demo it does nothing except

+   * sleeping in a loop and check the button state.

+   */

+  while (true) {

+    if (!palReadLine(LINE_ARD_D3))

+      test_execute((BaseSequentialStream *)&SD2);

+    chThdSleepMilliseconds(500);

+  }

+}

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32L031K6-NUCLEO32/mcuconf.h
new file mode 100644
index 000000000..f7cedeb21
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/mcuconf.h
@@ -0,0 +1,181 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

+/*

+ * STM32L1xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+#define STM32L0xx_MCUCONF

+

+/*

+ * HAL driver system settings.

+ */

+#define STM32_NO_INIT                       FALSE

+#define STM32_VOS                           STM32_VOS_1P8

+#define STM32_PVD_ENABLE                    FALSE

+#define STM32_PLS                           STM32_PLS_LEV0

+#define STM32_HSI16_ENABLED                 TRUE

+#define STM32_LSI_ENABLED                   TRUE

+#define STM32_HSE_ENABLED                   FALSE

+#define STM32_LSE_ENABLED                   FALSE

+#define STM32_ADC_CLOCK_ENABLED             TRUE

+#define STM32_USB_CLOCK_ENABLED             TRUE

+#define STM32_MSIRANGE                      STM32_MSIRANGE_2M

+#define STM32_SW                            STM32_SW_PLL

+#define STM32_PLLSRC                        STM32_PLLSRC_HSI16

+#define STM32_PLLMUL_VALUE                  4

+#define STM32_PLLDIV_VALUE                  2

+#define STM32_HPRE                          STM32_HPRE_DIV1

+#define STM32_PPRE1                         STM32_PPRE1_DIV1

+#define STM32_PPRE2                         STM32_PPRE2_DIV1

+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK

+#define STM32_MCOPRE                        STM32_MCOPRE_DIV1

+#define STM32_RTCSEL                        STM32_RTCSEL_LSI

+#define STM32_RTCPRE                        STM32_RTCPRE_DIV2

+#define STM32_USART2SEL                     STM32_USART2SEL_APB

+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_APB

+#define STM32_I2C1SEL                       STM32_I2C1SEL_APB

+#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_APB

+#define STM32_HSI48SEL                      STM32_HSI48SEL_HSI48

+

+/*

+ * ADC driver system settings.

+ * Note, IRQ is shared with EXT channels 21 and 22.

+ */

+#define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_ADC1_CKMODE               STM32_ADC_CKMODE_ADCCLK

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_PRESCALER_VALUE           1

+

+/*

+ * EXT driver system settings.

+ */

+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY      3

+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY      3

+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY     3

+#define STM32_EXT_EXTI16_IRQ_PRIORITY       3

+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY    3

+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY    3

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_TIM2_IRQ_PRIORITY         2

+#define STM32_GPT_USE_TIM21                 FALSE

+#define STM32_GPT_TIM21_IRQ_PRIORITY        2

+#define STM32_GPT_USE_TIM22                 FALSE

+#define STM32_GPT_TIM22_IRQ_PRIORITY        2

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  FALSE

+#define STM32_I2C_USE_I2C2                  FALSE

+#define STM32_I2C_BUSY_TIMEOUT              50

+#define STM32_I2C_I2C1_IRQ_PRIORITY         3

+#define STM32_I2C_I2C2_IRQ_PRIORITY         3

+#define STM32_I2C_USE_DMA                   TRUE

+#define STM32_I2C_I2C1_DMA_PRIORITY         1

+#define STM32_I2C_I2C2_DMA_PRIORITY         1

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_TIM2_IRQ_PRIORITY         3

+#define STM32_ICU_USE_TIM21                 FALSE

+#define STM32_ICU_TIM21_IRQ_PRIORITY        3

+#define STM32_ICU_USE_TIM22                 FALSE

+#define STM32_ICU_TIM22_IRQ_PRIORITY        3

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              FALSE

+#define STM32_PWM_USE_TIM2                  FALSE

+#define STM32_PWM_TIM2_IRQ_PRIORITY         3

+#define STM32_PWM_USE_TIM21                 FALSE

+#define STM32_PWM_TIM21_IRQ_PRIORITY        3

+#define STM32_PWM_USE_TIM22                 FALSE

+#define STM32_PWM_TIM22_IRQ_PRIORITY        3

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART2             TRUE

+#define STM32_SERIAL_USE_LPUART1            FALSE

+#define STM32_SERIAL_USART1_PRIORITY        3

+#define STM32_SERIAL_USART2_PRIORITY        3

+#define STM32_SERIAL_LPUART1_PRIORITY       3

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  FALSE

+#define STM32_SPI_USE_SPI2                  FALSE

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI1_IRQ_PRIORITY         1

+#define STM32_SPI_SPI2_IRQ_PRIORITY         1

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

+

+/*

+ * ST driver system settings.

+ */

+#define STM32_ST_IRQ_PRIORITY               2

+#define STM32_ST_USE_TIMER                  21

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USART2_IRQ_PRIORITY      3

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

+

+/*

+ * WDG driver system settings.

+ */

+#define STM32_WDG_USE_IWDG                  FALSE

+

+#endif /* MCUCONF_H */

diff --git a/demos/STM32/RT-STM32L031K6-NUCLEO32/readme.txt b/demos/STM32/RT-STM32L031K6-NUCLEO32/readme.txt
new file mode 100644
index 000000000..5ceba8db7
--- /dev/null
+++ b/demos/STM32/RT-STM32L031K6-NUCLEO32/readme.txt
@@ -0,0 +1,28 @@
+*****************************************************************************

+** ChibiOS/RT port for ARM-Cortex-M0 STM32L053.                            **

+*****************************************************************************

+

+** TARGET **

+

+The demo runs on an STM32 Nucleo64-L053R8 board. board.

+

+** The Demo **

+

+The demo flashes the board LED using a thread, by pressing the button located

+on the board the test procedure is activated with output on the serial port

+SD2 (USART2, mapped on USB virtual COM port).

+

+** Build Procedure **

+

+The demo has been tested by using the free Codesourcery GCC-based toolchain

+and YAGARTO.

+Just modify the TRGT line in the makefile in order to use different GCC ports.

+

+** Notes **

+

+Some files used by the demo are not part of ChibiOS/RT but are copyright of

+ST Microelectronics and are licensed under a different license.

+Also note that not all the files present in the ST library are distributed

+with ChibiOS/RT, you can find the whole library on the ST web site:

+

+                             http://www.st.com

diff --git a/os/hal/boards/ST_NUCLEO32_L031K6/board.c b/os/hal/boards/ST_NUCLEO32_L031K6/board.c
new file mode 100644
index 000000000..f56bd1a03
--- /dev/null
+++ b/os/hal/boards/ST_NUCLEO32_L031K6/board.c
@@ -0,0 +1,124 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#include "hal.h"

+

+#if HAL_USE_PAL || defined(__DOXYGEN__)

+/**

+ * @brief   PAL setup.

+ * @details Digital I/O ports static configuration as defined in @p board.h.

+ *          This variable is used by the HAL when initializing the PAL driver.

+ */

+const PALConfig pal_default_config = {

+#if STM32_HAS_GPIOA

+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,

+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},

+#endif

+#if STM32_HAS_GPIOB

+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,

+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},

+#endif

+#if STM32_HAS_GPIOC

+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,

+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},

+#endif

+#if STM32_HAS_GPIOD

+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,

+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},

+#endif

+#if STM32_HAS_GPIOE

+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,

+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},

+#endif

+#if STM32_HAS_GPIOF

+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,

+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},

+#endif

+#if STM32_HAS_GPIOG

+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,

+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},

+#endif

+#if STM32_HAS_GPIOH

+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,

+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},

+#endif

+#if STM32_HAS_GPIOI

+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,

+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}

+#endif

+};

+#endif

+

+/**

+ * @brief   Early initialization code.

+ * @details This initialization must be performed just after stack setup

+ *          and before any other initialization.

+ */

+void __early_init(void) {

+

+  stm32_clock_init();

+}

+

+#if HAL_USE_SDC || defined(__DOXYGEN__)

+/**

+ * @brief   SDC card detection.

+ */

+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* TODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   SDC card write protection detection.

+ */

+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {

+

+  (void)sdcp;

+  /* TODO: Fill the implementation.*/

+  return false;

+}

+#endif /* HAL_USE_SDC */

+

+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)

+/**

+ * @brief   MMC_SPI card detection.

+ */

+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* TODO: Fill the implementation.*/

+  return true;

+}

+

+/**

+ * @brief   MMC_SPI card write protection detection.

+ */

+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {

+

+  (void)mmcp;

+  /* TODO: Fill the implementation.*/

+  return false;

+}

+#endif

+

+/**

+ * @brief   Board-specific initialization code.

+ * @todo    Add your board-specific code, if any.

+ */

+void boardInit(void) {

+}

diff --git a/os/hal/boards/ST_NUCLEO32_L031K6/board.h b/os/hal/boards/ST_NUCLEO32_L031K6/board.h
new file mode 100644
index 000000000..e5f1e46b0
--- /dev/null
+++ b/os/hal/boards/ST_NUCLEO32_L031K6/board.h
@@ -0,0 +1,1067 @@
+/*

+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef _BOARD_H_

+#define _BOARD_H_

+

+/*

+ * Setup for STMicroelectronics STM32 Nucleo32-L031K6 board.

+ */

+

+/*

+ * Board identifier.

+ */

+#define BOARD_ST_NUCLEO32_L031K6

+#define BOARD_NAME                  "STMicroelectronics STM32 Nucleo32-L031K6"

+

+/*

+ * Board oscillators-related settings.

+ * NOTE: LSE not fitted.

+ * NOTE: HSE not fitted.

+ */

+#if !defined(STM32_LSECLK)

+#define STM32_LSECLK                0U

+#endif

+

+#define STM32_LSEDRV                (3U << 11U)

+

+#if !defined(STM32_HSECLK)

+#define STM32_HSECLK                0U

+#endif

+

+/*

+ * MCU type as defined in the ST header.

+ */

+#define STM32L031xx

+

+/*

+ * IO pins assignments.

+ */

+#define GPIOA_ARD_A0                0U

+#define GPIOA_ARD_A1                1U

+#define GPIOA_VCP_TX                2U

+#define GPIOA_ARD_A2                3U

+#define GPIOA_ARD_A3                4U

+#define GPIOA_ARD_A4                5U

+#define GPIOA_ARD_A5                6U

+#define GPIOA_ARD_A6                7U

+#define GPIOA_ARD_D9                8U

+#define GPIOA_ARD_D1                9U

+#define GPIOA_ARD_D0                10U

+#define GPIOA_ARD_D10               11U

+#define GPIOA_ARD_D2                12U

+#define GPIOA_SWDIO                 13U

+#define GPIOA_SWCLK                 14U

+#define GPIOA_VCP_RX                15U

+

+#define GPIOB_ARD_D3                0U

+#define GPIOB_ARD_D6                1U

+#define GPIOB_PIN2                  2U

+#define GPIOB_ARD_D13               3U

+#define GPIOB_LED_GREEN             3U

+#define GPIOB_ARD_D12               4U

+#define GPIOB_ARD_D11               5U

+#define GPIOB_ARD_D5                6U

+#define GPIOB_ARD_A5_ALT            6U

+#define GPIOB_ARD_D4                7U

+#define GPIOB_ARD_A4_ALT            7U

+#define GPIOB_PIN8                  8U

+#define GPIOB_PIN9                  9U

+#define GPIOB_PIN10                 10U

+#define GPIOB_PIN11                 11U

+#define GPIOB_PIN12                 12U

+#define GPIOB_PIN13                 13U

+#define GPIOB_PIN14                 14U

+#define GPIOB_PIN15                 15U

+

+#define GPIOC_PIN0                  0U

+#define GPIOC_PIN1                  1U

+#define GPIOC_PIN2                  2U

+#define GPIOC_PIN3                  3U

+#define GPIOC_PIN4                  4U

+#define GPIOC_PIN5                  5U

+#define GPIOC_PIN6                  6U

+#define GPIOC_PIN7                  7U

+#define GPIOC_PIN8                  8U

+#define GPIOC_PIN9                  9U

+#define GPIOC_PIN10                 10U

+#define GPIOC_PIN11                 11U

+#define GPIOC_PIN12                 12U

+#define GPIOC_PIN13                 13U

+#define GPIOC_PIN14                 14U

+#define GPIOC_PIN15                 15U

+

+#define GPIOD_PIN0                  0U

+#define GPIOD_PIN1                  1U

+#define GPIOD_PIN2                  2U

+#define GPIOD_PIN3                  3U

+#define GPIOD_PIN4                  4U

+#define GPIOD_PIN5                  5U

+#define GPIOD_PIN6                  6U

+#define GPIOD_PIN7                  7U

+#define GPIOD_PIN8                  8U

+#define GPIOD_PIN9                  9U

+#define GPIOD_PIN10                 10U

+#define GPIOD_PIN11                 11U

+#define GPIOD_PIN12                 12U

+#define GPIOD_PIN13                 13U

+#define GPIOD_PIN14                 14U

+#define GPIOD_PIN15                 15U

+

+#define GPIOE_PIN0                  0U

+#define GPIOE_PIN1                  1U

+#define GPIOE_PIN2                  2U

+#define GPIOE_PIN3                  3U

+#define GPIOE_PIN4                  4U

+#define GPIOE_PIN5                  5U

+#define GPIOE_PIN6                  6U

+#define GPIOE_PIN7                  7U

+#define GPIOE_PIN8                  8U

+#define GPIOE_PIN9                  9U

+#define GPIOE_PIN10                 10U

+#define GPIOE_PIN11                 11U

+#define GPIOE_PIN12                 12U

+#define GPIOE_PIN13                 13U

+#define GPIOE_PIN14                 14U

+#define GPIOE_PIN15                 15U

+

+#define GPIOF_ARD_D7                0U

+#define GPIOF_ARD_D8                1U

+#define GPIOF_PIN2                  2U

+#define GPIOF_PIN3                  3U

+#define GPIOF_PIN4                  4U

+#define GPIOF_PIN5                  5U

+#define GPIOF_PIN6                  6U

+#define GPIOF_PIN7                  7U

+#define GPIOF_PIN8                  8U

+#define GPIOF_PIN9                  9U

+#define GPIOF_PIN10                 10U

+#define GPIOF_PIN11                 11U

+#define GPIOF_PIN12                 12U

+#define GPIOF_PIN13                 13U

+#define GPIOF_PIN14                 14U

+#define GPIOF_PIN15                 15U

+

+#define GPIOH_OSC_IN                0U

+#define GPIOH_OSC_OUT               1U

+#define GPIOH_PIN2                  2U

+#define GPIOH_PIN3                  3U

+#define GPIOH_PIN4                  4U

+#define GPIOH_PIN5                  5U

+#define GPIOH_PIN6                  6U

+#define GPIOH_PIN7                  7U

+#define GPIOH_PIN8                  8U

+#define GPIOH_PIN9                  9U

+#define GPIOH_PIN10                 10U

+#define GPIOH_PIN11                 11U

+#define GPIOH_PIN12                 12U

+#define GPIOH_PIN13                 13U

+#define GPIOH_PIN14                 14U

+#define GPIOH_PIN15                 15U

+

+/*

+ * IO lines assignments.

+ */

+#define LINE_ARD_A0                 PAL_LINE(GPIOA, 0U)

+#define LINE_ARD_A1                 PAL_LINE(GPIOA, 1U)

+#define LINE_VCP_TX                 PAL_LINE(GPIOA, 2U)

+#define LINE_ARD_A2                 PAL_LINE(GPIOA, 3U)

+#define LINE_ARD_A3                 PAL_LINE(GPIOA, 4U)

+#define LINE_ARD_A4                 PAL_LINE(GPIOA, 5U)

+#define LINE_ARD_A5                 PAL_LINE(GPIOA, 6U)

+#define LINE_ARD_A6                 PAL_LINE(GPIOA, 7U)

+#define LINE_ARD_D9                 PAL_LINE(GPIOA, 8U)

+#define LINE_ARD_D1                 PAL_LINE(GPIOA, 9U)

+#define LINE_ARD_D0                 PAL_LINE(GPIOA, 10U)

+#define LINE_ARD_D10                PAL_LINE(GPIOA, 11U)

+#define LINE_ARD_D2                 PAL_LINE(GPIOA, 12U)

+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)

+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)

+#define LINE_VCP_RX                 PAL_LINE(GPIOA, 15U)

+

+#define LINE_ARD_D3                 PAL_LINE(GPIOB, 0U)

+#define LINE_ARD_D6                 PAL_LINE(GPIOB, 1U)

+#define LINE_ARD_D13                PAL_LINE(GPIOB, 3U)

+#define LINE_LED_GREEN              PAL_LINE(GPIOB, 3U)

+#define LINE_ARD_D12                PAL_LINE(GPIOB, 4U)

+#define LINE_ARD_D11                PAL_LINE(GPIOB, 5U)

+#define LINE_ARD_D5                 PAL_LINE(GPIOB, 6U)

+#define LINE_ARD_A5_ALT             PAL_LINE(GPIOB, 6U)

+#define LINE_ARD_D4                 PAL_LINE(GPIOB, 7U)

+#define LINE_ARD_A4_ALT             PAL_LINE(GPIOB, 7U)

+

+

+

+

+#define LINE_ARD_D7                 PAL_LINE(GPIOF, 0U)

+#define LINE_ARD_D8                 PAL_LINE(GPIOF, 1U)

+

+#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)

+#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)

+

+/*

+ * I/O ports initial setup, this configuration is established soon after reset

+ * in the initialization code.

+ * Please refer to the STM32 Reference Manual for details.

+ */

+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))

+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))

+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))

+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))

+#define PIN_ODR_LOW(n)              (0U << (n))

+#define PIN_ODR_HIGH(n)             (1U << (n))

+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))

+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))

+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))

+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))

+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))

+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))

+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))

+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))

+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))

+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))

+

+/*

+ * GPIOA setup:

+ *

+ * PA0  - ARD_A0                    (input pullup).

+ * PA1  - ARD_A1                    (input pullup).

+ * PA2  - VCP_TX                    (alternate 4).

+ * PA3  - ARD_A2                    (input pullup).

+ * PA4  - ARD_A3                    (input pullup).

+ * PA5  - ARD_A4                    (input pullup).

+ * PA6  - ARD_A5                    (input pullup).

+ * PA7  - ARD_A6                    (input pullup).

+ * PA8  - ARD_D9                    (input pullup).

+ * PA9  - ARD_D1                    (input pullup).

+ * PA10 - ARD_D0                    (input pullup).

+ * PA11 - ARD_D10                   (input pullup).

+ * PA12 - ARD_D2                    (input pullup).

+ * PA13 - SWDIO                     (alternate 0).

+ * PA14 - SWCLK                     (alternate 0).

+ * PA15 - VCP_RX                    (alternate 4).

+ */

+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_ARD_A0) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A1) |         \

+                                     PIN_MODE_ALTERNATE(GPIOA_VCP_TX) |     \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A2) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A3) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A4) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A5) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_A6) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_D9) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_D1) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_D0) |         \

+                                     PIN_MODE_INPUT(GPIOA_ARD_D10) |        \

+                                     PIN_MODE_INPUT(GPIOA_ARD_D2) |         \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \

+                                     PIN_MODE_ALTERNATE(GPIOA_VCP_RX))

+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A3) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A4) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A5) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_A6) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D9) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX))

+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_HIGH(GPIOA_ARD_A0) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A1) |        \

+                                     PIN_OSPEED_MEDIUM(GPIOA_VCP_TX) |      \

+                                     PIN_OSPEED_MEDIUM(GPIOA_ARD_A2) |      \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A3) |        \

+                                     PIN_OSPEED_MEDIUM(GPIOA_ARD_A4) |      \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A5) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_A6) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D9) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D1) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D0) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D10) |       \

+                                     PIN_OSPEED_HIGH(GPIOA_ARD_D2) |        \

+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \

+                                     PIN_OSPEED_HIGH(GPIOA_VCP_RX))

+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A1) |       \

+                                     PIN_PUPDR_FLOATING(GPIOA_VCP_TX) |     \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A2) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A3) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A4) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A5) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_A6) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_D9) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_D1) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_D0) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_D10) |      \

+                                     PIN_PUPDR_PULLUP(GPIOA_ARD_D2) |       \

+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \

+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \

+                                     PIN_PUPDR_FLOATING(GPIOA_VCP_RX))

+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_ARD_A0) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A1) |           \

+                                     PIN_ODR_HIGH(GPIOA_VCP_TX) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A2) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A3) |           \

+                                     PIN_ODR_LOW(GPIOA_ARD_A4) |            \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A5) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_A6) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D9) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D1) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D0) |           \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D10) |          \

+                                     PIN_ODR_HIGH(GPIOA_ARD_D2) |           \

+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \

+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \

+                                     PIN_ODR_HIGH(GPIOA_VCP_RX))

+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_ARD_A0, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A1, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_VCP_TX, 4) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A2, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A3, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A4, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A5, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_A6, 0))

+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_ARD_D9, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_D1, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_D0, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_ARD_D10, 0) |        \

+                                     PIN_AFIO_AF(GPIOA_ARD_D2, 0) |         \

+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \

+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \

+                                     PIN_AFIO_AF(GPIOA_VCP_RX, 4))

+

+/*

+ * GPIOB setup:

+ *

+ * PB0  - ARD_D3                    (input pullup).

+ * PB1  - ARD_D6                    (input pullup).

+ * PB2  - PIN2                      (input pullup).

+ * PB3  - ARD_D13 LED_GREEN         (input pullup).

+ * PB4  - ARD_D12                   (input pullup).

+ * PB5  - ARD_D11                   (input pullup).

+ * PB6  - ARD_D5 ARD_A5_ALT         (input pullup).

+ * PB7  - ARD_D4 ARD_A4_ALT         (input pullup).

+ * PB8  - PIN8                      (input pullup).

+ * PB9  - PIN9                      (input pullup).

+ * PB10 - PIN10                     (input pullup).

+ * PB11 - PIN11                     (input pullup).

+ * PB12 - PIN12                     (input pullup).

+ * PB13 - PIN13                     (input pullup).

+ * PB14 - PIN14                     (input pullup).

+ * PB15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_ARD_D3) |         \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D6) |         \

+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D13) |        \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D12) |        \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D11) |        \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D5) |         \

+                                     PIN_MODE_INPUT(GPIOB_ARD_D4) |         \

+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOB_PIN15))

+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_ARD_D3) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D13) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))

+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_ARD_D3) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D6) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D13) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D12) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D11) |       \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D5) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_ARD_D4) |        \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOB_PIN15))

+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_ARD_D3) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D6) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D13) |      \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D12) |      \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D11) |      \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D5) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_ARD_D4) |       \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))

+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_ARD_D3) |           \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D6) |           \

+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D13) |          \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D12) |          \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D11) |          \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D5) |           \

+                                     PIN_ODR_HIGH(GPIOB_ARD_D4) |           \

+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOB_PIN15))

+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_ARD_D3, 0) |         \

+                                     PIN_AFIO_AF(GPIOB_ARD_D6, 0) |         \

+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOB_ARD_D13, 0) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D12, 0) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D11, 0) |        \

+                                     PIN_AFIO_AF(GPIOB_ARD_D5, 0) |         \

+                                     PIN_AFIO_AF(GPIOB_ARD_D4, 0))

+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))

+

+/*

+ * GPIOC setup:

+ *

+ * PC0  - PIN0                      (input pullup).

+ * PC1  - PIN1                      (input pullup).

+ * PC2  - PIN2                      (input pullup).

+ * PC3  - PIN3                      (input pullup).

+ * PC4  - PIN4                      (input pullup).

+ * PC5  - PIN5                      (input pullup).

+ * PC6  - PIN6                      (input pullup).

+ * PC7  - PIN7                      (input pullup).

+ * PC8  - PIN8                      (input pullup).

+ * PC9  - PIN9                      (input pullup).

+ * PC10 - PIN10                     (input pullup).

+ * PC11 - PIN11                     (input pullup).

+ * PC12 - PIN12                     (input pullup).

+ * PC13 - PIN13                     (input pullup).

+ * PC14 - PIN14                     (input pullup).

+ * PC15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOC_PIN15))

+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))

+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOC_PIN15))

+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))

+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOC_PIN15))

+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))

+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOC_PIN15, 0))

+

+/*

+ * GPIOD setup:

+ *

+ * PD0  - PIN0                      (input pullup).

+ * PD1  - PIN1                      (input pullup).

+ * PD2  - PIN2                      (input pullup).

+ * PD3  - PIN3                      (input pullup).

+ * PD4  - PIN4                      (input pullup).

+ * PD5  - PIN5                      (input pullup).

+ * PD6  - PIN6                      (input pullup).

+ * PD7  - PIN7                      (input pullup).

+ * PD8  - PIN8                      (input pullup).

+ * PD9  - PIN9                      (input pullup).

+ * PD10 - PIN10                     (input pullup).

+ * PD11 - PIN11                     (input pullup).

+ * PD12 - PIN12                     (input pullup).

+ * PD13 - PIN13                     (input pullup).

+ * PD14 - PIN14                     (input pullup).

+ * PD15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOD_PIN15))

+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))

+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_HIGH(GPIOD_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOD_PIN15))

+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))

+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOD_PIN15))

+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))

+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))

+

+/*

+ * GPIOE setup:

+ *

+ * PE0  - PIN0                      (input pullup).

+ * PE1  - PIN1                      (input pullup).

+ * PE2  - PIN2                      (input pullup).

+ * PE3  - PIN3                      (input pullup).

+ * PE4  - PIN4                      (input pullup).

+ * PE5  - PIN5                      (input pullup).

+ * PE6  - PIN6                      (input pullup).

+ * PE7  - PIN7                      (input pullup).

+ * PE8  - PIN8                      (input pullup).

+ * PE9  - PIN9                      (input pullup).

+ * PE10 - PIN10                     (input pullup).

+ * PE11 - PIN11                     (input pullup).

+ * PE12 - PIN12                     (input pullup).

+ * PE13 - PIN13                     (input pullup).

+ * PE14 - PIN14                     (input pullup).

+ * PE15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOE_PIN15))

+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))

+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_HIGH(GPIOE_PIN0) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN1) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOE_PIN15))

+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))

+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOE_PIN15))

+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN1, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))

+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))

+

+/*

+ * GPIOF setup:

+ *

+ * PF0  - ARD_D7                    (input pullup).

+ * PF1  - ARD_D8                    (input pullup).

+ * PF2  - PIN2                      (input pullup).

+ * PF3  - PIN3                      (input pullup).

+ * PF4  - PIN4                      (input pullup).

+ * PF5  - PIN5                      (input pullup).

+ * PF6  - PIN6                      (input pullup).

+ * PF7  - PIN7                      (input pullup).

+ * PF8  - PIN8                      (input pullup).

+ * PF9  - PIN9                      (input pullup).

+ * PF10 - PIN10                     (input pullup).

+ * PF11 - PIN11                     (input pullup).

+ * PF12 - PIN12                     (input pullup).

+ * PF13 - PIN13                     (input pullup).

+ * PF14 - PIN14                     (input pullup).

+ * PF15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_ARD_D7) |         \

+                                     PIN_MODE_INPUT(GPIOF_ARD_D8) |         \

+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOF_PIN15))

+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))

+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_HIGH(GPIOF_ARD_D7) |        \

+                                     PIN_OSPEED_HIGH(GPIOF_ARD_D8) |        \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOF_PIN15))

+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_ARD_D7) |       \

+                                     PIN_PUPDR_PULLUP(GPIOF_ARD_D8) |       \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))

+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_ARD_D7) |           \

+                                     PIN_ODR_HIGH(GPIOF_ARD_D8) |           \

+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOF_PIN15))

+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_ARD_D7, 0) |         \

+                                     PIN_AFIO_AF(GPIOF_ARD_D8, 0) |         \

+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))

+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))

+

+/*

+ * GPIOH setup:

+ *

+ * PH0  - OSC_IN                    (input floating).

+ * PH1  - OSC_OUT                   (input floating).

+ * PH2  - PIN2                      (input pullup).

+ * PH3  - PIN3                      (input pullup).

+ * PH4  - PIN4                      (input pullup).

+ * PH5  - PIN5                      (input pullup).

+ * PH6  - PIN6                      (input pullup).

+ * PH7  - PIN7                      (input pullup).

+ * PH8  - PIN8                      (input pullup).

+ * PH9  - PIN9                      (input pullup).

+ * PH10 - PIN10                     (input pullup).

+ * PH11 - PIN11                     (input pullup).

+ * PH12 - PIN12                     (input pullup).

+ * PH13 - PIN13                     (input pullup).

+ * PH14 - PIN14                     (input pullup).

+ * PH15 - PIN15                     (input pullup).

+ */

+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \

+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \

+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \

+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \

+                                     PIN_MODE_INPUT(GPIOH_PIN15))

+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \

+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))

+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_HIGH(GPIOH_OSC_IN) |        \

+                                     PIN_OSPEED_HIGH(GPIOH_OSC_OUT) |       \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN2) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN3) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN4) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN5) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN6) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN7) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN8) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN9) |          \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN10) |         \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN11) |         \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN12) |         \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN13) |         \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN14) |         \

+                                     PIN_OSPEED_HIGH(GPIOH_PIN15))

+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \

+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \

+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))

+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \

+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \

+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \

+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \

+                                     PIN_ODR_HIGH(GPIOH_PIN15))

+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \

+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \

+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))

+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \

+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \

+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))

+

+

+#if !defined(_FROM_ASM_)

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void boardInit(void);

+#ifdef __cplusplus

+}

+#endif

+#endif /* _FROM_ASM_ */

+

+#endif /* _BOARD_H_ */

diff --git a/os/hal/boards/ST_NUCLEO32_L031K6/board.mk b/os/hal/boards/ST_NUCLEO32_L031K6/board.mk
new file mode 100644
index 000000000..cc4a062af
--- /dev/null
+++ b/os/hal/boards/ST_NUCLEO32_L031K6/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.

+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L031K6/board.c

+

+# Required include directories

+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L031K6

diff --git a/os/hal/boards/ST_NUCLEO32_L031K6/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO32_L031K6/cfg/board.chcfg
new file mode 100644
index 000000000..41e308c5b
--- /dev/null
+++ b/os/hal/boards/ST_NUCLEO32_L031K6/cfg/board.chcfg
@@ -0,0 +1,929 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F0xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l0xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32l0xx/templates</templates_path>
+    <output_path>..</output_path>
+    <hal_version>3.0.x</hal_version>
+  </configuration_settings>
+  <board_name>STMicroelectronics STM32 Nucleo32-L031K6</board_name>
+  <board_id>ST_NUCLEO32_L031K6</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32L031xx</subtype>
+  <clocks HSEFrequency="0" HSEBypass="false" LSEFrequency="0"
+  	LSEBypass="false" LSEDrive="3 High Drive (default)" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="ARD_A0"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="ARD_A1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="VCP_TX"
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin3
+        ID="ARD_A2"
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="ARD_A3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="ARD_A4"
+        Type="PushPull"
+        Level="Low"
+        Speed="High"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="ARD_A5"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="ARD_A6"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="ARD_D9"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="ARD_D1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="ARD_D0"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="ARD_D10"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID="ARD_D2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullDown"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID="VCP_RX"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID="ARD_D3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="ARD_D6"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="ARD_D13 LED_GREEN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID="ARD_D12"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="ARD_D11"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="ARD_D5 ARD_A5_ALT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="ARD_D4 ARD_A4_ALT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID="ARD_D7"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="ARD_D8"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+    <GPIOH>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+  </ports>
+</board>