git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3797 35acf78f-673a-0410-8e92-d51de3d6d3f4

8 files changed, 88 insertions, 136 deletions

diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index 478b16f39..b90b1e668 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -53,71 +53,44 @@ RTCDriver RTCD1;
 /*===========================================================================*/

 

 /**

- * @brief   Shared IRQ handler.

- *

- * @param[in] rtcp    pointer to a @p RTCDriver object

+ * @brief   Wait for synchronization of RTC registers with APB1 bus.

+ * @details This function must be invoked before trying to read RTC registers

+ *          in the backup domain: DIV, CNT, ALR. CR registers can always

+ *          be read.

  *

  * @notapi

  */

-static void rtc_lld_serve_interrupt(RTCDriver *rtcp) {

-

-  PWR->CR |= PWR_CR_DBP;

-  chSysLockFromIsr();

-

-  if ((RTC->CRH & RTC_CRH_SECIE) && (RTC->CRL & RTC_CRL_SECF)) {

-    rtcp->callback(rtcp, RTC_EVENT_SECOND);

-    RTC->CRL &= ~RTC_CRL_SECF;

-  }

-  if ((RTC->CRH & RTC_CRH_ALRIE) && (RTC->CRL & RTC_CRL_ALRF)) {

-    rtcp->callback(rtcp, RTC_EVENT_ALARM);

-    RTC->CRL &= ~RTC_CRL_ALRF;

-  }

-  if ((RTC->CRH & RTC_CRH_OWIE) && (RTC->CRL & RTC_CRL_OWF)) {

-    rtcp->callback(rtcp, RTC_EVENT_OVERFLOW);

-    RTC->CRL &= ~RTC_CRL_OWF;

-  }

-

-  chSysUnlockFromIsr();

-  PWR->CR &= ~PWR_CR_DBP;

-}

+static void rtc_lld_apb1_sync(void) {

 

-/**

- * @brief   Wait for synchronization of RTC registers.

- * @details Ensure that RTC_CNT and RTC_DIV contain actual values after

- *          enabling clocking on APB1, because these values only update

- *          when APB1 functioning.

- *

- * @notapi

- */

-static void rtc_lld_wait_sync(void) {

-  while (!(RTC->CRL & RTC_CRL_RSF))

+  while ((RTC->CRL & RTC_CRL_RSF) == 0)

     ;

 }

 

 /**

- * @brief   Acquire exclusive write access to RTC registers.

+ * @brief   Acquires write access to RTC registers.

+ * @details Before writing to the backup domain RTC registers the previous

+ *          write operation must be completed. Use this function before

+ *          writing to PRL, CNT, ALR registers. CR registers can always

+ *          be written.

  *

  * @notapi

  */

 static void rtc_lld_acquire(void) {

 

-  /* Waits registers write completion.*/

-BEGIN:

   while ((RTC->CRL & RTC_CRL_RTOFF) == 0)

     ;

-  chSysLock();

-  if ((RTC->CRL & RTC_CRL_RTOFF) == 0){

-    chSysUnlock();

-    goto BEGIN;

-  }

+  RTC->CRL |= RTC_CRL_CNF;

 }

 

 /**

- * @brief   Release exclusive write access to RTC registers.

+ * @brief   Releases write access to RTC registers.

  *

  * @notapi

  */

-#define rtc_lld_release() {chSysUnlock();}

+static void  rtc_lld_release(void) {

+

+  RTC->CRL &= ~RTC_CRL_CNF;

+}

 

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

@@ -129,10 +102,22 @@ BEGIN:
  * @isr

  */

 CH_IRQ_HANDLER(RTC_IRQHandler) {

+  uint16_t flags;

 

   CH_IRQ_PROLOGUE();

 

-  rtc_lld_serve_interrupt(&RTCD1);

+  /* Mask of all enabled and pending sources.*/

+  flags = RTC->CRH & RTC->CRL;

+  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);

+

+  if (flags & RTC_CRL_SECF)

+    RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);

+

+  if (flags & RTC_CRL_ALRF)

+    RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);

+

+  if (flags & RTC_CRL_OWF)

+    RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);

 

   CH_IRQ_EPILOGUE();

 }

@@ -151,36 +136,26 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
  */

 void rtc_lld_init(void){

 

-  PWR->CR |= PWR_CR_DBP;

+  /* Required because access to PRL.*/

+  rtc_lld_apb1_sync();

 

-  RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);

-  rtc_lld_wait_sync();

-

-  /* Write preload register only if its value is not equal to desired value.*/

+  /* Writes preload register only if its value is not equal to desired value.*/

   if (STM32_RTCCLK != (((uint32_t)(RTC->PRLH)) << 16) +

                        ((uint32_t)RTC->PRLL) + 1) {

-

-    /* Enters configuration mode and writes PRLx registers then leaves the

-       configuration mode.*/

     rtc_lld_acquire();

-    RTC->CRL |= RTC_CRL_CNF;

     RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16);

     RTC->PRLL = (uint16_t)((STM32_RTCCLK - 1) & 0xFFFF);

-    RTC->CRL &= ~RTC_CRL_CNF;

     rtc_lld_release();

   }

 

   /* All interrupts initially disabled.*/

-  if (RTC->CRH != 0){

-    rtc_lld_acquire();

-    RTC->CRH = 0;

-    rtc_lld_release();

-  }

-

-  PWR->CR &= ~PWR_CR_DBP;

+  RTC->CRH = 0;

 

   /* Callback initially disabled.*/

   RTCD1.callback = NULL;

+

+  /* IRQ vector permanently assigned to this driver.*/

+  nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));

 }

 

 /**

@@ -197,14 +172,10 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
 

   (void)rtcp;

 

-  PWR->CR |= PWR_CR_DBP;

   rtc_lld_acquire();

-  RTC->CRL |= RTC_CRL_CNF;

   RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16);

   RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF);

-  RTC->CRL &= ~RTC_CRL_CNF;

   rtc_lld_release();

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /**

@@ -220,9 +191,10 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {
 

   uint32_t time_frac;

 

-  /* The read is repeated until we are able to do it twice and obtain the

-     same result.*/

-  rtc_lld_wait_sync();

+  /* Required because access to CNT and DIV.*/

+  rtc_lld_apb1_sync();

+

+  /* Loops until two consecutive read returning the same value.*/

   do {

     timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;

     time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;

@@ -250,11 +222,7 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
   (void)rtcp;

   (void)alarm;

 

-  /* Enters configuration mode and writes ALRHx registers then leaves the

-     configuration mode.*/

-  PWR->CR |= PWR_CR_DBP;

   rtc_lld_acquire();

-  RTC->CRL |= RTC_CRL_CNF;

   if (alarmspec != NULL) {

     RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);

     RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);

@@ -263,9 +231,7 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
     RTC->ALRH = 0;

     RTC->ALRL = 0;

   }

-  RTC->CRL &= ~RTC_CRL_CNF;

   rtc_lld_release();

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /**

@@ -288,7 +254,9 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
   (void)rtcp;

   (void)alarm;

 

-  rtc_lld_wait_sync();

+  /* Required because access to ALR.*/

+  rtc_lld_apb1_sync();

+

   alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL);

 }

 

@@ -304,25 +272,20 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
  */

 void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {

 

-  PWR->CR |= PWR_CR_DBP;

-  rtc_lld_acquire();

   if (callback != NULL) {

+

+    /* IRQ sources enabled only after setting up the callback.*/

     rtcp->callback = callback;

 

-    /* Interrupts are enabled only after setting up the callback, this

-       way there is no need to check for the NULL callback pointer inside

-       the IRQ handler.*/

     RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);

-    nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY));

-    RTC->CRH |= RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;

+    RTC->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;

   }

   else {

-    nvicDisableVector(RTC_IRQn);

-    RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);

-    RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE);

+    RTC->CRH = 0;

+

+    /* Callback set to NULL only after disabling the IRQ sources.*/

+    rtcp->callback = NULL;

   }

-  rtc_lld_release();

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 #endif /* HAL_USE_RTC */

diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
index aaf639492..6f55ab573 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
@@ -103,12 +103,10 @@ typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
  * @brief   Structure representing an RTC callbacks config.

  */

 struct RTCCallbackConfig{

-#if RTC_SUPPORTS_CALLBACKS

   /**

    * @brief Generic RTC callback pointer.

    */

   rtccb_t           callback;

-#endif /* RTC_SUPPORTS_CALLBACKS */

 };

 

 /**

diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index 0112d7eaa..f903106cb 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -46,8 +46,8 @@
  */

 static void hal_lld_backup_domain_init(void) {

 

-  /* Backup domain access enabled during initialization.*/

-  PWR->CR |= PWR_CR_DBP;

+  /* Backup domain access enabled and left open.*/

+  PWR->CR = PWR_CR_DBP;

 

   /* If enabled then the LSE is started.*/

 #if STM32_LSE_ENABLED

@@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;

   }

 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

-

-  /*  Backup domain access disabled for operations safety.*/

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index 7cc24f2a0..8dc079187 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -46,8 +46,8 @@
  */

 static void hal_lld_backup_domain_init(void) {

 

-  /* Backup domain access enabled during initialization.*/

-  PWR->CR |= PWR_CR_DBP;

+  /* Backup domain access enabled and left open.*/

+  PWR->CR = PWR_CR_DBP;

 

   /* If enabled then the LSE is started.*/

 #if STM32_LSE_ENABLED

@@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;

   }

 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

-

-  /*  Backup domain access disabled for operations safety.*/

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 00c560f08..3dd520c2c 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -46,8 +46,8 @@
  */

 static void hal_lld_backup_domain_init(void) {

 

-  /* Backup domain access enabled during initialization.*/

-  PWR->CR |= PWR_CR_DBP;

+  /* Backup domain access enabled and left open.*/

+  PWR->CR = PWR_CR_DBP;

 

   /* If enabled then the LSE is started.*/

 #if STM32_LSE_ENABLED

@@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;

   }

 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

-

-  /*  Backup domain access disabled for operations safety.*/

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
index 4e1b385a3..e4b21ede3 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.c
+++ b/os/hal/platforms/STM32L1xx/hal_lld.c
@@ -46,8 +46,8 @@
  */

 static void hal_lld_backup_domain_init(void) {

 

-  /* Backup domain access enabled during initialization.*/

-  PWR->CR |= PWR_CR_DBP;

+  /* Backup domain access enabled and left open.*/

+  PWR->CR = PWR_CR_DBP;

 

   /* If enabled then the LSE is started.*/

 #if STM32_LSE_ENABLED

@@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->CSR |= RCC_CSR_RTCEN;

   }

 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

-

-  /*  Backup domain access disabled for operations safety.*/

-  PWR->CR &= ~PWR_CR_DBP;

 }

 

 /*===========================================================================*/

diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c
index d7750001d..1f463eb38 100644
--- a/os/hal/src/rtc.c
+++ b/os/hal/src/rtc.c
@@ -141,8 +141,8 @@ void rtcGetAlarm(RTCDriver *rtcp,
 #if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__)

 /**

  * @brief   Enables or disables RTC callbacks.

- * @details This function enables or disables callbacks, use a @p NULL pointer

- *          in order to disable a callback.

+ * @details This function enables or disables the callback, use a @p NULL

+ *          pointer in order to disable it.

  *

  * @param[in] rtcp      pointer to RTC driver structure

  * @param[in] callback  callback function pointer or @p NULL

diff --git a/todo.txt b/todo.txt
index c1325f5f7..8079a4cbc 100644
--- a/todo.txt
+++ b/todo.txt
@@ -5,38 +5,43 @@ X = In progress, some work done.
 ? = Not sure if worth the effort or useful at all.

 N = Decided against.

 

-Current Pipeline (2.3.x):

-* I2C device driver class support and at least one implementation.

-* Consistency check of all halconf.h files.

-* Consistency check of all STM32xx mcuconf.h files.

-* Revision of the RTCv1 driver implementation.

-* Fixing issue with Simulator and CH_DBG_SYSTEM_STATE_CHECK option.

-X STM32F2 validation (so far done testing on STM32F4).

+Current Pipeline (2.4.0):

+X Revision of the RTCv1 driver implementation.

+- Posix simulator tickets and test.

+- Complete test cycle.

+- Complete documentation cycle.

+

+Version 2.4.1

+X STM32F2 validation (so far testing done on STM32F4 only).

 X Revision of the RTCv2 driver implementation.

-- SDC driver port to STM32F2 and STM32F4.

-- CAN driver test on STM32F4.

+X SDC driver port to STM32F2 and STM32F4.

+- CAN2 support and CAN driver test on STM32F2/F4.

 

-Within 2.x.x

-- Nios II support.

+Within 2.5.x:

+- Revision of scheduling strategy for threads at equal priority.

+- Add a chSysIntegrityCheck() API to the kernel.

+- Add a CH_THREAD macro for threads declaration in order to hide

+  compiler-specific optimizations for thread functions. All demos will have

+  to be updated.

+- Runtime errors manager in HAL.

+- Critical errors manager in HAL (to replace or complement assertions).

+- MMC_SPI driver speedup.

+- USB driver model revision.

+- MAC driver for STM32F107, STM32F2xx, STM32F4xx.

+- STM32 OTG USB cell support for CL, F2, F4 devices.

+- Add ADC3 support to the STM32 ADC driver.

 - Update C++ wrapper.

 - FatFs 0.9x integration.

-- Software I2C implementation using a GPT instance for timings.

+- Nios II support.

 - LPC17xx support.

 - NUC120 support.

-- MMC_SPI driver speedup.

+

+Within 2.x.x

+- Software I2C implementation using a GPT instance for timings.

 - Static memory allocation hook macros in kernel code.

-- MAC driver for STM32F107, STM32F2xx, STM32F4xx.

-- USB driver model revision.

-  ? USB double buffering support for STM32 implementation.

-  X Evaluate using DMA channels for buffer copy.

 X File System infrastructure.

 X Implement the "transmission end" serial driver event on those platforms

   supporting the feature, so far only done in STM32 driver.

-- Revision of scheduling strategy for threads at equal priority.

-- Add a chSysIntegrityCheck() API.

-- Add a CH_THREAD macro for threads declaration in order to hide

-  compiler-specific optimizations for thread functions. All demos will have

-  to be updated.

 - Test suite overhaul, the API should be more generic in order to be used

   with different subsystems and not just the kernel.

 - Reduce number of demos globally, add demos to a repository or on web site.

@@ -45,8 +50,6 @@ X Implement the "transmission end" serial driver event on those platforms
 - New device driver models: Clock, Systick, WDG, DAC, Power Monitor.

 - Add UART4 support to the STM32 UART driver (CL line only, HD has a nasty

   shared interrupt).

-- STM32 OTG USB cell support for CL, F2, F4 devices.

-- Add ADC3 support to the STM32 ADC driver.

 - Shared DMA channels support in the STM8L HAL.

 - Device drivers for STM8/STM8L (ADC, PWM, bring them on par with STM32).

 - Device drivers for LPC1xxx (ADC, PWM, bring them on par with STM32).