I2C. Examples update.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3051 35acf78f-673a-0410-8e92-d51de3d6d3f4

8 files changed, 250 insertions, 185 deletions

diff --git a/testhal/STM32/I2C/Makefile b/testhal/STM32/I2C/Makefile
index 888e33eb2..62eef3874 100644
--- a/testhal/STM32/I2C/Makefile
+++ b/testhal/STM32/I2C/Makefile
@@ -78,8 +78,8 @@ CSRC = $(PORTSRC) \
        main.c \

        i2c_pns.c \

 	   lis3.c\

-	   tmp75.c\

 	   max1236.c\

+	   tmp75.c\

        

 # C++ sources that can be compiled in ARM or THUMB mode depending on the global

 # setting.

diff --git a/testhal/STM32/I2C/ch.ld b/testhal/STM32/I2C/ch.ld
index 44f494121..4d97e7682 100644
--- a/testhal/STM32/I2C/ch.ld
+++ b/testhal/STM32/I2C/ch.ld
@@ -1,5 +1,6 @@
 /*

-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

 

     This file is part of ChibiOS/RT.

 

@@ -37,11 +38,32 @@ __ram_end__             = __ram_start__ + __ram_size__;
 SECTIONS

 {

     . = 0;

+    _text = .;

 

-    .text : ALIGN(16) SUBALIGN(16)

+    startup : ALIGN(16) SUBALIGN(16)

     {

-        _text = .;

         KEEP(*(vectors))

+    } > flash

+

+    constructors : ALIGN(4) SUBALIGN(4)

+    {

+        PROVIDE(__init_array_start = .);

+        KEEP(*(SORT(.init_array.*)))

+        KEEP(*(.init_array))

+        PROVIDE(__init_array_end = .);

+    } > flash

+

+    destructors : ALIGN(4) SUBALIGN(4)

+    {

+        PROVIDE(__fini_array_start = .);

+        KEEP(*(.fini_array))

+        KEEP(*(SORT(.fini_array.*)))

+        PROVIDE(__fini_array_end = .);

+    } > flash

+

+    .text : ALIGN(16) SUBALIGN(16)

+    {

+        *(.text.startup.*)

         *(.text)

         *(.text.*)

         *(.rodata)

@@ -51,31 +73,26 @@ SECTIONS
         *(.gcc*)

     } > flash

 

-    .ctors :

+    .ARM.extab :

     {

-        PROVIDE(_ctors_start_ = .);

-        KEEP(*(SORT(.ctors.*)))

-        KEEP(*(.ctors))

-        PROVIDE(_ctors_end_ = .);

+        *(.ARM.extab* .gnu.linkonce.armextab.*)

     } > flash

 

-    .dtors :

+    .ARM.exidx : {

+        PROVIDE(__exidx_start = .);

+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+        PROVIDE(__exidx_end = .);

+     } > flash

+

+    .eh_frame_hdr :

     {

-        PROVIDE(_dtors_start_ = .);

-        KEEP(*(SORT(.dtors.*)))

-        KEEP(*(.dtors))

-        PROVIDE(_dtors_end_ = .);

+        *(.eh_frame_hdr)

     } > flash

 

-    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}

-

-    __exidx_start = .;

-    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash

-    __exidx_end = .;

-

-    .eh_frame_hdr : {*(.eh_frame_hdr)}

-

-    .eh_frame : ONLY_IF_RO {*(.eh_frame)}

+    .eh_frame : ONLY_IF_RO

+    {

+        *(.eh_frame)

+    } > flash

 

     . = ALIGN(4);

     _etext = .;

@@ -83,26 +100,26 @@ SECTIONS
 

     .data :

     {

-        _data = .;

+        PROVIDE(_data = .);

         *(.data)

         . = ALIGN(4);

         *(.data.*)

         . = ALIGN(4);

         *(.ramtext)

         . = ALIGN(4);

-        _edata = .;

+        PROVIDE(_edata = .);

     } > ram AT > flash

 

     .bss :

     {

-        _bss_start = .;

+        PROVIDE(_bss_start = .);

         *(.bss)

         . = ALIGN(4);

         *(.bss.*)

         . = ALIGN(4);

         *(COMMON)

         . = ALIGN(4);

-        _bss_end = .;

+        PROVIDE(_bss_end = .);

     } > ram    

 }

 

diff --git a/testhal/STM32/I2C/chconf.h b/testhal/STM32/I2C/chconf.h
index 657ddf887..9f5273ba5 100644
--- a/testhal/STM32/I2C/chconf.h
+++ b/testhal/STM32/I2C/chconf.h
@@ -89,6 +89,23 @@
 #define CH_MEMCORE_SIZE                 0

 #endif

 

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread automatically. The application has

+ *          then the responsibility to do one of the following:

+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.

+ *          - Change the main() thread priority to @p IDLEPRIO then enter

+ *            an endless loop. In this scenario the @p main() thread acts as

+ *            the idle thread.

+ *          .

+ * @note    Unless an idle thread is spawned the @p main() thread must not

+ *          enter a sleep state.

+ */

+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)

+#define CH_NO_IDLE_THREAD               FALSE

+#endif

+

 /*===========================================================================*/

 /* Performance options.                                                      */

 /*===========================================================================*/

@@ -105,26 +122,6 @@
 #define CH_OPTIMIZE_SPEED               FALSE

 #endif

 

-/**

- * @brief   Exotic optimization.

- * @details If defined then a CPU register is used as storage for the global

- *          @p currp variable. Caching this variable in a register greatly

- *          improves both space and time OS efficiency. A side effect is that

- *          one less register has to be saved during the context switch

- *          resulting in lower RAM usage and faster context switch.

- *

- * @note    This option is only usable with the GCC compiler and is only useful

- *          on processors with many registers like ARM cores.

- * @note    If this option is enabled then ALL the libraries linked to the

- *          ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p

- *          -ffixed-@<reg@>.

- * @note    This option must be enabled in the Makefile, it is listed here for

- *          documentation only.

- */

-#if defined(__DOXYGEN__)

-#define CH_CURRP_REGISTER_CACHE         "reg"

-#endif

-

 /*===========================================================================*/

 /* Subsystem options.                                                        */

 /*===========================================================================*/

diff --git a/testhal/STM32/I2C/halconf.h b/testhal/STM32/I2C/halconf.h
index 9a7979cc9..b128d89cf 100644
--- a/testhal/STM32/I2C/halconf.h
+++ b/testhal/STM32/I2C/halconf.h
@@ -55,6 +55,13 @@
 #endif

 

 /**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                 FALSE

+#endif

+

+/**

  * @brief   Enables the I2C subsystem.

  */

 #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

@@ -62,6 +69,13 @@
 #endif

 

 /**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                 FALSE

+#endif

+

+/**

  * @brief   Enables the MAC subsystem.

  */

 #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

@@ -83,10 +97,24 @@
 #endif

 

 /**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                 FALSE

+#endif

+

+/**

  * @brief   Enables the SERIAL subsystem.

  */

 #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

-#define HAL_USE_SERIAL              FALSE

+#define HAL_USE_SERIAL              TRUE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB          FALSE

 #endif

 

 /**

@@ -100,7 +128,14 @@
  * @brief   Enables the UART subsystem.

  */

 #if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

-#define HAL_USE_UART                TRUE

+#define HAL_USE_UART                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                 FALSE

 #endif

 

 /*===========================================================================*/

@@ -207,6 +242,36 @@
 /*===========================================================================*/

 

 /*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intevals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY              100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT             FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

 /* SERIAL driver related settings.                                           */

 /*===========================================================================*/

 

@@ -216,7 +281,7 @@
  *          default configuration.

  */

 #if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

-#define SERIAL_DEFAULT_BITRATE      38400

+#define SERIAL_DEFAULT_BITRATE      57600

 #endif

 

 /**

@@ -227,7 +292,7 @@
  *          buffers.

  */

 #if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

-#define SERIAL_BUFFERS_SIZE         16

+#define SERIAL_BUFFERS_SIZE         256

 #endif

 

 /*===========================================================================*/

diff --git a/testhal/STM32/I2C/lis3.c b/testhal/STM32/I2C/lis3.c
index 06f6da1d0..7e7c9d221 100644
--- a/testhal/STM32/I2C/lis3.c
+++ b/testhal/STM32/I2C/lis3.c
@@ -30,19 +30,21 @@ static void i2c_lis3_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
 static I2CSlaveConfig lis3 = {

   NULL,

   i2c_lis3_error_cb,

-  accel_rx_data,

-  ACCEL_RX_DEPTH,

   0,

   0,

+  accel_rx_data,

   accel_tx_data,

-  ACCEL_TX_DEPTH,

+  0b0011101,

+  7,

   0,

   0,

-  0b0011101,

-  FALSE,

+  {NULL},

 };

 

 

+

+

+

 /**

  * This treading need for convenient realize

  * "read through write" process.

@@ -82,26 +84,13 @@ static msg_t I2CAccelThread(void *arg) {
 

 /* This callback raise up when transfer finished */

 static void i2c_lis3_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){

+  (void) i2cscfg;

 

-  if (i2cp->id_slave_config->restart){ // is it restart flag set to TRUE

-    /* reset restart flag */

-    i2cp->id_slave_config->restart = FALSE;

-    /* now send restart and read acceleration data.

-     * Function i2cMasterReceive() send restart implicitly. */

-    i2cMasterReceive(i2cp, i2cscfg);

-  }

-  else{

-    /* If jump here than requested data have been read.

-     * Stop communication, release bus and wake up processing thread */

-    i2cMasterStop(i2cp);

-    i2cReleaseBus(&I2CD1);

-

-    // wake up heavy thread for data processing

-    if (i2c_accel_tp != NULL) {

-      i2c_accel_tp->p_msg = (msg_t)i2cp;

-      chSchReadyI(i2c_accel_tp);

-      i2c_accel_tp = NULL;

-    }

+  // only wake up processing thread

+  if (i2c_accel_tp != NULL) {

+    i2c_accel_tp->p_msg = (msg_t)i2cp;

+    chSchReadyI(i2c_accel_tp);

+    i2c_accel_tp = NULL;

   }

 }

 

@@ -121,25 +110,19 @@ int init_lis3(void){
   while (i2c_accel_tp == NULL)

     chThdSleepMilliseconds(1);

 

-  lis3.txbufhead = 0;

-  lis3.rxbufhead = 0;

-

+  lis3.rxbytes = 0; //set to 0 because we need only transmit

 

-  /* Write configuration data */

+  /* configure accelerometer */

   lis3.txbytes = 4;

-  /* fill transmit buffer. See datasheet to understand what we write */

-  lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT;

+  lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; // register address

   lis3.txbuf[1] = 0b11100111;

   lis3.txbuf[2] = 0b01000001;

   lis3.txbuf[3] = 0b00000000;

 

-  /* setting callback */

-  lis3.id_callback = i2c_lis3_cb;

-

-  i2cAcquireBus(&I2CD1);

-

   /* sending */

   i2cMasterTransmit(&I2CD1, &lis3);

+  chThdSleepMilliseconds(1);

+  lis3.id_callback = i2c_lis3_cb;

 

   return 0;

 }

@@ -148,23 +131,11 @@ int init_lis3(void){
  *

  */

 void request_acceleration_data(void){

-

-  /* fill transmit buffer with address of register that we want to read */

-  lis3.txbufhead = 0;

   lis3.txbuf[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address

   lis3.txbytes = 1;

-

-  /* tune receive structures */

-  lis3.rxbufhead = 0;

   lis3.rxbytes = 6;

-

-  /* Now it is most important action. We must set restart flag to TRUE.

-   * And in callback function we must reset it to FALSE after sending

-   * of register address. In TMP75 and MAX1236 this flag does not use. */

-  lis3.restart = TRUE;

-

-  /* talk to slave what we want from it */

   i2cAcquireBus(&I2CD1);

   i2cMasterTransmit(&I2CD1, &lis3);

+  i2cReleaseBus(&I2CD1);

 }

 

diff --git a/testhal/STM32/I2C/max1236.c b/testhal/STM32/I2C/max1236.c
index e7e253916..36a77ff03 100644
--- a/testhal/STM32/I2C/max1236.c
+++ b/testhal/STM32/I2C/max1236.c
@@ -13,6 +13,9 @@
 // Data buffers

 static i2cblock_t max1236_rx_data[MAX1236_RX_DEPTH];

 static i2cblock_t max1236_tx_data[MAX1236_TX_DEPTH];

+// ADC results

+static uint16_t ch1 = 0, ch2 = 0, ch3 = 0, ch4 = 0;

+

 

 /* Error trap */

 static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){

@@ -25,17 +28,7 @@ static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
 

 /* This callback raise up when transfer finished */

 static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){

-  uint16_t ch1 = 0;

-  uint16_t ch2 = 0;

-  uint16_t ch3 = 0;

-  uint16_t ch4 = 0;

-

-  /* send stop */

-  i2cMasterStop(i2cp);

-

-  /* unlock bus */

-  i2cReleaseBus(&I2CD2);

-

+  (void)*i2cp;

   /* get ADC data */

   ch1 = ((i2cscfg->rxbuf[0] & 0xF) << 8) + i2cscfg->rxbuf[1];

   ch2 = ((i2cscfg->rxbuf[2] & 0xF) << 8) + i2cscfg->rxbuf[3];

@@ -45,19 +38,19 @@ static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
 

 

 // ADC maxim MAX1236 config

+

 static I2CSlaveConfig max1236 = {

-  NULL, // first set to NULL. We will set this pointer to the function later.

-  i2c_max1236_error_cb,

-  max1236_rx_data,

-  MAX1236_RX_DEPTH,

-  0,

-  0,

-  max1236_tx_data,

-  MAX1236_TX_DEPTH,

-  0,

-  0,

-  0b0110100,

-  FALSE,

+    NULL,

+    i2c_max1236_error_cb,

+    0,

+    0,

+    max1236_rx_data,

+    max1236_tx_data,

+    0b0110100,

+    7,

+    0,

+    0,

+    {NULL},

 };

 

 

@@ -66,41 +59,30 @@ static I2CSlaveConfig max1236 = {
  * how to initialize ADC.

  */

 void init_max1236(void){

-  /* lock bus */

-  i2cAcquireBus(&I2CD2);

-

-  /* this data we must send to IC to setup ADC settings */

-  max1236.txbufhead = 0;

+  /* this data we must send via IC to setup ADC */

+  max1236.rxbytes = 0;

   max1236.txbytes = 2; // total 2 bytes to be sent

   max1236.txbuf[0] = 0b10000011; // config register content. Consult datasheet

   max1236.txbuf[1] = 0b00000111; // config register content. Consult datasheet

 

+

   // transmit out 2 bytes

+  i2cAcquireBus(&I2CD2);

   i2cMasterTransmit(&I2CD2, &max1236);

-  while(I2CD2.id_state != I2C_READY) // wait

-      chThdSleepMilliseconds(1);

-

+  while(I2CD2.id_state != I2C_READY){

+    chThdSleepMilliseconds(1);

+  }

   /* now add pointer to callback function */

   max1236.id_callback = i2c_max1236_cb;

-

-  /*clear transmitting structures */

-  max1236.txbytes = 0;

-  max1236.txbufhead = 0;

-

-  /* unlock bus */

   i2cReleaseBus(&I2CD2);

 }

 

 

 /* Now simply read 8 bytes to get all 4 ADC channels */

 void read_max1236(void){

-  /* tune receive buffer */

-  max1236.rxbufhead = 0;

+  max1236.txbytes = 0;

   max1236.rxbytes = 8;

-

-  /* lock bus */

   i2cAcquireBus(&I2CD2);

-

-  /* start reading */

   i2cMasterReceive(&I2CD2, &max1236);

+  i2cReleaseBus(&I2CD2);

 }

diff --git a/testhal/STM32/I2C/mcuconf.h b/testhal/STM32/I2C/mcuconf.h
index 92f8e17d8..465de58b8 100644
--- a/testhal/STM32/I2C/mcuconf.h
+++ b/testhal/STM32/I2C/mcuconf.h
@@ -59,24 +59,53 @@
 #define STM32_CAN_CAN1_IRQ_PRIORITY         11

 

 /*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  FALSE

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_USE_TIM3                  FALSE

+#define STM32_GPT_USE_TIM4                  FALSE

+#define STM32_GPT_USE_TIM5                  FALSE

+#define STM32_GPT_TIM1_IRQ_PRIORITY         7

+#define STM32_GPT_TIM2_IRQ_PRIORITY         7

+#define STM32_GPT_TIM3_IRQ_PRIORITY         7

+#define STM32_GPT_TIM4_IRQ_PRIORITY         7

+#define STM32_GPT_TIM5_IRQ_PRIORITY         7

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  FALSE

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_USE_TIM3                  FALSE

+#define STM32_ICU_USE_TIM4                  TRUE

+#define STM32_ICU_USE_TIM5                  FALSE

+#define STM32_ICU_TIM1_IRQ_PRIORITY         7

+#define STM32_ICU_TIM2_IRQ_PRIORITY         7

+#define STM32_ICU_TIM3_IRQ_PRIORITY         7

+#define STM32_ICU_TIM4_IRQ_PRIORITY         7

+#define STM32_ICU_TIM5_IRQ_PRIORITY         7

+

+/*

  * PWM driver system settings.

  */

+#define STM32_PWM_USE_ADVANCED              FALSE

 #define STM32_PWM_USE_TIM1                  FALSE

 #define STM32_PWM_USE_TIM2                  FALSE

 #define STM32_PWM_USE_TIM3                  TRUE

 #define STM32_PWM_USE_TIM4                  TRUE

 #define STM32_PWM_USE_TIM5                  FALSE

-#define STM32_PWM_TIM1_IRQ_PRIORITY         7

-#define STM32_PWM_TIM2_IRQ_PRIORITY         7

-#define STM32_PWM_TIM3_IRQ_PRIORITY         7

-#define STM32_PWM_TIM4_IRQ_PRIORITY         7

-#define STM32_PWM_TIM5_IRQ_PRIORITY         7

+#define STM32_PWM_TIM1_IRQ_PRIORITY         2

+#define STM32_PWM_TIM2_IRQ_PRIORITY         2

+#define STM32_PWM_TIM3_IRQ_PRIORITY         2

+#define STM32_PWM_TIM4_IRQ_PRIORITY         2

+#define STM32_PWM_TIM5_IRQ_PRIORITY         2

 

 /*

  * SERIAL driver system settings.

  */

-#define STM32_SERIAL_USE_USART1             FALSE

-#define STM32_SERIAL_USE_USART2             FALSE

+#define STM32_SERIAL_USE_USART1             TRUE

+#define STM32_SERIAL_USE_USART2             TRUE

 #define STM32_SERIAL_USE_USART3             FALSE

 #define STM32_SERIAL_USE_UART4              FALSE

 #define STM32_SERIAL_USE_UART5              FALSE

@@ -89,24 +118,22 @@
 /*

  * SPI driver system settings.

  */

-#define STM32_SPI_USE_SPI1                  FALSE

-#define STM32_SPI_USE_SPI2                  FALSE

+#define STM32_SPI_USE_SPI1                  TRUE

+#define STM32_SPI_USE_SPI2                  TRUE

 #define STM32_SPI_USE_SPI3                  FALSE

-#define STM32_SPI_SPI1_DMA_PRIORITY         2

-#define STM32_SPI_SPI2_DMA_PRIORITY         2

-#define STM32_SPI_SPI3_DMA_PRIORITY         2

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI3_DMA_PRIORITY         1

 #define STM32_SPI_SPI1_IRQ_PRIORITY         10

 #define STM32_SPI_SPI2_IRQ_PRIORITY         10

 #define STM32_SPI_SPI3_IRQ_PRIORITY         10

-#define STM32_SPI_SPI1_DMA_ERROR_HOOK()     chSysHalt()

-#define STM32_SPI_SPI2_DMA_ERROR_HOOK()     chSysHalt()

-#define STM32_SPI_SPI3_DMA_ERROR_HOOK()     chSysHalt()

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()

 

 /*

  * UART driver system settings.

  */

-#define STM32_UART_USE_USART1               TRUE

-#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART1               FALSE // RF link

+#define STM32_UART_USE_USART2               FALSE //GPS

 #define STM32_UART_USE_USART3               FALSE

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

@@ -114,18 +141,35 @@
 #define STM32_UART_USART1_DMA_PRIORITY      0

 #define STM32_UART_USART2_DMA_PRIORITY      0

 #define STM32_UART_USART3_DMA_PRIORITY      0

-#define STM32_UART_USART1_DMA_ERROR_HOOK()  chSysHalt()

-#define STM32_UART_USART2_DMA_ERROR_HOOK()  chSysHalt()

-#define STM32_UART_USART3_DMA_ERROR_HOOK()  chSysHalt()

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

 

 /*

  * I2C driver system settings.

  */

 #define STM32_I2C_USE_I2C1                  TRUE

 #define STM32_I2C_USE_I2C2                  TRUE

-#define STM32_I2C_I2C1_IRQ_PRIORITY         11

-#define STM32_I2C_I2C2_IRQ_PRIORITY         11

+#define STM32_I2C_I2C1_IRQ_PRIORITY         10

+#define STM32_I2C_I2C2_IRQ_PRIORITY         10

 #define STM32_I2C_I2C1_DMA_PRIORITY         4

 #define STM32_I2C_I2C2_DMA_PRIORITY         4

 #define STM32_I2C_I2C1_DMA_ERROR_HOOK()     chSysHalt()

 #define STM32_I2C_I2C2_DMA_ERROR_HOOK()     chSysHalt()

+

+/*

+ * EXTI system settings.

+ */

+#define STM32_EXTI0_PRIORITY        5

+#define STM32_EXTI1_PRIORITY        5

+#define STM32_EXTI2_PRIORITY        5

+#define STM32_EXTI3_PRIORITY        5

+#define STM32_EXTI4_PRIORITY        5

+#define STM32_EXTI9_5_PRIORITY      5

+#define STM32_EXTI15_10_PRIORITY    5

+

+/*

+ * USB driver system settings.

+ */

+#define STM32_USB_USE_USB1                  TRUE

+#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE

+#define STM32_USB_USB1_HP_IRQ_PRIORITY      6

+#define STM32_USB_USB1_LP_IRQ_PRIORITY      14

diff --git a/testhal/STM32/I2C/tmp75.c b/testhal/STM32/I2C/tmp75.c
index 4d9923881..cc1b2ca7f 100644
--- a/testhal/STM32/I2C/tmp75.c
+++ b/testhal/STM32/I2C/tmp75.c
@@ -15,6 +15,8 @@
 // input buffer

 static i2cblock_t tmp75_rx_data[TMP75_RX_DEPTH];

 static i2cblock_t tmp75_tx_data[TMP75_TX_DEPTH];

+// temperature value

+static int16_t temperature = 0;

 

 // Simple error trap

 static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){

@@ -26,47 +28,34 @@ static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
 

 /* This callback raise up when transfer finished */

 static void i2c_tmp75_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){

-  int16_t temperature = 0;

-

-  /* Manually send stop signal to the bus. This is important! */

-  i2cMasterStop(i2cp);

-  /* unlock bus */

-  i2cReleaseBus(&I2CD2);

-

+  (void)*i2cp;

   /* store temperature value */

   temperature = (i2cscfg->rxbuf[0] << 8) + i2cscfg->rxbuf[1];

-

 }

 

 // Fill TMP75 config.

 static I2CSlaveConfig tmp75 = {

     i2c_tmp75_cb,

     i2c_tmp75_error_cb,

-    tmp75_rx_data,

-    TMP75_RX_DEPTH,

     0,

     0,

+    tmp75_rx_data,

     tmp75_tx_data,

-    TMP75_TX_DEPTH,

+    0b1001000,

+    7,

     0,

     0,

-    0b1001000,

-    FALSE,

+    {NULL},

 };

 

 /* This is main function. */

 void request_temperature(void){

-  tmp75.txbytes = 0;  // set to zero just to be safe

-

-  /* tune receiving buffer */

-  tmp75.rxbufhead = 0;// point to beginig of buffer

-  tmp75.rxbytes = 2;  // we need read 2 bytes

+  tmp75.txbytes = 0;  // set to zero because we need only reading

+  tmp75.rxbytes = 2;  // we need to read 2 bytes

 

-  /* get exclusive access to the bus */

   i2cAcquireBus(&I2CD2);

-

-  /* start receiving process in background and return */

   i2cMasterReceive(&I2CD2, &tmp75);

+  i2cReleaseBus(&I2CD2);

 }