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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-13 09:24:17 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-13 09:24:17 +0000 |
| commit | 3cc94a962116a7529d8555bbf774cc5e31f9f1a7 (patch) | |
| tree | 0ca6758f96448b2981ccf6ec593d602ee8c1cf4d | |
| parent | 61650db8e547e811190b13338f22f69f2e3fa1dc (diff) | |
| download | ChibiOS-3cc94a962116a7529d8555bbf774cc5e31f9f1a7.tar.gz ChibiOS-3cc94a962116a7529d8555bbf774cc5e31f9f1a7.tar.bz2 ChibiOS-3cc94a962116a7529d8555bbf774cc5e31f9f1a7.zip | |
Fixed bug 3575297.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4750 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/STM32F2xx/adc_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/adc_lld.c | 6 | ||||
| -rw-r--r-- | readme.txt | 2 |
3 files changed, 10 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c index fd91ba76a..6d889d4c5 100644 --- a/os/hal/platforms/STM32F2xx/adc_lld.c +++ b/os/hal/platforms/STM32F2xx/adc_lld.c @@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { */
void adc_lld_init(void) {
- ADC->CCR = STM32_ADC_ADCPRE;
-
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) { }
#endif /* STM32_ADC_USE_ADC3 */
+ /* This is a common register but apparently it requires that at least one
+ of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+ ADC->CCR = STM32_ADC_ADCPRE << 16;
+
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index bf0788dea..9f447f9a6 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { */
void adc_lld_init(void) {
- ADC->CCR = STM32_ADC_ADCPRE;
-
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
@@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) { }
#endif /* STM32_ADC_USE_ADC3 */
+ /* This is a common register but apparently it requires that at least one
+ of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+ ADC->CCR = STM32_ADC_ADCPRE << 16;
+
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR1 = 0;
diff --git a/readme.txt b/readme.txt index 37aaa7d02..f1a7289da 100644 --- a/readme.txt +++ b/readme.txt @@ -83,6 +83,8 @@ *****************************************************************************
*** 2.5.1 ***
+- FIX: Fixed STM32F4 ADC prescaler incorrectly initialized (bug 3575297)
+ (backported to 2.4.3).
- FIX: Fixed RCC_APB2ENR_IOPEEN undeclared on STM32F10X_LD_VL devices (bug
3575098)(backported to 2.4.3).
- FIX: Fixed misplaced declarations in lwip_bindings sys_arch.c (bug 3571053)
|