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authorGiovanni Di Sirio <gdisirio@gmail.com>2015-08-26 12:42:52 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-08-26 12:42:52 +0000
commit3a5c3788fa9bc4b900926daceb86ad525fb28df4 (patch)
treeadb236285dd3d339a28ec5c37f6b73226f3350ff
parent95229524a642ae2cfe7f19b79a82f3e8a274b3a3 (diff)
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Added cache handling example for F7 ADC and SPI demos.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8243 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--testhal/STM32/STM32F7xx/GPT-ADC/main.c9
-rw-r--r--testhal/STM32/STM32F7xx/SPI/main.c91
2 files changed, 78 insertions, 22 deletions
diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/main.c b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
index 1f65197c3..4e1b27520 100644
--- a/testhal/STM32/STM32F7xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32F7xx/GPT-ADC/main.c
@@ -38,6 +38,12 @@ static const GPTConfig gpt4cfg1 = {
#define ADC_GRP1_NUM_CHANNELS 2
#define ADC_GRP1_BUF_DEPTH 64
+/* Note, the buffer is aligned to a 32 bytes boundary because limitations
+ imposed by the data cache. Note, this is GNU specific, it must be
+ handled differently for other compilers.*/
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
@@ -46,7 +52,8 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
- (void)adcp;
+ /* DMA buffer invalidation because data cache.*/
+ dmaBufferInvalidate(buffer, buffer + (n * adcp->grpp->num_channels));
/* Updating counters.*/
if (samples1 == buffer) {
diff --git a/testhal/STM32/STM32F7xx/SPI/main.c b/testhal/STM32/STM32F7xx/SPI/main.c
index 996b3c9b7..cd7b3ed07 100644
--- a/testhal/STM32/STM32F7xx/SPI/main.c
+++ b/testhal/STM32/STM32F7xx/SPI/main.c
@@ -14,6 +14,8 @@
limitations under the License.
*/
+#include <string.h>
+
#include "ch.h"
#include "hal.h"
@@ -21,6 +23,8 @@
/* SPI driver related. */
/*===========================================================================*/
+#define SPI_LOOPBACK
+
/*
* Maximum speed SPI configuration (27MHz, CPHA=0, CPOL=0, MSb first).
*/
@@ -45,9 +49,21 @@ static const SPIConfig ls_spicfg = {
/*
* SPI TX and RX buffers.
+ * Note, the buffer are aligned to a 32 bytes boundary because limitations
+ * imposed by the data cache. Note, this is GNU specific, it must be
+ * handled differently for other compilers.
*/
-static uint8_t txbuf[512];
-static uint8_t rxbuf[512];
+#define SPI_BUFFERS_SIZE 128U
+
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+static uint8_t txbuf[SPI_BUFFERS_SIZE];
+
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+static uint8_t rxbuf[SPI_BUFFERS_SIZE];
/*===========================================================================*/
/* Application code. */
@@ -62,14 +78,32 @@ static THD_FUNCTION(spi_thread_1, p) {
(void)p;
chRegSetThreadName("SPI thread 1");
while (true) {
- spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */
- palSetPad(GPIOI, GPIOI_ARD_D13); /* LED ON. */
- spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */
- spiSelect(&SPID2); /* Slave Select assertion. */
- spiExchange(&SPID2, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
- spiUnselect(&SPID2); /* Slave Select de-assertion. */
- spiReleaseBus(&SPID2); /* Ownership release. */
+ unsigned i;
+
+ /* Bush acquisition and SPI reprogramming.*/
+ spiAcquireBus(&SPID2);
+ spiStart(&SPID2, &hs_spicfg);
+
+ /* Preparing data buffer and flushing cache.*/
+ for (i = 0; i < SPI_BUFFERS_SIZE; i++)
+ txbuf[i] = (uint8_t)i;
+ dmaBufferFlush(txbuf, txbuf + SPI_BUFFERS_SIZE);
+
+ /* Slave selection and data exchange.*/
+ spiSelect(&SPID2);
+ spiExchange(&SPID2, SPI_BUFFERS_SIZE, txbuf, rxbuf);
+ spiUnselect(&SPID2);
+
+#if defined(SPI_LOOPBACK)
+ /* Invalidating cache over the buffer then checking the
+ loopback result.*/
+ dmaBufferInvalidate(rxbuf, rxbuf + SPI_BUFFERS_SIZE);
+ if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
+ chSysHalt("loopback failure");
+#endif
+
+ /* Releasing the bus.*/
+ spiReleaseBus(&SPID2);
}
}
@@ -82,14 +116,32 @@ static THD_FUNCTION(spi_thread_2, p) {
(void)p;
chRegSetThreadName("SPI thread 2");
while (true) {
- spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */
- palClearPad(GPIOI, GPIOI_ARD_D13); /* LED OFF. */
- spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */
- spiSelect(&SPID2); /* Slave Select assertion. */
- spiExchange(&SPID2, 512,
- txbuf, rxbuf); /* Atomic transfer operations. */
- spiUnselect(&SPID2); /* Slave Select de-assertion. */
- spiReleaseBus(&SPID2); /* Ownership release. */
+ unsigned i;
+
+ /* Bush acquisition and SPI reprogramming.*/
+ spiAcquireBus(&SPID2);
+ spiStart(&SPID2, &ls_spicfg);
+
+ /* Preparing data buffer and flushing cache.*/
+ for (i = 0; i < SPI_BUFFERS_SIZE; i++)
+ txbuf[i] = (uint8_t)(128U + i);
+ dmaBufferFlush(txbuf, txbuf + SPI_BUFFERS_SIZE);
+
+ /* Slave selection and data exchange.*/
+ spiSelect(&SPID2);
+ spiExchange(&SPID2, SPI_BUFFERS_SIZE, txbuf, rxbuf);
+ spiUnselect(&SPID2);
+
+#if defined(SPI_LOOPBACK)
+ /* Invalidating cache over the buffer then checking the
+ loopback result.*/
+ dmaBufferInvalidate(rxbuf, rxbuf + SPI_BUFFERS_SIZE);
+ if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
+ chSysHalt("loopback failure");
+#endif
+
+ /* Releasing the bus.*/
+ spiReleaseBus(&SPID2);
}
}
@@ -97,7 +149,6 @@ static THD_FUNCTION(spi_thread_2, p) {
* Application entry point.
*/
int main(void) {
- unsigned i;
/*
* System initializations.
@@ -136,8 +187,6 @@ int main(void) {
/*
* Prepare transmit pattern.
*/
- for (i = 0; i < sizeof(txbuf); i++)
- txbuf[i] = (uint8_t)i;
/*
* Starting the transmitter and receiver threads.