git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@69 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 202 insertions, 0 deletions

diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile
index fb9dba78b..310124c2a 100644
--- a/demos/ARM7-LPC214x-GCC/Makefile
+++ b/demos/ARM7-LPC214x-GCC/Makefile
@@ -64,6 +64,7 @@ UADEFS =
 # List ARM-mode C source files here

 ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \

        ../../ports/ARM7-LPC214x/GCC/vic.c  ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c  \

+       ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c  \

        ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \

        ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \

        ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c

diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c
index e0de6fc02..beee2a7ae 100644
--- a/demos/ARM7-LPC214x-GCC/chcore.c
+++ b/demos/ARM7-LPC214x-GCC/chcore.c
@@ -22,6 +22,7 @@
 #include "lpc214x.h"

 #include "vic.h"

 #include "lpc214x_serial.h"

+#include "lpc214x_ssp.h"

 

 #include "buzzer.h"

 

@@ -117,6 +118,7 @@ void hwinit(void) {
   SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);

   SetVICVector(UART0IrqHandler, 1, SOURCE_UART0);

   SetVICVector(UART1IrqHandler, 2, SOURCE_UART1);

+  SetVICVector(SSPIrqHandler, 3, SOURCE_SPI1);

 

   /*

    * System Timer initialization, 1ms intervals.

@@ -133,6 +135,7 @@ void hwinit(void) {
    * Other subsystems.

    */

   InitSerial();

+  InitSSP();

   InitBuzzer();

 }

 

diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s
index f734eebba..97a38fdfe 100644
--- a/demos/ARM7-LPC214x-GCC/chcore2.s
+++ b/demos/ARM7-LPC214x-GCC/chcore2.s
@@ -155,6 +155,16 @@ UART1IrqHandler:
         bl      UART1Irq

         b       IrqCommon

 

+.globl SSPIrqHandler

+SSPIrqHandler:

+        sub     lr, lr, #4

+        stmfd   sp!, {r0-r3, r12, lr}

+        mrs     r0, SPSR                        // Workaround for ARM7TDMI+VIC

+        tst     r0, #I_BIT                      // spurious interrupts.

+        ldmnefd sp!, {r0-r3, r12, pc}^

+        bl      SSPIrq

+        b       IrqCommon

+

 /*

  * Common exit point for all IRQ routines, it performs the rescheduling if

  * required.

diff --git a/ports/ARM7-LPC214x/GCC/lpc214x.h b/ports/ARM7-LPC214x/GCC/lpc214x.h
index 74bbce2c3..213409cb9 100644
--- a/ports/ARM7-LPC214x/GCC/lpc214x.h
+++ b/ports/ARM7-LPC214x/GCC/lpc214x.h
@@ -338,6 +338,81 @@ typedef struct {
 #define TER_ENABLE      0x80

 

 /*

+ * SSP.

+ */

+typedef struct {

+  IOREG32       SSP_CR0;

+  IOREG32       SSP_CR1;

+  IOREG32       SSP_DR;

+  IOREG32       SSP_SR;

+  IOREG32       SSP_CPSR;

+  IOREG32       SSP_IMSC;

+  IOREG32       SSP_RIS;

+  IOREG32       SSP_MIS;

+  IOREG32       SSP_ICR;

+} SSP;

+

+#define SSPBase                 ((SSP *)0xE0068000)

+#define SSPCR0                  (SSPBase->SSP_CR0)

+#define SSPCR1                  (SSPBase->SSP_CR1)

+#define SSPDR                   (SSPBase->SSP_DR)

+#define SSPSR                   (SSPBase->SSP_SR)

+#define SSPCPSR                 (SSPBase->SSP_CPSR)

+#define SSPIMSC                 (SSPBase->SSP_IMSC)

+#define SSPRIS                  (SSPBase->SSP_RIS)

+#define SSPMIS                  (SSPBase->SSP_MIS)

+#define SSPICR                  (SSPBase->SSP_ICR)

+

+#define CR0_DSS4BIT             3

+#define CR0_DSS5BIT             4

+#define CR0_DSS6BIT             5

+#define CR0_DSS7BIT             6

+#define CR0_DSS8BIT             7

+#define CR0_DSS9BIT             8

+#define CR0_DSS10BIT            9

+#define CR0_DSS11BIT            0xA

+#define CR0_DSS12BIT            0xB

+#define CR0_DSS13BIT            0xC

+#define CR0_DSS14BIT            0xD

+#define CR0_DSS15BIT            0xE

+#define CR0_DSS16BIT            0xF

+#define CR0_FRFSPI              0

+#define CR0_FRFSSI              0x10

+#define CR0_FRFMW               0x20

+#define CR0_CPOL                0x40

+#define CR0_CPHA                0x80

+#define CR0_CLOCKRATE(n)        ((n) << 8)

+

+#define CR1_LBM                 1

+#define CR1_SSE                 2

+#define CR1_MS                  4

+#define CR1_SOD                 8

+

+#define SR_TFE                  1

+#define SR_TNF                  2

+#define SR_RNE                  4

+#define SR_RFF                  8

+#define SR_BSY                  0x10

+

+#define IMSC_ROR                1

+#define IMSC_RT                 2

+#define IMSC_RX                 4

+#define IMSC_TX                 8

+

+#define RIS_ROR                1

+#define RIS_RT                 2

+#define RIS_RX                 4

+#define RIS_TX                 8

+

+#define MIS_ROR                1

+#define MIS_RT                 2

+#define MIS_RX                 4

+#define MIS_TX                 8

+

+#define ICR_ROR                1

+#define ICR_RT                 2

+

+/*

  * Timers/Counters.

  */

 typedef struct {

diff --git a/ports/ARM7-LPC214x/GCC/lpc214x_ssp.c b/ports/ARM7-LPC214x/GCC/lpc214x_ssp.c
new file mode 100644
index 000000000..4168b6157
--- /dev/null
+++ b/ports/ARM7-LPC214x/GCC/lpc214x_ssp.c
@@ -0,0 +1,78 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#include <ch.h>

+

+#include "lpc214x.h"

+#include "lpc214x_ssp.h"

+

+static BYTE8 *ip, *op;

+static t_size icnt, ocnt;

+static t_sspnotify callback;

+

+void SSPIrq(void) {

+}

+

+/*

+ * Starts an asynchronous SSP transfer.

+ * @param in pointer to the incoming data buffer, if this parameter is set to

+ *           \p NULL then the incoming data is discarded.

+ * @param out pointer to the outgoing data buffer, if this parameter is set to

+ *           \p NULL then 0xFF bytes will be output.

+ * @param n the number of bytes to be transferred

+ * @param fn callback function invoked when the operation is done

+ * @return \p SSP_OK if the trasfer is started else \p SSP_RUNNING if a

+ *         an operation was already started

+ */

+t_msg sspRWI(BYTE8 *in, BYTE8 *out, t_size n, t_sspnotify fn) {

+

+  if (callback)

+    return SSP_RUNNING;

+

+  callback = fn, ip = in, op = out, icnt = ocnt = n;

+  SSPIMSC = IMSC_ROR | IMSC_RT | IMSC_RX | IMSC_TX;

+  return SSP_OK;

+}

+

+/*

+ * SSP setup, must be invoked with interrupts disabled.

+ * Do not invoke while an operation is in progress.

+ */

+void SetSSPI(int cpsr, int cr0, int cr1) {

+  SSP *ssp = SSPBase;

+

+  ssp->SSP_CR1 = cr1 & ~CR1_SSE;

+  ssp->SSP_CR0 = cr0;

+  ssp->SSP_CPSR = cpsr;

+  ssp->SSP_CR1 = cr1 | CR1_SSE;

+}

+

+/*

+ * SSP subsystem initialization.

+ */

+void InitSSP(void) {

+

+  /* Enables the SPI1 clock */

+  PCONP = (PCONP & PCALL) | PCSPI1;

+

+  /* Clock = PCLK / 2 */

+  SetSSPI(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0);

+

+  VICIntEnable = INTMASK(SOURCE_SPI1);

+}

diff --git a/ports/ARM7-LPC214x/GCC/lpc214x_ssp.h b/ports/ARM7-LPC214x/GCC/lpc214x_ssp.h
new file mode 100644
index 000000000..655a6b1e0
--- /dev/null
+++ b/ports/ARM7-LPC214x/GCC/lpc214x_ssp.h
@@ -0,0 +1,32 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#ifndef _LPC214x_SSP_H_

+#define _LPC214x_SSP_H_

+

+#define SSP_OK      RDY_OK

+#define SSP_RUNNING -3

+

+typedef void (*t_sspnotify)(void);

+

+void InitSSP(void);

+void SetSSPI(int cpsr, int cr0, int cr1);

+void SSPIrqHandler(void);

+

+#endif /* _LPC214x_SSP_H_*/

diff --git a/readme.txt b/readme.txt
index 4ca08701f..3336c8789 100644
--- a/readme.txt
+++ b/readme.txt
@@ -38,6 +38,9 @@ AVR-AT90CANx-GCC    - Port on AVR AT90CAN128, not complete yet.
 *** Releases                                                              ***

 *****************************************************************************

 

+*** 0.3.6 ***

+- Added SSP (SPI1) definitions to the lpc214x.h file.

+

 *** 0.3.5 ***

 - Space optimization in events code.

 - Changed the behavior of chEvtWaitTimeout() when the timeout parameter is