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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-07-13 20:41:26 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-07-13 20:41:26 +0000 |
| commit | 2bdd9885e282b8cf26642f4a4b73fc4e61da872c (patch) | |
| tree | a77a9a8ea3d6a365431a6509311ef0c0c19ec347 | |
| parent | 146118a1365dcfc7b9b1e2263dd3eb2e94d0fe27 (diff) | |
| download | ChibiOS-2bdd9885e282b8cf26642f4a4b73fc4e61da872c.tar.gz ChibiOS-2bdd9885e282b8cf26642f4a4b73fc4e61da872c.tar.bz2 ChibiOS-2bdd9885e282b8cf26642f4a4b73fc4e61da872c.zip | |
I2C. Code cleanups.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3159 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/STM32/i2c_lld.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index e261c825f..62a269dba 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -490,15 +490,18 @@ void i2c_lld_set_clock(I2CDriver *i2cp) { if (clock_speed <= 100000) { /* Configure clock_div in standard mode */ chDbgAssert(duty == STD_DUTY_CYCLE, - "i2c_lld_set_clock(), #1", "Invalid standard mode duty cycle"); + "i2c_lld_set_clock(), #1", + "Invalid standard mode duty cycle"); clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); /* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */ if (clock_div < 0x04) clock_div = 0x04; /* Test if CCR value is under 0x4, and set the minimum allowed value */ regCCR |= (clock_div & I2C_CCR_CCR); /* Set clock_div value for standard mode */ i2cp->id_i2c->TRISE = freq + 1; /* Set Maximum Rise Time for standard mode */ } else if(clock_speed <= 400000) { /* Configure clock_div in fast mode */ - chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9), - "i2c_lld_set_clock(), #2", "Invalid fast mode duty cycle"); + chDbgAssert((duty == FAST_DUTY_CYCLE_2) || + (duty == FAST_DUTY_CYCLE_16_9), + "i2c_lld_set_clock(), #2", + "Invalid fast mode duty cycle"); if(duty == FAST_DUTY_CYCLE_2) { clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); /* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */ } |