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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-12-11 08:54:40 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-12-11 08:54:40 +0000 |
| commit | 27b7c4ec048316bfc1ec82638ddc6ecb412fffe0 (patch) | |
| tree | e0b5192e18a71caf4ca4fb88ee98e2b12f1a729d | |
| parent | 6f0b15aba33406fb080b6dcee17367a4c2882401 (diff) | |
| download | ChibiOS-27b7c4ec048316bfc1ec82638ddc6ecb412fffe0.tar.gz ChibiOS-27b7c4ec048316bfc1ec82638ddc6ecb412fffe0.tar.bz2 ChibiOS-27b7c4ec048316bfc1ec82638ddc6ecb412fffe0.zip | |
Implemented CR on the STM32 ADC driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2467 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/STM32/adc_lld.c | 8 | ||||
| -rw-r--r-- | readme.txt | 4 | ||||
| -rw-r--r-- | testhal/STM32/ADC/main.c | 2 |
3 files changed, 9 insertions, 5 deletions
diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c index ae983e7bf..1a9069c59 100644 --- a/os/hal/platforms/STM32/adc_lld.c +++ b/os/hal/platforms/STM32/adc_lld.c @@ -203,16 +203,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { dmaChannelSetup(adcp->ad_dmachp, n, adcp->ad_samples, ccr);
/* ADC setup.*/
+ adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
+ adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
adcp->ad_adc->SMPR1 = grpp->acg_smpr1;
adcp->ad_adc->SMPR2 = grpp->acg_smpr2;
adcp->ad_adc->SQR1 = grpp->acg_sqr1;
adcp->ad_adc->SQR2 = grpp->acg_sqr2;
adcp->ad_adc->SQR3 = grpp->acg_sqr3;
- adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
- adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
- /* ADC start.*/
- adcp->ad_adc->CR2 |= ADC_CR2_SWSTART | ADC_CR2_EXTTRIG;
+ /* ADC start by writing ADC_CR2_ADON a second time.*/
+ adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
}
/**
diff --git a/readme.txt b/readme.txt index 07f437938..15fffdc91 100644 --- a/readme.txt +++ b/readme.txt @@ -68,6 +68,10 @@ - NEW: Now the STM32 CAN driver puts the lower half word of the ESR
register in the upper half word of the can status word for easier
debug.
+- CHANGE: Modified the start of the ADC in the STM32 ADC driver, now it is
+ no more required to specify ADC_CR2_EXTSEL_SWSTART in the CR2 register
+ configuration. Also reordered the start sequence in order to allows a
+ longer stabilization time for the ADC.
*** 2.1.5 ***
- FIX: Fixed references to non-existing SSP1 device in LPC13xx SPI device
diff --git a/testhal/STM32/ADC/main.c b/testhal/STM32/ADC/main.c index 478500afe..ee6975046 100644 --- a/testhal/STM32/ADC/main.c +++ b/testhal/STM32/ADC/main.c @@ -55,7 +55,7 @@ static const ADCConversionGroup adcgrpcfg = { ADC_GRP1_NUM_CHANNELS,
adccallback,
0,
- ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE | ADC_CR2_CONT,
+ ADC_CR2_TSVREFE | ADC_CR2_CONT,
0,
0,
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),
|