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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-03-06 14:26:19 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-03-06 14:26:19 +0000 |
| commit | 1eabe1e91173d56ccbd85092570b3d0bfb8346e9 (patch) | |
| tree | 536bde5a1c03105289802a20f22fcc73ae4ffa7c | |
| parent | 8d1dc1313cf3d1ce8f7793d037c1df0c0591dc8c (diff) | |
| download | ChibiOS-1eabe1e91173d56ccbd85092570b3d0bfb8346e9.tar.gz ChibiOS-1eabe1e91173d56ccbd85092570b3d0bfb8346e9.tar.bz2 ChibiOS-1eabe1e91173d56ccbd85092570b3d0bfb8346e9.zip | |
Fixed support for QUADSPI on F4xx.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10120 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 30 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 4 |
2 files changed, 32 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index 6f3e269e6..503cf1bae 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -714,6 +714,36 @@ /** @} */
/**
+ * @name QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Disables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
+/**
* @name SDIO peripheral specific RCC operations
* @{
*/
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 941deffd7..ef21d7136 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -595,8 +595,8 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
-#define STM32_QUADSPI1_HANDLER Vector1AC
-#define STM32_QUADSPI1_NUMBER 91
+#define STM32_QUADSPI1_HANDLER Vector1B0
+#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
|