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authorRocco Marco Guglielmi <roccomarco.guglielmi@live.com>2016-06-06 07:42:00 +0000
committerRocco Marco Guglielmi <roccomarco.guglielmi@live.com>2016-06-06 07:42:00 +0000
commit1a7543117ce07e130984f0d66fd738bd45bc1be8 (patch)
tree3ad55e3fd2f96a433b00cc6b9be9b514b93aa80a
parent38416ed55e952de9898c5269c7c6cea8821e2bc3 (diff)
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Improved STM32F469I-Discovery/mcuconf.h enabling SYSCLK up to 180 MHz when OTG is enabled
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9597 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h
index c687a343a..95e9e95de 100644
--- a/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h
+++ b/demos/STM32/RT-STM32F469I-DISCOVERY/mcuconf.h
@@ -45,7 +45,7 @@
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
-#define STM32_PLLN_VALUE 336
+#define STM32_PLLN_VALUE 360
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_PLLI2SN_VALUE 192
@@ -67,7 +67,7 @@
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_SAI1SEL STM32_SAI2SEL_PLLR
#define STM32_SAI2SEL STM32_SAI2SEL_PLLR
-#define STM32_CK48MSEL STM32_CK48MSEL_PLL
+#define STM32_CK48MSEL STM32_CK48MSEL_PLLSAI
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE