[KINETIS] Add basic K20 family support

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7135 35acf78f-673a-0410-8e92-d51de3d6d3f4

8 files changed, 1653 insertions, 0 deletions

diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c
new file mode 100644
index 000000000..b88849437
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/hal_lld.c
@@ -0,0 +1,142 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/hal_lld.c

+ * @brief   HAL Driver subsystem low level driver source template.

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level HAL driver initialization.

+ * @todo    Use a macro to define the system clock frequency.

+ *

+ * @notapi

+ */

+void hal_lld_init(void) {

+

+}

+

+/**

+ * @brief   MK20D5 clock initialization.

+ * @note    All the involved constants come from the file @p board.h.

+ * @note    This function is meant to be invoked early during the system

+ *          initialization, it is usually invoked from the file

+ *          @p board.c.

+ * @todo    This function needs to be more generic.

+ *

+ * @special

+ */

+void mk20d50_clock_init(void) {

+

+  /* Disable the watchdog */

+  WDOG->UNLOCK = 0xC520;

+  WDOG->UNLOCK = 0xD928;

+  WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;

+

+  SIM->SCGC5 |= SIM_SCGC5_PORTA |

+                SIM_SCGC5_PORTB |

+                SIM_SCGC5_PORTC |

+                SIM_SCGC5_PORTD |

+                SIM_SCGC5_PORTE;

+

+  /* EXTAL0 and XTAL0 */

+  PORTA->PCR[18] = 0;

+  PORTA->PCR[19] = 0;

+

+  /*

+   * Start in FEI mode

+   */

+

+  /* Disable capacitors for crystal */

+  OSC->CR = 0;

+

+  /* Enable OSC, 8-32 MHz range, low power mode */

+  MCG->C2 = MCG_C2_RANGE0(1) | MCG_C2_LOCRE0 | MCG_C2_EREFS0;

+

+  /* Switch to crystal as clock source, FLL input of 8 MHz / 256 = 31.25 KHz */

+  MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);

+

+  /* Wait for crystal oscillator to begin */

+  while (!(MCG->S & MCG_S_OSCINIT0));

+

+  /* Wait for the FLL to use the oscillator */

+  while (MCG->S & MCG_S_IREFST);

+

+  /* Wait for the MCGOUTCLK to use the oscillator */

+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));

+

+  /*

+   * Now in FBE mode

+   */

+

+  /* Config PLL input for 2 MHz (8 MHz crystal / 4) */

+  MCG->C5 = MCG_C5_PRDIV0(3);

+

+  /* Config PLL for 96 MHz output */

+  MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);

+

+  /* Wait for PLL to start using crystal as its input */

+  while (!(MCG->S & MCG_S_PLLST));

+

+  /* Wait for PLL to lock */

+  while (!(MCG->S & MCG_S_LOCK0));

+

+  /*

+   * Now in PBE mode

+   */

+

+  /* Switch to PLL as clock source */

+  MCG->C1 = MCG_C1_CLKS(0);

+

+  /* Wait for PLL clock to be used */

+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);

+

+  /*

+   * Now in PEE mode

+   */

+}

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.h b/os/hal/ports/KINETIS/K20x/hal_lld.h
new file mode 100644
index 000000000..b2939df0b
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/hal_lld.h
@@ -0,0 +1,268 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    KL2x/hal_lld.h

+ * @brief   Kinetis KL2x HAL subsystem low level driver header.

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#ifndef _HAL_LLD_H_

+#define _HAL_LLD_H_

+

+#include "mk20d5.h"

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Defines the support for realtime counters in the HAL.

+ */

+#define HAL_IMPLEMENTS_COUNTERS FALSE

+

+/**

+ * @name    Platform identification

+ * @{

+ */

+#define PLATFORM_NAME           "Kinetis"

+/** @} */

+

+/**

+ * @brief   Maximum system and core clock (f_SYS) frequency.

+ */

+#define KINETIS_SYSCLK_MAX      48000000

+

+/**

+ * @brief   Maximum bus clock (f_BUS) frequency.

+ */

+#define KINETIS_BUSCLK_MAX      24000000

+

+/**

+ * @name    Internal clock sources

+ * @{

+ */

+#define KINETIS_IRCLK_F         4000000     /**< Fast internal reference clock, factory trimmed. */

+#define KINETIS_IRCLK_S         32768       /**< Slow internal reference clock, factory trimmed. */

+/** @} */

+

+#define KINETIS_MCG_MODE_FEI    1    /**< FLL Engaged Internal. */

+#define KINETIS_MCG_MODE_FEE    2    /**< FLL Engaged External. */

+#define KINETIS_MCG_MODE_FBI    3    /**< FLL Bypassed Internal. */

+#define KINETIS_MCG_MODE_FBE    4    /**< FLL Bypassed External. */

+#define KINETIS_MCG_MODE_PEE    5    /**< PLL Engaged External. */

+#define KINETIS_MCG_MODE_PBE    6    /**< PLL Bypassed External. */

+#define KINETIS_MCG_MODE_BLPI   7    /**< Bypassed Low Power Internal. */

+#define KINETIS_MCG_MODE_BLPE   8    /**< Bypassed Low Power External. */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   Disables the MCG/system clock initialization in the HAL.

+ */

+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)

+#define KINETIS_NO_INIT             FALSE

+#endif

+

+/**

+ * @brief   MCG mode selection.

+ */

+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)

+#define KINETIS_MCG_MODE            KINETIS_MCG_MODE_PEE

+#endif

+

+/**

+ * @brief   Clock divider for core/system and bus/flash clocks (OUTDIV1).

+ * @note    The allowed range is 1...16.

+ * @note    The default value is calculated for a 48 MHz system clock

+ *          from a 96 MHz PLL output.

+ */

+#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)

+#define KINETIS_MCG_FLL_OUTDIV1     2

+#endif

+

+/**

+ * @brief   Additional clock divider bus/flash clocks (OUTDIV4).

+ * @note    The allowed range is 1...8.

+ * @note    This divider is on top of the OUTDIV1 divider.

+ * @note    The default value is calculated for 24 MHz bus/flash clocks

+ *          from a 96 MHz PLL output and 48 MHz core/system clock.

+ */

+#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)

+#define KINETIS_MCG_FLL_OUTDIV4     2

+#endif

+

+/**

+ * @brief   FLL DCO tuning enable for 32.768 kHz reference.

+ * @note    Set to 1 for fine-tuning DCO for maximum frequency with

+ *          a 32.768 kHz reference.

+ * @note    The default value is for a 32.768 kHz external crystal.

+ */

+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)

+#define KINETIS_MCG_FLL_DMX32       1

+#endif

+

+/**

+ * @brief   FLL DCO range selection.

+ * @note    The allowed range is 0...3.

+ * @note    The default value is calculated for 48 MHz FLL output

+ *          from a 32.768 kHz external crystal.

+ *          (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)

+ *

+ */

+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)

+#define KINETIS_MCG_FLL_DRS         2

+#endif

+

+/**

+ * @brief   MCU system/core clock frequency.

+ */

+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)

+#define KINETIS_SYSCLK_FREQUENCY    48000000UL

+#endif

+

+/**

+ * @brief   MCU bus/flash clock frequency.

+ */

+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)

+#define KINETIS_BUSCLK_FREQUENCY    (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)

+#endif

+

+/**

+ * @brief   UART0 clock frequency.

+ * @note    The default value is based on 96 MHz PLL/2 source.

+ *          If you use a different source, such as the FLL,

+ *          you must set this properly.

+ */

+#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)

+#define KINETIS_UART0_CLOCK_FREQ    KINETIS_SYSCLK_FREQUENCY

+#endif

+

+/**

+ * @brief   UART0 clock source.

+ * @note    The default value is to use PLL/2 or FLL source.

+ */

+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)

+#define KINETIS_UART0_CLOCK_SRC     1

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if !defined(KINETIS_SYSCLK_FREQUENCY)

+#error KINETIS_SYSCLK_FREQUENCY must be defined

+#endif

+

+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX

+#error KINETIS_SYSCLK_FREQUENCY out of range

+#endif

+

+#if !defined(KINETIS_BUSCLK_FREQUENCY)

+#error KINETIS_BUSCLK_FREQUENCY must be defined

+#endif

+

+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX

+#error KINETIS_BUSCLK_FREQUENCY out of range

+#endif

+

+#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \

+      KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)

+#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16

+#endif

+

+#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \

+      KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)

+#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8

+#endif

+

+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)

+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1

+#endif

+

+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)

+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Type representing a system clock frequency.

+ */

+typedef uint32_t halclock_t;

+

+/**

+ * @brief   Type of the realtime free counter value.

+ */

+typedef uint32_t halrtcnt_t;

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Returns the current value of the system free running counter.

+ * @note    This service is implemented by returning the content of the

+ *          DWT_CYCCNT register.

+ *

+ * @return              The value of the system free running counter of

+ *                      type halrtcnt_t.

+ *

+ * @notapi

+ */

+#define hal_lld_get_counter_value()         0

+

+/**

+ * @brief   Realtime counter frequency.

+ * @note    The DWT_CYCCNT register is incremented directly by the system

+ *          clock so this function returns STM32_HCLK.

+ *

+ * @return              The realtime counter frequency of type halclock_t.

+ *

+ * @notapi

+ */

+#define hal_lld_get_counter_frequency()     0

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#include "nvic.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void hal_lld_init(void);

+  void mk20d50_clock_init(void);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _HAL_LLD_H_ */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.c b/os/hal/ports/KINETIS/K20x/pal_lld.c
new file mode 100644
index 000000000..221ce7480
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/pal_lld.c
@@ -0,0 +1,240 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    MK20D5/pal_lld.c

+ * @brief   PAL subsystem low level driver.

+ *

+ * @addtogroup PAL

+ * @{

+ */

+

+#include "osal.h"

+#include "hal.h"

+

+#if HAL_USE_PAL || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/**

+ * @brief Reads a logical state from an I/O pad.

+ * @note The @ref PAL provides a default software implementation of this

+ * functionality, implement this function if can optimize it by using

+ * special hardware functionalities or special coding.

+ *

+ * @param[in] port port identifier

+ * @param[in] pad pad number within the port

+ * @return The logical state.

+ * @retval PAL_LOW low logical state.

+ * @retval PAL_HIGH high logical state.

+ *

+ * @notapi

+ */

+uint8_t _pal_lld_readpad(ioportid_t port,

+                         uint8_t pad) {

+

+  return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;

+}

+

+/**

+ * @brief Writes a logical state on an output pad.

+ * @note This function is not meant to be invoked directly by the

+ * application code.

+ * @note The @ref PAL provides a default software implementation of this

+ * functionality, implement this function if can optimize it by using

+ * special hardware functionalities or special coding.

+ *

+ * @param[in] port port identifier

+ * @param[in] pad pad number within the port

+ * @param[in] bit logical value, the value must be @p PAL_LOW or

+ * @p PAL_HIGH

+ *

+ * @notapi

+ */

+void _pal_lld_writepad(ioportid_t port,

+                       uint8_t pad,

+                       uint8_t bit) {

+

+  if (bit == PAL_HIGH)

+    port->PDOR |= ((uint32_t) 1 << pad);

+  else

+    port->PDOR &= ~((uint32_t) 1 << pad);

+}

+

+/**

+ * @brief   Pad mode setup.

+ * @details This function programs a pad with the specified mode.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ * @note    Programming an unknown or unsupported mode is silently ignored.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ * @param[in] mode      pad mode

+ *

+ * @notapi

+ */

+void _pal_lld_setpadmode(ioportid_t port,

+                         uint8_t pad,

+                         iomode_t mode) {

+

+  PORT_TypeDef *portcfg = NULL;

+

+  chDbgAssert(pad <= 31, "pal_lld_setpadmode() #1, invalid pad");

+

+  if (mode == PAL_MODE_OUTPUT_PUSHPULL)

+    port->PDDR |= ((uint32_t) 1 << pad);

+  else

+    port->PDDR &= ~((uint32_t) 1 << pad);

+

+  if (port == IOPORT1)

+    portcfg = PORTA;

+  else if (port == IOPORT2)

+    portcfg = PORTB;

+  else if (port == IOPORT3)

+    portcfg = PORTC;

+  else if (port == IOPORT4)

+    portcfg = PORTD;

+  else if (port == IOPORT5)

+    portcfg = PORTE;

+

+  chDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");

+

+  switch (mode) {

+  case PAL_MODE_RESET:

+  case PAL_MODE_INPUT:

+  case PAL_MODE_OUTPUT_PUSHPULL:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);

+    break;

+  case PAL_MODE_OUTPUT_OPENDRAIN:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |

+                        PORTx_PCRn_ODE;

+  case PAL_MODE_INPUT_PULLUP:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |

+                        PORTx_PCRn_PE |

+                        PORTx_PCRn_PS;

+      break;

+  case PAL_MODE_INPUT_PULLDOWN:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |

+                        PORTx_PCRn_PE;

+      break;

+  case PAL_MODE_UNCONNECTED:

+  case PAL_MODE_INPUT_ANALOG:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(0);

+    break;

+  case PAL_MODE_ALTERNATIVE_1:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);

+    break;

+  case PAL_MODE_ALTERNATIVE_2:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(2);

+    break;

+  case PAL_MODE_ALTERNATIVE_3:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(3);

+    break;

+  case PAL_MODE_ALTERNATIVE_4:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(4);

+    break;

+  case PAL_MODE_ALTERNATIVE_5:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(5);

+    break;

+  case PAL_MODE_ALTERNATIVE_6:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(6);

+    break;

+  case PAL_MODE_ALTERNATIVE_7:

+    portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(7);

+    break;

+  }

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Kinetis I/O ports configuration.

+ * @details Ports A-E clocks enabled.

+ *

+ * @param[in] config    the Kinetis ports configuration

+ *

+ * @notapi

+ */

+void _pal_lld_init(const PALConfig *config) {

+

+  int i, j;

+

+  /* Enable clocking on all Ports */

+  SIM->SCGC5 |= SIM_SCGC5_PORTA |

+                SIM_SCGC5_PORTB |

+                SIM_SCGC5_PORTC |

+                SIM_SCGC5_PORTD |

+                SIM_SCGC5_PORTE;

+

+  /* Initial PORT and GPIO setup */

+  for (i = 0; i < TOTAL_PORTS; i++) {

+    for (j = 0; j < PADS_PER_PORT; j++) {

+      pal_lld_setpadmode(config->ports[i].port,

+                         j,

+                         config->ports[i].pads[j]);

+    }

+  }

+}

+

+/**

+ * @brief   Pads mode setup.

+ * @details This function programs a pads group belonging to the same port

+ *          with the specified mode.

+ *

+ * @param[in] port      the port identifier

+ * @param[in] mask      the group mask

+ * @param[in] mode      the mode

+ *

+ * @notapi

+ */

+void _pal_lld_setgroupmode(ioportid_t port,

+                           ioportmask_t mask,

+                           iomode_t mode) {

+

+  int i;

+

+  (void)mask;

+

+  for (i = 0; i < PADS_PER_PORT; i++) {

+    pal_lld_setpadmode(port, i, mode);

+  }

+}

+

+#endif /* HAL_USE_PAL */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.h b/os/hal/ports/KINETIS/K20x/pal_lld.h
new file mode 100644
index 000000000..cb278c5a0
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/pal_lld.h
@@ -0,0 +1,372 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    MK20D5/pal_lld.h

+ * @brief   PAL subsystem low level driver header.

+ *

+ * @addtogroup PAL

+ * @{

+ */

+

+#ifndef _PAL_LLD_H_

+#define _PAL_LLD_H_

+

+#if HAL_USE_PAL || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Unsupported modes and specific modes                                      */

+/*===========================================================================*/

+

+#define PAL_MODE_ALTERNATIVE_1      10

+#define PAL_MODE_ALTERNATIVE_2      11

+#define PAL_MODE_ALTERNATIVE_3      12

+#define PAL_MODE_ALTERNATIVE_4      13

+#define PAL_MODE_ALTERNATIVE_5      14

+#define PAL_MODE_ALTERNATIVE_6      15

+#define PAL_MODE_ALTERNATIVE_7      16

+

+#define PIN_MUX_ALTERNATIVE(x)      PORTx_PCRn_MUX(x)

+

+/*===========================================================================*/

+/* I/O Ports Types and constants.                                            */

+/*===========================================================================*/

+

+#define TOTAL_PORTS                 5

+#define PADS_PER_PORT               32

+

+/**

+ * @brief   Width, in bits, of an I/O port.

+ */

+#define PAL_IOPORTS_WIDTH 32

+

+/**

+ * @brief   Whole port mask.

+ * @brief   This macro specifies all the valid bits into a port.

+ */

+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)

+

+/**

+ * @brief   Digital I/O port sized unsigned type.

+ */

+typedef uint32_t ioportmask_t;

+

+/**

+ * @brief   Digital I/O modes.

+ */

+typedef uint32_t iomode_t;

+

+/**

+ * @brief   Port Identifier.

+ * @details This type can be a scalar or some kind of pointer, do not make

+ *          any assumption about it, use the provided macros when populating

+ *          variables of this type.

+ */

+typedef GPIO_TypeDef *ioportid_t;

+

+/**

+ * @brief   Port Configuration.

+ * @details This structure stores the configuration parameters of all pads

+ *          belonging to a port.

+ */

+typedef struct {

+    ioportid_t      port;

+    iomode_t        pads[PADS_PER_PORT];

+} PortConfig;

+

+/**

+ * @brief   Generic I/O ports static initializer.

+ * @details An instance of this structure must be passed to @p palInit() at

+ *          system startup time in order to initialized the digital I/O

+ *          subsystem. This represents only the initial setup, specific pads

+ *          or whole ports can be reprogrammed at later time.

+ * @note    Implementations may extend this structure to contain more,

+ *          architecture dependent, fields.

+ */

+typedef struct {

+    PortConfig      ports[TOTAL_PORTS];

+} PALConfig;

+

+/*===========================================================================*/

+/* I/O Ports Identifiers.                                                    */

+/*===========================================================================*/

+

+/**

+ * @brief   GPIO port A identifier.

+ */

+#define IOPORT1          GPIOA

+

+/**

+ * @brief   GPIO port B identifier.

+ */

+#define IOPORT2          GPIOB

+

+/**

+ * @brief   GPIO port C identifier.

+ */

+#define IOPORT3          GPIOC

+

+/**

+ * @brief   GPIO port D identifier.

+ */

+#define IOPORT4          GPIOD

+

+/**

+ * @brief   GPIO port E identifier.

+ */

+#define IOPORT5          GPIOE

+

+/*===========================================================================*/

+/* Implementation, some of the following macros could be implemented as      */

+/* functions, if so please put them in pal_lld.c.                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level PAL subsystem initialization.

+ *

+ * @param[in] config    architecture-dependent ports configuration

+ *

+ * @notapi

+ */

+#define pal_lld_init(config) _pal_lld_init(config)

+

+/**

+ * @brief   Reads the physical I/O port states.

+ *

+ * @param[in] port      port identifier

+ * @return              The port bits.

+ *

+ * @notapi

+ */

+#define pal_lld_readport(port) (port)->PDIR

+

+/**

+ * @brief   Reads the output latch.

+ * @details The purpose of this function is to read back the latched output

+ *          value.

+ *

+ * @param[in] port      port identifier

+ * @return              The latched logical states.

+ *

+ * @notapi

+ */

+#define pal_lld_readlatch(port) (port)->PDOR

+

+/**

+ * @brief   Writes a bits mask on a I/O port.

+ *

+ * @param[in] port      port identifier

+ * @param[in] bits      bits to be written on the specified port

+ *

+ * @notapi

+ */

+#define pal_lld_writeport(port, bits) (port)->PDOR = (bits)

+

+/**

+ * @brief   Sets a bits mask on a I/O port.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] bits      bits to be ORed on the specified port

+ *

+ * @notapi

+ */

+#define pal_lld_setport(port, bits) (port)->PSOR |= (bits)

+

+/**

+ * @brief   Clears a bits mask on a I/O port.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] bits      bits to be cleared on the specified port

+ *

+ * @notapi

+ */

+#define pal_lld_clearport(port, bits) (port)->PCOR |= (bits)

+

+/**

+ * @brief   Toggles a bits mask on a I/O port.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] bits      bits to be toggled on the specified port

+ *

+ * @notapi

+ */

+#define pal_lld_toggleport(port, bits) (port)->PTOR |= (bits)

+

+/**

+ * @brief   Reads a group of bits.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] mask      group mask

+ * @param[in] offset    group bit offset within the port

+ * @return              The group logical states.

+ *

+ * @notapi

+ */

+#define pal_lld_readgroup(port, mask, offset) 0

+

+/**

+ * @brief   Writes a group of bits.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] mask      group mask

+ * @param[in] offset    group bit offset within the port

+ * @param[in] bits      bits to be written. Values exceeding the group width

+ *                      are masked.

+ *

+ * @notapi

+ */

+#define pal_lld_writegroup(port, mask, offset, bits) (void)bits

+

+/**

+ * @brief   Pads group mode setup.

+ * @details This function programs a pads group belonging to the same port

+ *          with the specified mode.

+ * @note    Programming an unknown or unsupported mode is silently ignored.

+ *

+ * @param[in] port      port identifier

+ * @param[in] mask      group mask

+ * @param[in] offset    group bit offset within the port

+ * @param[in] mode      group mode

+ *

+ * @notapi

+ */

+#define pal_lld_setgroupmode(port, mask, offset, mode)                      \

+  _pal_lld_setgroupmode(port, mask << offset, mode)

+

+/**

+ * @brief   Reads a logical state from an I/O pad.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ * @return              The logical state.

+ * @retval PAL_LOW      low logical state.

+ * @retval PAL_HIGH     high logical state.

+ *

+ * @notapi

+ */

+#define pal_lld_readpad(port, pad) _pal_lld_readpad(port, pad)

+

+/**

+ * @brief   Writes a logical state on an output pad.

+ * @note    This function is not meant to be invoked directly by the

+ *          application  code.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ * @param[in] bit       logical value, the value must be @p PAL_LOW or

+ *                      @p PAL_HIGH

+ *

+ * @notapi

+ */

+#define pal_lld_writepad(port, pad, bit) _pal_lld_writepad(port, pad, bit)

+

+/**

+ * @brief   Sets a pad logical state to @p PAL_HIGH.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ *

+ * @notapi

+ */

+#define pal_lld_setpad(port, pad) (port)->PSOR |= ((uint32_t) 1 << (pad))

+

+/**

+ * @brief   Clears a pad logical state to @p PAL_LOW.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ *

+ * @notapi

+ */

+#define pal_lld_clearpad(port, pad) (port)->PCOR |= ((uint32_t) 1 << (pad))

+

+/**

+ * @brief   Toggles a pad logical state.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ *

+ * @notapi

+ */

+#define pal_lld_togglepad(port, pad) (port)->PTOR |= ((uint32_t) 1 << (pad))

+

+/**

+ * @brief   Pad mode setup.

+ * @details This function programs a pad with the specified mode.

+ * @note    The @ref PAL provides a default software implementation of this

+ *          functionality, implement this function if can optimize it by using

+ *          special hardware functionalities or special coding.

+ * @note    Programming an unknown or unsupported mode is silently ignored.

+ *

+ * @param[in] port      port identifier

+ * @param[in] pad       pad number within the port

+ * @param[in] mode      pad mode

+ *

+ * @notapi

+ */

+#define pal_lld_setpadmode(port, pad, mode)                                 \

+    _pal_lld_setpadmode(port, pad, mode)

+

+#if !defined(__DOXYGEN__)

+extern const PALConfig pal_default_config;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void _pal_lld_init(const PALConfig *config);

+  void _pal_lld_setgroupmode(ioportid_t port,

+                             ioportmask_t mask,

+                             iomode_t mode);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_PAL */

+

+#endif /* _PAL_LLD_H_ */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/K20x/platform.dox b/os/hal/ports/KINETIS/K20x/platform.dox
new file mode 100644
index 000000000..50cc5cd8e
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/platform.dox
@@ -0,0 +1,365 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/* TODO Still need to edit this entire file */

+

+/**

+ * @defgroup MK20D5_DRIVERS MK20D5 Drivers

+ * @details This section describes all the supported drivers on the MK20D5

+ *          platform and the implementation details of the single drivers.

+ *

+ * @ingroup platforms

+ */

+

+/**

+ * @defgroup MK20D5_HAL MK20D5 Initialization Support

+ * @details The MK20D5 HAL support is responsible for system initialization.

+ *

+ * @section mk20d5_hal_1 Supported HW resources

+ * - PLL1.

+ * - PLL2.

+ * - RCC.

+ * - Flash.

+ * .

+ * @section mk20d5_hal_2 MK20D5 HAL driver implementation features

+ * - PLL startup and stabilization.

+ * - Clock tree initialization.

+ * - Clock source selection.

+ * - Flash wait states initialization based on the selected clock options.

+ * - SYSTICK initialization based on current clock and kernel required rate.

+ * - DMA support initialization.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_ADC MK20D5 ADC Support

+ * @details The MK20D5 ADC driver supports the ADC peripherals using DMA

+ *          channels for maximum performance.

+ *

+ * @section mk20d5_adc_1 Supported HW resources

+ * - ADC1.

+ * - ADC2.

+ * - ADC3.

+ * - DMA2.

+ * .

+ * @section mk20d5_adc_2 MK20D5 ADC driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Streaming conversion using DMA for maximum performance.

+ * - Programmable ADC interrupt priority level.

+ * - Programmable DMA bus priority for each DMA channel.

+ * - Programmable DMA interrupt priority for each DMA channel.

+ * - DMA and ADC errors detection.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_CAN MK20D5 CAN Support

+ * @details The MK20D5 CAN driver uses the CAN peripherals.

+ *

+ * @section mk20d5_can_1 Supported HW resources

+ * - bxCAN1.

+ * .

+ * @section mk20d5_can_2 MK20D5 CAN driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Support for bxCAN sleep mode.

+ * - Programmable bxCAN interrupts priority level.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_EXT MK20D5 EXT Support

+ * @details The MK20D5 EXT driver uses the EXTI peripheral.

+ *

+ * @section mk20d5_ext_1 Supported HW resources

+ * - EXTI.

+ * .

+ * @section mk20d5_ext_2 MK20D5 EXT driver implementation features

+ * - Each EXTI channel can be independently enabled and programmed.

+ * - Programmable EXTI interrupts priority level.

+ * - Capability to work as event sources (WFE) rather than interrupt sources.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_GPT MK20D5 GPT Support

+ * @details The MK20D5 GPT driver uses the TIMx peripherals.

+ *

+ * @section mk20d5_gpt_1 Supported HW resources

+ * - TIM1.

+ * - TIM2.

+ * - TIM3.

+ * - TIM4.

+ * - TIM5.

+ * - TIM8.

+ * .

+ * @section mk20d5_gpt_2 MK20D5 GPT driver implementation features

+ * - Each timer can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Programmable TIMx interrupts priority level.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_ICU MK20D5 ICU Support

+ * @details The MK20D5 ICU driver uses the TIMx peripherals.

+ *

+ * @section mk20d5_icu_1 Supported HW resources

+ * - TIM1.

+ * - TIM2.

+ * - TIM3.

+ * - TIM4.

+ * - TIM5.

+ * - TIM8.

+ * .

+ * @section mk20d5_icu_2 MK20D5 ICU driver implementation features

+ * - Each timer can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Programmable TIMx interrupts priority level.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_MAC MK20D5 MAC Support

+ * @details The MK20D5 MAC driver supports the ETH peripheral.

+ *

+ * @section mk20d5_mac_1 Supported HW resources

+ * - ETH.

+ * - PHY (external).

+ * .

+ * @section mk20d5_mac_2 MK20D5 MAC driver implementation features

+ * - Dedicated DMA operations.

+ * - Support for checksum off-loading.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_PAL MK20D5 PAL Support

+ * @details The MK20D5 PAL driver uses the GPIO peripherals.

+ *

+ * @section mk20d5_pal_1 Supported HW resources

+ * - GPIOA.

+ * - GPIOB.

+ * - GPIOC.

+ * - GPIOD.

+ * - GPIOE.

+ * - GPIOF.

+ * - GPIOG.

+ * - GPIOH.

+ * - GPIOI.

+ * .

+ * @section mk20d5_pal_2 MK20D5 PAL driver implementation features

+ * The PAL driver implementation fully supports the following hardware

+ * capabilities:

+ * - 16 bits wide ports.

+ * - Atomic set/reset functions.

+ * - Atomic set+reset function (atomic bus operations).

+ * - Output latched regardless of the pad setting.

+ * - Direct read of input pads regardless of the pad setting.

+ * .

+ * @section mk20d5_pal_3 Supported PAL setup modes

+ * The MK20D5 PAL driver supports the following I/O modes:

+ * - @p PAL_MODE_RESET.

+ * - @p PAL_MODE_UNCONNECTED.

+ * - @p PAL_MODE_INPUT.

+ * - @p PAL_MODE_INPUT_PULLUP.

+ * - @p PAL_MODE_INPUT_PULLDOWN.

+ * - @p PAL_MODE_INPUT_ANALOG.

+ * - @p PAL_MODE_OUTPUT_PUSHPULL.

+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.

+ * - @p PAL_MODE_ALTERNATE (non standard).

+ * .

+ * Any attempt to setup an invalid mode is ignored.

+ *

+ * @section mk20d5_pal_4 Suboptimal behavior

+ * The MK20D5 GPIO is less than optimal in several areas, the limitations

+ * should be taken in account while using the PAL driver:

+ * - Pad/port toggling operations are not atomic.

+ * - Pad/group mode setup is not atomic.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_PWM MK20D5 PWM Support

+ * @details The MK20D5 PWM driver uses the TIMx peripherals.

+ *

+ * @section mk20d5_pwm_1 Supported HW resources

+ * - TIM1.

+ * - TIM2.

+ * - TIM3.

+ * - TIM4.

+ * - TIM5.

+ * - TIM8.

+ * .

+ * @section mk20d5_pwm_2 MK20D5 PWM driver implementation features

+ * - Each timer can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Four independent PWM channels per timer.

+ * - Programmable TIMx interrupts priority level.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_SDC MK20D5 SDC Support

+ * @details The MK20D5 SDC driver uses the SDIO peripheral.

+ *

+ * @section mk20d5_sdc_1 Supported HW resources

+ * - SDIO.

+ * - DMA2.

+ * .

+ * @section mk20d5_sdc_2 MK20D5 SDC driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Programmable interrupt priority.

+ * - DMA is used for receiving and transmitting.

+ * - Programmable DMA bus priority for each DMA channel.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_SERIAL MK20D5 Serial Support

+ * @details The MK20D5 Serial driver uses the USART/UART peripherals in a

+ *          buffered, interrupt driven, implementation.

+ *

+ * @section mk20d5_serial_1 Supported HW resources

+ * The serial driver can support any of the following hardware resources:

+ * - USART1.

+ * - USART2.

+ * - USART3.

+ * - UART4.

+ * - UART5.

+ * - USART6.

+ * .

+ * @section mk20d5_serial_2 MK20D5 Serial driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Each UART/USART can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Fully interrupt driven.

+ * - Programmable priority levels for each UART/USART.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_SPI MK20D5 SPI Support

+ * @details The SPI driver supports the MK20D5 SPI peripherals using DMA

+ *          channels for maximum performance.

+ *

+ * @section mk20d5_spi_1 Supported HW resources

+ * - SPI1.

+ * - SPI2.

+ * - SPI3.

+ * - DMA1.

+ * - DMA2.

+ * .

+ * @section mk20d5_spi_2 MK20D5 SPI driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Each SPI can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Programmable interrupt priority levels for each SPI.

+ * - DMA is used for receiving and transmitting.

+ * - Programmable DMA bus priority for each DMA channel.

+ * - Programmable DMA interrupt priority for each DMA channel.

+ * - Programmable DMA error hook.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_UART MK20D5 UART Support

+ * @details The UART driver supports the MK20D5 USART peripherals using DMA

+ *          channels for maximum performance.

+ *

+ * @section mk20d5_uart_1 Supported HW resources

+ * The UART driver can support any of the following hardware resources:

+ * - USART1.

+ * - USART2.

+ * - USART3.

+ * - DMA1.

+ * - DMA2.

+ * .

+ * @section mk20d5_uart_2 MK20D5 UART driver implementation features

+ * - Clock stop for reduced power usage when the driver is in stop state.

+ * - Each UART/USART can be independently enabled and programmed. Unused

+ *   peripherals are left in low power mode.

+ * - Programmable interrupt priority levels for each UART/USART.

+ * - DMA is used for receiving and transmitting.

+ * - Programmable DMA bus priority for each DMA channel.

+ * - Programmable DMA interrupt priority for each DMA channel.

+ * - Programmable DMA error hook.

+ * .

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_PLATFORM_DRIVERS MK20D5 Platform Drivers

+ * @details Platform support drivers. Platform drivers do not implement HAL

+ *          standard driver templates, their role is to support platform

+ *          specific functionalities.

+ *

+ * @ingroup MK20D5_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_DMA MK20D5 DMA Support

+ * @details This DMA helper driver is used by the other drivers in order to

+ *          access the shared DMA resources in a consistent way.

+ *

+ * @section mk20d5_dma_1 Supported HW resources

+ * The DMA driver can support any of the following hardware resources:

+ * - DMA1.

+ * - DMA2.

+ * .

+ * @section mk20d5_dma_2 MK20D5 DMA driver implementation features

+ * - Exports helper functions/macros to the other drivers that share the

+ *   DMA resource.

+ * - Automatic DMA clock stop when not in use by any driver.

+ * - DMA streams and interrupt vectors sharing among multiple drivers.

+ * .

+ * @ingroup MK20D5_PLATFORM_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_ISR MK20D5 ISR Support

+ * @details This ISR helper driver is used by the other drivers in order to

+ *          map ISR names to physical vector names.

+ *

+ * @ingroup MK20D5_PLATFORM_DRIVERS

+ */

+

+/**

+ * @defgroup MK20D5_RCC MK20D5 RCC Support

+ * @details This RCC helper driver is used by the other drivers in order to

+ *          access the shared RCC resources in a consistent way.

+ *

+ * @section mk20d5_rcc_1 Supported HW resources

+ * - RCC.

+ * .

+ * @section mk20d5_rcc_2 MK20D5 RCC driver implementation features

+ * - Peripherals reset.

+ * - Peripherals clock enable.

+ * - Peripherals clock disable.

+ * .

+ * @ingroup MK20D5_PLATFORM_DRIVERS

+ */

diff --git a/os/hal/ports/KINETIS/K20x/platform.mk b/os/hal/ports/KINETIS/K20x/platform.mk
new file mode 100644
index 000000000..c556a0853
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/platform.mk
@@ -0,0 +1,12 @@
+# List of all platform files.

+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \

+              ${CHIBIOS}/os/hal/ports/KINETIS/K20x/hal_lld.c \

+              ${CHIBIOS}/os/hal/ports/KINETIS/K20x/pal_lld.c \

+              ${CHIBIOS}/os/hal/ports/KINETIS/K20x/st_lld.c

+

+# Required include directories

+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \

+              ${CHIBIOS}/os/hal/ports/KINETIS/K20x

+

+

+

diff --git a/os/hal/ports/KINETIS/K20x/st_lld.c b/os/hal/ports/KINETIS/K20x/st_lld.c
new file mode 100644
index 000000000..b0b731b99
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/st_lld.c
@@ -0,0 +1,98 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    KINETIS/KL2x/st_lld.c

+ * @brief   ST Driver subsystem low level driver code.

+ *

+ * @addtogroup ST

+ * @{

+ */

+

+#include "hal.h"

+

+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local types.                                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)

+/**

+ * @brief   System Timer vector.

+ * @details This interrupt is used for system tick in periodic mode.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(SysTick_Handler) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  osalSysLockFromISR();

+  osalOsTimerHandlerI();

+  osalSysUnlockFromISR();

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level ST driver initialization.

+ *

+ * @notapi

+ */

+void st_lld_init(void) {

+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

+  /* Periodic systick mode, the Cortex-Mx internal systick timer is used

+     in this mode.*/

+  SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;

+  SysTick->VAL = 0;

+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

+                  SysTick_CTRL_ENABLE_Msk |

+                  SysTick_CTRL_TICKINT_Msk;

+

+  /* IRQ enabled.*/

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

+}

+

+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */

+

+/** @} */

diff --git a/os/hal/ports/KINETIS/K20x/st_lld.h b/os/hal/ports/KINETIS/K20x/st_lld.h
new file mode 100644
index 000000000..9c548a343
--- /dev/null
+++ b/os/hal/ports/KINETIS/K20x/st_lld.h
@@ -0,0 +1,156 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    KINETIS/st_lld.h

+ * @brief   ST Driver subsystem low level driver header.

+ * @details This header is designed to be include-able without having to

+ *          include other files from the HAL.

+ *

+ * @addtogroup ST

+ * @{

+ */

+

+#ifndef _ST_LLD_H_

+#define _ST_LLD_H_

+

+#include "mcuconf.h"

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   SysTick timer IRQ priority.

+ */

+#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define KINETIS_ST_IRQ_PRIORITY               8

+#endif

+

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void st_lld_init(void);

+#ifdef __cplusplus

+}

+#endif

+

+/*===========================================================================*/

+/* Driver inline functions.                                                  */

+/*===========================================================================*/

+

+/**

+ * @brief   Returns the time counter value.

+ *

+ * @return              The counter value.

+ *

+ * @notapi

+ */

+static inline systime_t st_lld_get_counter(void) {

+

+  return (systime_t)0;

+}

+

+/**

+ * @brief   Starts the alarm.

+ * @note    Makes sure that no spurious alarms are triggered after

+ *          this call.

+ *

+ * @param[in] time      the time to be set for the first alarm

+ *

+ * @notapi

+ */

+static inline void st_lld_start_alarm(systime_t time) {

+

+  (void)time;

+}

+

+/**

+ * @brief   Stops the alarm interrupt.

+ *

+ * @notapi

+ */

+static inline void st_lld_stop_alarm(void) {

+

+}

+

+/**

+ * @brief   Sets the alarm time.

+ *

+ * @param[in] time      the time to be set for the next alarm

+ *

+ * @notapi

+ */

+static inline void st_lld_set_alarm(systime_t time) {

+

+  (void)time;

+}

+

+/**

+ * @brief   Returns the current alarm time.

+ *

+ * @return              The currently set alarm time.

+ *

+ * @notapi

+ */

+static inline systime_t st_lld_get_alarm(void) {

+

+  return (systime_t)0;

+}

+

+/**

+ * @brief   Determines if the alarm is active.

+ *

+ * @return              The alarm status.

+ * @retval false        if the alarm is not active.

+ * @retval true         is the alarm is active

+ *

+ * @notapi

+ */

+static inline bool st_lld_is_alarm_active(void) {

+

+  return false;

+}

+

+#endif /* _ST_LLD_H_ */

+

+/** @} */