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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-06-30 13:35:26 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-06-30 13:35:26 +0000 |
| commit | 077ee8eea7c6e07cdf47ed86acb9f4aa30f61969 (patch) | |
| tree | a0110009a5a40d00106f85edbd83c143979fedaf | |
| parent | 52da4b196e3b72bf18a1f9f443ec29f9f36eab97 (diff) | |
| download | ChibiOS-077ee8eea7c6e07cdf47ed86acb9f4aa30f61969.tar.gz ChibiOS-077ee8eea7c6e07cdf47ed86acb9f4aa30f61969.tar.bz2 ChibiOS-077ee8eea7c6e07cdf47ed86acb9f4aa30f61969.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12864 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h | 14 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h | 9 |
2 files changed, 11 insertions, 12 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h index 2f2146416..734e8c588 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h @@ -32,7 +32,7 @@ * Foundation line.
* - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx
* for High-performance STM32F4 devices of Access line.
- * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
+ * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
* STM32F479xx for High-performance STM32F4 devices of Advanced line.
* .
*
@@ -538,9 +538,8 @@ #define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
-#define STM32_CK48MSEL_PLLALT (1 << 27) /**< PLL48CLK source is PLLSAI
- or PLLI2S depending on
- device. */
+#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
+#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
@@ -784,7 +783,7 @@ * @brief PLLI2SN multiplier value.
* @note The allowed values are 192..432, except for
* STM32F446 where values are 50...432.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
@@ -794,7 +793,7 @@ /**
* @brief PLLI2SM divider value.
* @note The allowed values are 2..63.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
@@ -804,7 +803,7 @@ /**
* @brief PLLI2SR divider value.
* @note The allowed values are 2..7.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
@@ -1164,7 +1163,6 @@ #error "invalid VDD voltage specified"
#endif
-
#elif defined(STM32F401xx)
#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
#define STM32_0WS_THRESHOLD 30000000
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h index 52ff026c5..11b68fbb8 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h @@ -317,7 +317,7 @@ * @name RCC_DCKCFGR2 register bits definitions
* @{
*/
-#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */
+#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */
#define STM32_I2CFMP1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
#define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
#define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
@@ -325,6 +325,7 @@ #define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
#define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */
+#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
#define STM32_SDIOSEL_MASK (1 << 28) /**< SDIOSEL mask. */
#define STM32_SDIOSEL_PLL48CLK (0 << 28) /**< SDIO source is PLL48CLK. */
@@ -508,7 +509,7 @@ /**
* @brief PLLI2SM divider value.
* @note The allowed values are 2..63.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
@@ -519,7 +520,7 @@ * @brief PLLI2SN multiplier value.
* @note The allowed values are 192..432, except for
* STM32F446 where values are 50...432.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
@@ -529,7 +530,7 @@ /**
* @brief PLLI2SR divider value.
* @note The allowed values are 2..7.
- * @note The default value is calculated for a 96MHz I2S clock
+ * @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
|