blob: 1e770f17b89e6f3c33379feace533249adf864ee (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
#ifndef _BOARD_GPIO_H_
#define _BOARD_GPIO_H_
/* Generated by mx2board.py */
{% for d, v in defines %}
#define {{ d }} {{ v }}
{%- endfor %}
{% for p, v in ports %}
/* PORT {{p}} */
#define VAL_GPIO{{p}}_MODER ( \
{%- for i in v.MODER %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_OTYPER ( \
{%- for i in v.OTYPER %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_OSPEEDR ( \
{%- for i in v.OSPEEDR %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_PUPDR ( \
{%- for i in v.PUPDR %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_ODR ( \
{%- for i in v.ODR %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_AFRL ( \
{%- for i in v.AFRL %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_AFRH ( \
{%- for i in v.AFRH %}
{{ i }} | \
{%- endfor %}
0)
{% if ascr_lockr %}
#define VAL_GPIO{{p}}_ASCR ( \
{%- for i in v.ASCR %}
{{ i }} | \
{%- endfor %}
0)
#define VAL_GPIO{{p}}_LOCKR ( \
{%- for i in v.LOCKR %}
{{ i }} | \
{%- endfor %}
0)
{% endif %}
{% endfor %}
#endif
|
