aboutsummaryrefslogtreecommitdiffstats
path: root/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
diff options
context:
space:
mode:
Diffstat (limited to 'testhal/STM32/STM32F4xx/onewire/mcuconf_community.h')
-rw-r--r--testhal/STM32/STM32F4xx/onewire/mcuconf_community.h110
1 files changed, 110 insertions, 0 deletions
diff --git a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
index 7ca6e71..cf6a1ce 100644
--- a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
+++ b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h
@@ -43,3 +43,113 @@
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM FALSE
+
+/*
+ * TIMCAP driver system settings.
+ */
+#define STM32_TIMCAP_USE_TIM1 TRUE
+#define STM32_TIMCAP_USE_TIM2 FALSE
+#define STM32_TIMCAP_USE_TIM3 TRUE
+#define STM32_TIMCAP_USE_TIM4 TRUE
+#define STM32_TIMCAP_USE_TIM5 TRUE
+#define STM32_TIMCAP_USE_TIM8 TRUE
+#define STM32_TIMCAP_USE_TIM9 TRUE
+#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
+#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
+
+/*
+ * COMP driver system settings.
+ */
+#define STM32_COMP_USE_COMP1 TRUE
+#define STM32_COMP_USE_COMP2 TRUE
+#define STM32_COMP_USE_COMP3 TRUE
+#define STM32_COMP_USE_COMP4 TRUE
+#define STM32_COMP_USE_COMP5 TRUE
+#define STM32_COMP_USE_COMP6 TRUE
+#define STM32_COMP_USE_COMP7 TRUE
+
+#define STM32_COMP_USE_INTERRUPTS TRUE
+#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
+#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
+#define STM32_COMP_7_IRQ_PRIORITY 5
+
+#if STM32_COMP_USE_INTERRUPTS
+#define STM32_DISABLE_EXTI21_22_29_HANDLER
+#define STM32_DISABLE_EXTI30_32_HANDLER
+#define STM32_DISABLE_EXTI33_HANDLER
+#endif
+
+/*
+ * USBH driver system settings.
+ */
+#define STM32_OTG1_CHANNELS_NUMBER 8
+#define STM32_OTG2_CHANNELS_NUMBER 12
+
+#define STM32_USBH_USE_OTG1 1
+#define STM32_OTG1_RXFIFO_SIZE 1024
+#define STM32_OTG1_PTXFIFO_SIZE 128
+#define STM32_OTG1_NPTXFIFO_SIZE 128
+
+#define STM32_USBH_USE_OTG2 0
+#define STM32_OTG2_RXFIFO_SIZE 2048
+#define STM32_OTG2_PTXFIFO_SIZE 1024
+#define STM32_OTG2_NPTXFIFO_SIZE 1024
+
+#define STM32_USBH_MIN_QSPACE 4
+#define STM32_USBH_CHANNELS_NP 4
+
+/*
+ * CRC driver system settings.
+ */
+#define STM32_CRC_USE_CRC1 TRUE
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
+#define STM32_CRC_CRC1_DMA_PRIORITY 2
+#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
+
+#define CRCSW_USE_CRC1 FALSE
+#define CRCSW_CRC32_TABLE TRUE
+#define CRCSW_CRC16_TABLE TRUE
+#define CRCSW_PROGRAMMABLE TRUE
+
+/*
+ * EICU driver system settings.
+ */
+#define STM32_EICU_USE_TIM1 TRUE
+#define STM32_EICU_USE_TIM2 FALSE
+#define STM32_EICU_USE_TIM3 TRUE
+#define STM32_EICU_USE_TIM4 TRUE
+#define STM32_EICU_USE_TIM5 TRUE
+#define STM32_EICU_USE_TIM8 TRUE
+#define STM32_EICU_USE_TIM9 TRUE
+#define STM32_EICU_USE_TIM10 TRUE
+#define STM32_EICU_USE_TIM11 TRUE
+#define STM32_EICU_USE_TIM12 TRUE
+#define STM32_EICU_USE_TIM13 TRUE
+#define STM32_EICU_USE_TIM14 TRUE
+#define STM32_EICU_TIM1_IRQ_PRIORITY 7
+#define STM32_EICU_TIM2_IRQ_PRIORITY 7
+#define STM32_EICU_TIM3_IRQ_PRIORITY 7
+#define STM32_EICU_TIM4_IRQ_PRIORITY 7
+#define STM32_EICU_TIM5_IRQ_PRIORITY 7
+#define STM32_EICU_TIM8_IRQ_PRIORITY 7
+#define STM32_EICU_TIM9_IRQ_PRIORITY 7
+#define STM32_EICU_TIM10_IRQ_PRIORITY 7
+#define STM32_EICU_TIM11_IRQ_PRIORITY 7
+#define STM32_EICU_TIM12_IRQ_PRIORITY 7
+#define STM32_EICU_TIM13_IRQ_PRIORITY 7
+#define STM32_EICU_TIM14_IRQ_PRIORITY 7
+
+/*
+ * QEI driver system settings.
+ */
+#define STM32_QEI_USE_TIM1 TRUE
+#define STM32_QEI_USE_TIM2 FALSE
+#define STM32_QEI_USE_TIM3 TRUE
+#define STM32_QEI_TIM1_IRQ_PRIORITY 3
+#define STM32_QEI_TIM2_IRQ_PRIORITY 3
+#define STM32_QEI_TIM3_IRQ_PRIORITY 3