diff options
Diffstat (limited to 'testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c')
| -rw-r--r-- | testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 83 |
1 files changed, 2 insertions, 81 deletions
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 1ec34d2..0d3feee 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -23,7 +23,6 @@ #include "string.h" -#include "hal_fsmc_sdram.h" #include "membench.h" #include "memtest.h" @@ -33,84 +32,6 @@ ****************************************************************************** */ -/* - * FMC SDRAM Mode definition register defines - */ -#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) -#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) -#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) -#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) -#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) -#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/* - * FMC_ReadPipe_Delay - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) -#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) - -/* - * FMC_Read_Burst - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) -#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) - -/* - * FMC_SDClock_Period - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) -#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) - -/* - * FMC_ColumnBits_Number - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -/* - * FMC_RowBits_Number - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -/* - * FMC_SDMemory_Data_Width - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -/* - * FMC_InternalBank_Number - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -/* - * FMC_CAS_Latency - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -/* - * FMC_Write_Protection - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) #define SDRAM_SIZE (8 * 1024 * 1024) #define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) @@ -262,8 +183,8 @@ int main(void) { halInit(); chSysInit(); - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); + sdramInit(); + sdramStart(&SDRAMD1, &sdram_cfg); membench(); memtest(); |