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Diffstat (limited to 'testhal/STM32/STM32F0xx/crc/mcuconf.h')
-rw-r--r--testhal/STM32/STM32F0xx/crc/mcuconf.h76
1 files changed, 57 insertions, 19 deletions
diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf.h b/testhal/STM32/STM32F0xx/crc/mcuconf.h
index ad184cd..98a9e21 100644
--- a/testhal/STM32/STM32F0xx/crc/mcuconf.h
+++ b/testhal/STM32/STM32F0xx/crc/mcuconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2015 Michael D. Spradling
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,8 +14,8 @@
limitations under the License.
*/
-#ifndef _MCUCONF_H_
-#define _MCUCONF_H_
+#ifndef MCUCONF_H
+#define MCUCONF_H
/*
* STM32F0xx drivers configuration.
@@ -50,32 +50,33 @@
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
-#define STM32_ADCSW STM32_ADCSW_HSI14
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
-#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
+#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
- * ADC driver system settings.
+ * IRQ system settings.
*/
-#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_PRIORITY 2
-#define STM32_ADC_IRQ_PRIORITY 2
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
+#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
/*
- * EXT driver system settings.
+ * ADC driver system settings.
*/
-#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
/*
* GPT driver system settings.
@@ -100,9 +101,32 @@
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
@@ -140,6 +164,10 @@
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@@ -157,10 +185,20 @@
#define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+/*
* header for community drivers.
*/
#include "mcuconf_community.h"
-#endif /* _MCUCONF_H_ */
+
+#endif /* MCUCONF_H */