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-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/driver.mk14
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c193
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h351
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h172
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c24
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h36
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c (renamed from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c)107
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h (renamed from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h)107
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c (renamed from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c)61
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h91
10 files changed, 194 insertions, 962 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
index d92230d..8c354a5 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
+++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk
@@ -1,16 +1,16 @@
ifeq ($(USE_SMART_BUILD),yes)
-ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),)
-PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
+endif
+ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),)
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c
endif
ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
endif
else
-PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \
+PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
deleted file mode 100644
index 71c6ada..0000000
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_fsmc.c
- * @brief FSMC Driver subsystem low level driver source template.
- *
- * @addtogroup FSMC
- * @{
- */
-#include "hal.h"
-#include "hal_fsmc.h"
-
-#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief FSMC1 driver identifier.
- */
-#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__)
-FSMCDriver FSMCD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level FSMC driver initialization.
- *
- * @notapi
- */
-void fsmc_init(void) {
-
- if (FSMCD1.state == FSMC_UNINIT) {
- FSMCD1.state = FSMC_STOP;
-
-#if STM32_SRAM_USE_FSMC_SRAM1
- FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM2
- FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM3
- FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM4
- FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
-#endif
-
-#if STM32_NAND_USE_FSMC_NAND1
- FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
-#endif
-
-#if STM32_NAND_USE_FSMC_NAND2
- FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
-#endif
-
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F745xx) || defined(STM32F746xx) || \
- defined(STM32F756xx) || defined(STM32F767xx) || \
- defined(STM32F769xx) || defined(STM32F777xx) || \
- defined(STM32F779xx))
- #if STM32_USE_FSMC_SDRAM
- FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
- #endif
-#endif
- }
-}
-
-/**
- * @brief Configures and activates the FSMC peripheral.
- *
- * @param[in] fsmcp pointer to the @p FSMCDriver object
- *
- * @notapi
- */
-void fsmc_start(FSMCDriver *fsmcp) {
-
- osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
- "invalid state");
-
- if (fsmcp->state == FSMC_STOP) {
- /* Enables the peripheral.*/
-#if STM32_FSMC_USE_FSMC1
- if (&FSMCD1 == fsmcp) {
-#ifdef rccResetFSMC
- rccResetFSMC();
-#endif
- rccEnableFSMC(FALSE);
-#if HAL_USE_NAND
- nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
-#endif
- }
-#endif /* STM32_FSMC_USE_FSMC1 */
-
- fsmcp->state = FSMC_READY;
- }
-}
-
-/**
- * @brief Deactivates the FSMC peripheral.
- *
- * @param[in] emcp pointer to the @p FSMCDriver object
- *
- * @notapi
- */
-void fsmc_stop(FSMCDriver *fsmcp) {
-
- if (fsmcp->state == FSMC_READY) {
- /* Resets the peripheral.*/
-#ifdef rccResetFSMC
- rccResetFSMC();
-#endif
-
- /* Disables the peripheral.*/
-#if STM32_FSMC_USE_FSMC1
- if (&FSMCD1 == fsmcp) {
-#if HAL_USE_NAND
- nvicDisableVector(STM32_FSMC_NUMBER);
-#endif
- rccDisableFSMC();
- }
-#endif /* STM32_FSMC_USE_FSMC1 */
-
- fsmcp->state = FSMC_STOP;
- }
-}
-
-/**
- * @brief FSMC shared interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-#if STM32_NAND_USE_FSMC_NAND1
- if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) {
- NANDD1.isr_handler(&NANDD1);
- }
-#endif
-#if STM32_NAND_USE_FSMC_NAND2
- if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) {
- NANDD2.isr_handler(&NANDD2);
- }
-#endif
- CH_IRQ_EPILOGUE();
-}
-
-#endif /* HAL_USE_FSMC */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
deleted file mode 100644
index 80c5d26..0000000
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_fsmc.h
- * @brief FSMC Driver subsystem low level driver header.
- *
- * @addtogroup FSMC
- * @{
- */
-
-#ifndef HAL_FSMC_H_
-#define HAL_FSMC_H_
-
-#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*
- * (Re)define if needed base address constants supplied in ST's CMSIS
- */
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F745xx) || defined(STM32F746xx) || \
- defined(STM32F756xx) || defined(STM32F767xx) || \
- defined(STM32F769xx) || defined(STM32F777xx) || \
- defined(STM32F779xx))
- #if !defined(FSMC_Bank1_R_BASE)
- #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
- #endif
- #if !defined(FSMC_Bank1E_R_BASE)
- #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
- #endif
- #if !defined(FSMC_Bank2_R_BASE)
- #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
- #endif
- #if !defined(FSMC_Bank3_R_BASE)
- #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
- #endif
- #if !defined(FSMC_Bank4_R_BASE)
- #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
- #endif
- #if !defined(FSMC_Bank5_R_BASE)
- #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
- #endif
-#else
- #if !defined(FSMC_Bank1_R_BASE)
- #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
- #endif
- #if !defined(FSMC_Bank1E_R_BASE)
- #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
- #endif
- #if !defined(FSMC_Bank2_R_BASE)
- #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
- #endif
- #if !defined(FSMC_Bank3_R_BASE)
- #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
- #endif
- #if !defined(FSMC_Bank4_R_BASE)
- #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
- #endif
-#endif
-
-/*
- * Base bank mappings
- */
-#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000)
-#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000)
-#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
-#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
- #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000)
- #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000)
-#endif
-
-/*
- * Subbunks of bank1
- */
-#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
-#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
-#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
-#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
-#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
-
-/*
- * Bank 2 (NAND)
- */
-#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0)
-#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000)
-
-#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0)
-#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000)
-#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000)
-
-#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0)
-#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000)
-#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000)
-
-/*
- * Bank 3 (NAND)
- */
-#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0)
-#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000)
-
-#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0)
-#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000)
-#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000)
-
-#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0)
-#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000)
-#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000)
-
-/*
- * Bank 4 (PC card)
- */
-#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0)
-#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000)
-#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000)
-
-/*
- * More convenient typedefs than CMSIS has
- */
-typedef struct {
- __IO uint32_t PCR; /**< NAND Flash control */
- __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */
- __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */
- __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */
- uint32_t RESERVED0; /**< Reserved, 0x70 */
- __IO uint32_t ECCR; /**< NAND Flash ECC result registers */
-} FSMC_NAND_TypeDef;
-
-typedef struct {
- __IO uint32_t PCR; /**< PC Card control */
- __IO uint32_t SR; /**< PC Card FIFO status and interrupt */
- __IO uint32_t PMEM; /**< PC Card Common memory space timing */
- __IO uint32_t PATT; /**< PC Card Attribute memory space timing */
- __IO uint32_t PIO; /**< PC Card I/O space timing */
-} FSMC_PCCard_TypeDef;
-
-typedef struct {
- __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
- __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
- uint32_t RESERVED[63]; /**< Reserved */
- __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
-} FSMC_SRAM_NOR_TypeDef;
-
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
-
-typedef struct {
- __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */
- __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */
- __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */
- __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */
- __IO uint32_t SDCMR; /**< SDRAM comand mode register */
- __IO uint32_t SDRTR; /**< SDRAM refresh timer register */
- __IO uint32_t SDSR; /**< SDRAM status register */
-} FSMC_SDRAM_TypeDef;
-
-#endif
-
-/**
- * @brief PCR register
- */
-#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1)
-#define FSMC_PCR_PBKEN ((uint32_t)1 << 2)
-#define FSMC_PCR_PTYP ((uint32_t)1 << 3)
-#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4)
-#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4)
-#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4)
-#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4)
-#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4)
-#define FSMC_PCR_ECCEN ((uint32_t)1 << 6)
-#define FSMC_PCR_PTYP_PCCARD 0
-#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP
-
-/**
- * @brief SR register
- */
-#define FSMC_SR_IRS ((uint8_t)0x01)
-#define FSMC_SR_ILS ((uint8_t)0x02)
-#define FSMC_SR_IFS ((uint8_t)0x04)
-#define FSMC_SR_IREN ((uint8_t)0x08)
-#define FSMC_SR_ILEN ((uint8_t)0x10)
-#define FSMC_SR_IFEN ((uint8_t)0x20)
-#define FSMC_SR_FEMPT ((uint8_t)0x40)
-#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
-
-/**
- * @brief BCR register
- */
-#define FSMC_BCR_MBKEN ((uint32_t)1 << 0)
-#define FSMC_BCR_MUXEN ((uint32_t)1 << 1)
-#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2)
-#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2)
-#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2)
-#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2)
-#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4)
-#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
-#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
-#else
-#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
-#endif
-#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4)
-#define FSMC_BCR_FACCEN ((uint32_t)1 << 6)
-#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8)
-#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9)
-#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10)
-#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11)
-#define FSMC_BCR_WREN ((uint32_t)1 << 12)
-#define FSMC_BCR_WAITEN ((uint32_t)1 << 13)
-#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14)
-#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15)
-#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
-#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
-#endif
-#if (defined(STM32F7))
-#define FSMC_BCR_WFDIS ((uint32_t)1 << 21)
-#endif
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief FSMC driver enable switch.
- * @details If set to @p TRUE the support for FSMC is included.
- */
-#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__)
-#define STM32_FSMC_USE_FSMC1 FALSE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-#if !STM32_FSMC_USE_FSMC1
-#error "FSMC driver activated but no FSMC peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an FSMC driver.
- */
-typedef struct FSMCDriver FSMCDriver;
-
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- FSMC_UNINIT = 0, /**< Not initialized. */
- FSMC_STOP = 1, /**< Stopped. */
- FSMC_READY = 2, /**< Ready. */
-} fsmcstate_t;
-
-/**
- * @brief Structure representing an FSMC driver.
- */
-struct FSMCDriver {
- /**
- * @brief Driver state.
- */
- fsmcstate_t state;
- /* End of the mandatory fields.*/
-
-#if STM32_SRAM_USE_FSMC_SRAM1
- FSMC_SRAM_NOR_TypeDef *sram1;
-#endif
-#if STM32_SRAM_USE_FSMC_SRAM2
- FSMC_SRAM_NOR_TypeDef *sram2;
-#endif
-#if STM32_SRAM_USE_FSMC_SRAM3
- FSMC_SRAM_NOR_TypeDef *sram3;
-#endif
-#if STM32_SRAM_USE_FSMC_SRAM4
- FSMC_SRAM_NOR_TypeDef *sram4;
-#endif
-#if STM32_NAND_USE_FSMC_NAND1
- FSMC_NAND_TypeDef *nand1;
-#endif
-#if STM32_NAND_USE_FSMC_NAND2
- FSMC_NAND_TypeDef *nand2;
-#endif
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
- #if STM32_USE_FSMC_SDRAM
- FSMC_SDRAM_TypeDef *sdram;
- #endif
-#endif
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__)
-extern FSMCDriver FSMCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void fsmc_init(void);
- void fsmc_start(FSMCDriver *fsmcp);
- void fsmc_stop(FSMCDriver *fsmcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_FSMC */
-
-#endif /* HAL_FSMC_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h
deleted file mode 100644
index 5e749a8..0000000
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file hal_fsmc_sram.h
- * @brief SRAM Driver subsystem low level driver header.
- *
- * @addtogroup SRAM
- * @{
- */
-
-#ifndef HAL_FSMC_SRAM_H_
-#define HAL_FSMC_SRAM_H_
-
-#include "hal_fsmc.h"
-
-#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-/**
- * @name Configuration options
- * @{
- */
-
-/**
- * @brief SRAM driver enable switch.
- * @details If set to @p TRUE the support for SRAM1 is included.
- */
-#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
-#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
-#endif
-
-/**
- * @brief SRAM driver enable switch.
- * @details If set to @p TRUE the support for SRAM2 is included.
- */
-#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
-#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
-#endif
-
-/**
- * @brief SRAM driver enable switch.
- * @details If set to @p TRUE the support for SRAM3 is included.
- */
-#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
-#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
-#endif
-
-/**
- * @brief SRAM driver enable switch.
- * @details If set to @p TRUE the support for SRAM4 is included.
- */
-#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
-#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
- !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
-#error "SRAM driver activated but no SRAM peripheral assigned"
-#endif
-
-#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
- STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
-#error "FSMC not present in the selected device"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- SRAM_UNINIT = 0, /**< Not initialized. */
- SRAM_STOP = 1, /**< Stopped. */
- SRAM_READY = 2, /**< Ready. */
-} sramstate_t;
-
-/**
- * @brief Type of a structure representing an NAND driver.
- */
-typedef struct SRAMDriver SRAMDriver;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- * @note Some bits in BCR register will be forced by driver.
- */
-typedef struct {
- uint32_t bcr;
- uint32_t btr;
- uint32_t bwtr;
-} SRAMConfig;
-
-/**
- * @brief Structure representing an NAND driver.
- */
-struct SRAMDriver {
- /**
- * @brief Driver state.
- */
- sramstate_t state;
- /**
- * @brief Pointer to the FSMC SRAM registers block.
- */
- FSMC_SRAM_NOR_TypeDef *sram;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
-extern SRAMDriver SRAMD1;
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
-extern SRAMDriver SRAMD2;
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
-extern SRAMDriver SRAMD3;
-#endif
-
-#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
-extern SRAMDriver SRAMD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void fsmcSramInit(void);
- void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
- void fsmcSramStop(SRAMDriver *sramp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_USE_FSMC_SRAM */
-
-#endif /* HAL_FSMC_SRAM_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
index cc6dc20..abd5aa3 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
@@ -15,8 +15,8 @@
*/
/**
- * @file hal_nand_lld.c
- * @brief NAND Driver subsystem low level driver source.
+ * @file hal_fsmc_nand_lld.c
+ * @brief FSMC NAND Driver subsystem low level driver source.
*
* @addtogroup NAND
* @{
@@ -26,6 +26,8 @@
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
+#include "hal_nand_lld.h"
+
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@@ -53,14 +55,14 @@
/**
* @brief NAND1 driver identifier.
*/
-#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__)
+#if STM32_NAND_USE_NAND1 || defined(__DOXYGEN__)
NANDDriver NANDD1;
#endif
/**
* @brief NAND2 driver identifier.
*/
-#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__)
+#if STM32_NAND_USE_NAND2 || defined(__DOXYGEN__)
NANDDriver NANDD2;
#endif
@@ -280,9 +282,9 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) {
*/
void nand_lld_init(void) {
- fsmc_init();
+ fsmcInit();
-#if STM32_NAND_USE_FSMC_NAND1
+#if STM32_NAND_USE_NAND1
/* Driver initialization.*/
nandObjectInit(&NANDD1);
NANDD1.rxdata = NULL;
@@ -294,9 +296,9 @@ void nand_lld_init(void) {
NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD;
NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR;
NANDD1.bb_map = NULL;
-#endif /* STM32_NAND_USE_FSMC_NAND1 */
+#endif /* STM32_NAND_USE_NAND1 */
-#if STM32_NAND_USE_FSMC_NAND2
+#if STM32_NAND_USE_NAND2
/* Driver initialization.*/
nandObjectInit(&NANDD2);
NANDD2.rxdata = NULL;
@@ -308,7 +310,7 @@ void nand_lld_init(void) {
NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD;
NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR;
NANDD2.bb_map = NULL;
-#endif /* STM32_NAND_USE_FSMC_NAND2 */
+#endif /* STM32_NAND_USE_NAND2 */
}
/**
@@ -325,7 +327,7 @@ void nand_lld_start(NANDDriver *nandp) {
uint32_t pcr_bus_width;
if (FSMCD1.state == FSMC_STOP)
- fsmc_start(&FSMCD1);
+ fsmcStart(&FSMCD1);
if (nandp->state == NAND_STOP) {
b = dmaStreamAlloc(nandp->dma,
@@ -345,7 +347,7 @@ void nand_lld_start(NANDDriver *nandp) {
#endif
nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_NAND_DMA_PRIORITY) |
dmasize |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE |
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
index 5266138..51f2b95 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
@@ -16,7 +16,7 @@
/**
* @file hal_nand_lld.h
- * @brief NAND Driver subsystem low level driver header.
+ * @brief FSMC NAND Driver subsystem low level driver header.
*
* @addtogroup NAND
* @{
@@ -25,8 +25,8 @@
#ifndef HAL_NAND_LLD_H_
#define HAL_NAND_LLD_H_
-#include "hal_fsmc.h"
#include "bitmap.h"
+#include "hal_fsmc.h"
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
@@ -72,38 +72,38 @@
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
-#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
+#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
#endif
/**
* @brief NAND interrupt enable switch.
* @details If set to @p TRUE the support for internal FSMC interrupt included.
*/
-#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_INT FALSE
+#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__)
+#define STM32_FSMC_NAND_USE_INT FALSE
#endif
/**
* @brief NAND1 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_NAND_NAND1_DMA_PRIORITY 0
+#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_FSMC_NAND1_DMA_PRIORITY 0
#endif
/**
* @brief NAND2 DMA priority (0..3|lowest..highest).
*/
-#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_NAND_NAND2_DMA_PRIORITY 0
+#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_FSMC_NAND2_DMA_PRIORITY 0
#endif
/**
* @brief DMA stream used for NAND operations.
* @note This option is only available on platforms with enhanced DMA.
*/
-#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#endif
/** @} */
@@ -112,18 +112,14 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2
+#if !STM32_NAND_USE_NAND1 && !STM32_NAND_USE_NAND2
#error "NAND driver activated but no NAND peripheral assigned"
#endif
-#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
+#if (STM32_NAND_USE_NAND1 || STM32_NAND_USE_NAND2) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -260,11 +256,11 @@ struct NANDDriver {
/* External declarations. */
/*===========================================================================*/
-#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__)
+#if STM32_NAND_USE_NAND1 && !defined(__DOXYGEN__)
extern NANDDriver NANDD1;
#endif
-#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__)
+#if STM32_NAND_USE_NAND2 && !defined(__DOXYGEN__)
extern NANDDriver NANDD2;
#endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
index 6d727c8..66f7b80 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
@@ -34,9 +34,9 @@
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
-#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
+#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
-#include "hal_fsmc_sdram.h"
+#include "hal_sdram_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
@@ -59,7 +59,7 @@
/**
* @brief SDRAM driver identifier.
*/
-SDRAMDriver SDRAMD;
+SDRAMDriver SDRAMD1;
/*===========================================================================*/
/* Driver local types. */
@@ -78,9 +78,9 @@ SDRAMDriver SDRAMD;
*
* @notapi
*/
-static void _sdram_wait_ready(void) {
+static void sdram_lld_wait_ready(void) {
/* Wait until the SDRAM controller is ready */
- while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY);
+ while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY);
}
/**
@@ -90,48 +90,48 @@ static void _sdram_wait_ready(void) {
*
* @notapi
*/
-static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
+static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) {
uint32_t command_target = 0;
-#if STM32_SDRAM_USE_FSMC_SDRAM1
+#if STM32_SDRAM_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
-#if STM32_SDRAM_USE_FSMC_SDRAM2
+#if STM32_SDRAM_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
/* Step 3: Configure a clock configuration enable command.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
/* Step 4: Insert delay (tipically 100uS).*/
osalThreadSleepMilliseconds(1);
/* Step 5: Configure a PALL (precharge all) command.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target;
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target;
/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 6.2: Send the second command.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 7: Program the external memory mode register.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
(cfgp->sdcmr & FMC_SDCMR_MRD);
/* Step 8: Set clock.*/
- _sdram_wait_ready();
- SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
+ sdram_lld_wait_ready();
+ SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
- _sdram_wait_ready();
+ sdram_lld_wait_ready();
}
/*===========================================================================*/
@@ -142,71 +142,28 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
/* Driver exported functions. */
/*===========================================================================*/
-/**
- * @brief Low level SDRAM driver initialization.
- */
-void fsmcSdramInit(void) {
-
- fsmc_init();
+void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
+{
+ sdramp->sdram->SDCR1 = cfgp->sdcr;
+ sdramp->sdram->SDTR1 = cfgp->sdtr;
+ sdramp->sdram->SDCR2 = cfgp->sdcr;
+ sdramp->sdram->SDTR2 = cfgp->sdtr;
- SDRAMD.sdram = FSMCD1.sdram;
- SDRAMD.state = SDRAM_STOP;
+ sdram_lld_init_sequence(cfgp);
}
-/**
- * @brief Configures and activates the SDRAM peripheral.
- *
- * @param[in] sdramp pointer to the @p SDRAMDriver object
- * @param[in] cfgp pointer to the @p SDRAMConfig object
- */
-void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
-
- if (FSMCD1.state == FSMC_STOP)
- fsmc_start(&FSMCD1);
-
- osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
- "SDRAM. Invalid state.");
-
- if (sdramp->state == SDRAM_STOP) {
-
- /* Even if you need only bank2 you must properly set up SDCR and SDTR
- regitsters for bank1 too. Both banks will be tuned equally assuming
- connected memory ICs are equal.*/
- sdramp->sdram->SDCR1 = cfgp->sdcr;
- sdramp->sdram->SDTR1 = cfgp->sdtr;
- sdramp->sdram->SDCR2 = cfgp->sdcr;
- sdramp->sdram->SDTR2 = cfgp->sdtr;
-
- _sdram_init_sequence(cfgp);
-
- sdramp->state = SDRAM_READY;
- }
-}
-
-/**
- * @brief Deactivates the SDRAM peripheral.
- *
- * @param[in] sdramp pointer to the @p SDRAMDriver object
- *
- * @notapi
- */
-void fsmcSdramStop(SDRAMDriver *sdramp) {
-
+void sdram_lld_stop(SDRAMDriver *sdramp) {
uint32_t command_target = 0;
-#if STM32_SDRAM_USE_FSMC_SDRAM1
+#if STM32_SDRAM_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
-#if STM32_SDRAM_USE_FSMC_SDRAM2
+#if STM32_SDRAM_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
- if (sdramp->state == SDRAM_READY) {
- SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
- sdramp->state = SDRAM_STOP;
- }
+ sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
}
-
#endif /* STM32_USE_FSMC_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
index c9f9de0..665c570 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
@@ -18,26 +18,19 @@
*/
/**
- * @file hal_fsmc_sdram.h
+ * @file hal_sdram.h
* @brief SDRAM Driver subsystem low level driver header.
*
* @addtogroup SDRAM
* @{
*/
-#ifndef HAL_FMC_SDRAM_H_
-#define HAL_FMC_SDRAM_H_
-
-#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F745xx) || defined(STM32F746xx) || \
- defined(STM32F756xx) || defined(STM32F767xx) || \
- defined(STM32F769xx) || defined(STM32F777xx) || \
- defined(STM32F779xx))
+#ifndef HAL_SDRAM_LLD_H_
+#define HAL_SDRAM_LLD_H_
#include "hal_fsmc.h"
-#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
+#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@@ -55,8 +48,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM1 is included.
*/
-#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__)
-#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
+#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__)
+#define STM32_SDRAM_USE_SDRAM1 FALSE
#else
#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
#endif
@@ -65,8 +58,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM2 is included.
*/
-#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__)
-#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE
+#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__)
+#define STM32_SDRAM_USE_SDRAM2 FALSE
#else
#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
#endif
@@ -77,74 +70,27 @@
/* Derived constants and error checks. */
/*===========================================================================*/
-#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2
+#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2
#error "SDRAM driver activated but no SDRAM peripheral assigned"
#endif
-#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC
+#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC
#error "FMC not present in the selected device"
#endif
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
+#else
+#error "Device is not compatible with SDRAM"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
-/**
- * @brief Driver state machine possible states.
- */
-typedef enum {
- SDRAM_UNINIT = 0, /**< Not initialized. */
- SDRAM_STOP = 1, /**< Stopped. */
- SDRAM_READY = 2, /**< Ready. */
-} sdramstate_t;
-
-/**
- * @brief Type of a structure representing an SDRAM driver.
- */
-typedef struct SDRAMDriver SDRAMDriver;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief SDRAM control register.
- * @note Its value will be used for both banks.
- */
- uint32_t sdcr;
-
- /**
- * @brief SDRAM timing register.
- * @note Its value will be used for both banks.
- */
- uint32_t sdtr;
-
- /**
- * @brief SDRAM command mode register.
- * @note Only its MRD and NRFS bits will be used.
- */
- uint32_t sdcmr;
-
- /**
- * @brief SDRAM refresh timer register.
- * @note Only its COUNT bits will be used.
- */
- uint32_t sdrtr;
-} SDRAMConfig;
-
-/**
- * @brief Structure representing an SDRAM driver.
- */
-struct SDRAMDriver {
- /**
- * @brief Driver state.
- */
- sdramstate_t state;
- /**
- * @brief Pointer to the FMC SDRAM registers block.
- */
- FSMC_SDRAM_TypeDef *sdram;
-};
/*===========================================================================*/
/* Driver macros. */
@@ -154,22 +100,19 @@ struct SDRAMDriver {
/* External declarations. */
/*===========================================================================*/
-extern SDRAMDriver SDRAMD;
+extern SDRAMDriver SDRAMD1;
#ifdef __cplusplus
extern "C" {
#endif
- void fsmcSdramInit(void);
- void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
- void fsmcSdramStop(SDRAMDriver *sdramp);
+ void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
+ void sdram_lld_stop(SDRAMDriver *sdramp);
#ifdef __cplusplus
}
#endif
-#endif /* STM32_USE_FSMC_SDRAM */
-
-#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
+#endif /* STM32_SDRAM_USE_SDRAM */
-#endif /* HAL_FMC_SDRAM_H_ */
+#endif /* HAL_SDRAM_LLD_H_ */
/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c
index da13ca5..71ecacd 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c
@@ -22,9 +22,10 @@
* @{
*/
#include "hal.h"
-#include "hal_fsmc_sram.h"
-#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__)
+#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_sram_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
@@ -36,28 +37,28 @@
/**
* @brief SRAM1 driver identifier.
*/
-#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__)
+#if STM32_SRAM_USE_SRAM1 || defined(__DOXYGEN__)
SRAMDriver SRAMD1;
#endif
/**
* @brief SRAM2 driver identifier.
*/
-#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__)
+#if STM32_SRAM_USE_SRAM2 || defined(__DOXYGEN__)
SRAMDriver SRAMD2;
#endif
/**
* @brief SRAM3 driver identifier.
*/
-#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__)
+#if STM32_SRAM_USE_SRAM3 || defined(__DOXYGEN__)
SRAMDriver SRAMD3;
#endif
/**
* @brief SRAM4 driver identifier.
*/
-#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__)
+#if STM32_SRAM_USE_SRAM4 || defined(__DOXYGEN__)
SRAMDriver SRAMD4;
#endif
@@ -82,36 +83,6 @@ SRAMDriver SRAMD4;
/*===========================================================================*/
/**
- * @brief Low level SRAM driver initialization.
- *
- * @notapi
- */
-void fsmcSramInit(void) {
-
- fsmc_init();
-
-#if STM32_SRAM_USE_FSMC_SRAM1
- SRAMD1.sram = FSMCD1.sram1;
- SRAMD1.state = SRAM_STOP;
-#endif /* STM32_SRAM_USE_FSMC_SRAM1 */
-
-#if STM32_SRAM_USE_FSMC_SRAM2
- SRAMD2.sram = FSMCD1.sram2;
- SRAMD2.state = SRAM_STOP;
-#endif /* STM32_SRAM_USE_FSMC_SRAM2 */
-
-#if STM32_SRAM_USE_FSMC_SRAM3
- SRAMD3.sram = FSMCD1.sram3;
- SRAMD3.state = SRAM_STOP;
-#endif /* STM32_SRAM_USE_FSMC_SRAM3 */
-
-#if STM32_SRAM_USE_FSMC_SRAM4
- SRAMD4.sram = FSMCD1.sram4;
- SRAMD4.state = SRAM_STOP;
-#endif /* STM32_SRAM_USE_FSMC_SRAM4 */
-}
-
-/**
* @brief Configures and activates the SRAM peripheral.
*
* @param[in] sramp pointer to the @p SRAMDriver object
@@ -119,20 +90,11 @@ void fsmcSramInit(void) {
*
* @notapi
*/
-void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
-
- if (FSMCD1.state == FSMC_STOP)
- fsmc_start(&FSMCD1);
-
- osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
- "invalid state");
+void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp) {
- if (sramp->state == SRAM_STOP) {
sramp->sram->BTR = cfgp->btr;
sramp->sram->BWTR = cfgp->bwtr;
sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN;
- sramp->state = SRAM_READY;
- }
}
/**
@@ -142,9 +104,8 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
*
* @notapi
*/
-void fsmcSramStop(SRAMDriver *sramp) {
+void sram_lld_stop(SRAMDriver *sramp) {
- if (sramp->state == SRAM_READY) {
uint32_t mask = FSMC_BCR_MBKEN;
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
@@ -155,11 +116,9 @@ void fsmcSramStop(SRAMDriver *sramp) {
mask |= FSMC_BCR_CCLKEN;
#endif
sramp->sram->BCR &= ~mask;
- sramp->state = SRAM_STOP;
- }
}
-#endif /* STM32_USE_FSMC_SRAM */
+#endif /* STM32_SRAM_USE_SRAM */
/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h
new file mode 100644
index 0000000..857a96e
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h
@@ -0,0 +1,91 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_fsmc_sram.h
+ * @brief SRAM Driver subsystem low level driver header.
+ *
+ * @addtogroup SRAM
+ * @{
+ */
+
+#ifndef HAL_SRAM_LLD_H_
+#define HAL_SRAM_LLD_H_
+
+#include "hal_fsmc.h"
+
+#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD1;
+#endif
+
+#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD2;
+#endif
+
+#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD3;
+#endif
+
+#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp);
+ void sram_lld_stop(SRAMDriver *sramp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_SRAM_USE_SRAM */
+
+#endif /* HAL_SRAM_LLD_H_ */
+
+/** @} */