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-rw-r--r--os/hal/include/hal_community.h25
-rw-r--r--os/hal/include/hal_fsmc.h364
-rw-r--r--os/hal/include/hal_nand.h1
-rw-r--r--os/hal/include/hal_sdram.h244
-rw-r--r--os/hal/include/hal_sram.h171
5 files changed, 800 insertions, 5 deletions
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index f84e90a..435115b 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -27,6 +27,10 @@
/* Error checks on the configuration header file.*/
+#if !defined(HAL_USE_COMP)
+#define HAL_USE_COMP FALSE
+#endif
+
#if !defined(HAL_USE_CRC)
#define HAL_USE_CRC FALSE
#endif
@@ -39,6 +43,10 @@
#define HAL_USE_EICU FALSE
#endif
+#if !defined(HAL_USE_FSMC)
+#define HAL_USE_FSMC FALSE
+#endif
+
#if !defined(HAL_USE_NAND)
#define HAL_USE_NAND FALSE
#endif
@@ -47,6 +55,10 @@
#define HAL_USE_ONEWIRE FALSE
#endif
+#if !defined(HAL_USE_OPAMP)
+#define HAL_USE_OPAMP FALSE
+#endif
+
#if !defined(HAL_USE_QEI)
#define HAL_USE_QEI FALSE
#endif
@@ -71,12 +83,12 @@
#define HAL_USE_USB_MSD FALSE
#endif
-#if !defined(HAL_USE_COMP)
-#define HAL_USE_COMP FALSE
+#if !defined(HAL_USE_SDRAM)
+#define HAL_USE_SDRAM FALSE
#endif
-#if !defined(HAL_USE_OPAMP)
-#define HAL_USE_OPAMP FALSE
+#if !defined(HAL_USE_SRAM)
+#define HAL_USE_SRAM FALSE
#endif
/* Abstract interfaces.*/
@@ -84,7 +96,6 @@
/* Shared headers.*/
/* Normal drivers.*/
-#include "hal_nand.h"
#include "hal_eicu.h"
#include "hal_rng.h"
#include "hal_usbh.h"
@@ -92,6 +103,7 @@
#include "hal_qei.h"
#include "hal_comp.h"
#include "hal_opamp.h"
+#include "hal_fsmc.h"
/* Complex drivers.*/
#include "hal_onewire.h"
@@ -99,6 +111,9 @@
#include "hal_eeprom.h"
#include "hal_usb_hid.h"
#include "hal_usb_msd.h"
+#include "hal_nand.h"
+#include "hal_sram.h"
+#include "hal_sdram.h"
/*===========================================================================*/
/* Driver constants. */
diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h
new file mode 100644
index 0000000..3c5d999
--- /dev/null
+++ b/os/hal/include/hal_fsmc.h
@@ -0,0 +1,364 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_fsmc.h
+ * @brief FSMC Driver subsystem low level driver header.
+ *
+ * @addtogroup FSMC
+ * @{
+ */
+
+#ifndef HAL_FSMC_H_
+#define HAL_FSMC_H_
+
+#include "hal.h"
+
+#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * (Re)define if needed base address constants supplied in ST's CMSIS
+ */
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
+ #if !defined(FSMC_Bank1_R_BASE)
+ #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+ #endif
+ #if !defined(FSMC_Bank1E_R_BASE)
+ #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+ #endif
+ #if !defined(FSMC_Bank2_R_BASE)
+ #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
+ #endif
+ #if !defined(FSMC_Bank3_R_BASE)
+ #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+ #endif
+ #if !defined(FSMC_Bank4_R_BASE)
+ #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+ #endif
+ #if !defined(FSMC_Bank5_R_BASE)
+ #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+ #endif
+#else
+ #if !defined(FSMC_Bank1_R_BASE)
+ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
+ #endif
+ #if !defined(FSMC_Bank1E_R_BASE)
+ #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
+ #endif
+ #if !defined(FSMC_Bank2_R_BASE)
+ #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
+ #endif
+ #if !defined(FSMC_Bank3_R_BASE)
+ #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
+ #endif
+ #if !defined(FSMC_Bank4_R_BASE)
+ #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
+ #endif
+#endif
+
+/*
+ * Base bank mappings
+ */
+#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000)
+#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000)
+#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
+#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F7))
+ #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000)
+ #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000)
+#endif
+
+/*
+ * Subbunks of bank1
+ */
+#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
+#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
+#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
+#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
+#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
+
+/*
+ * Bank 2 (NAND)
+ */
+#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0)
+#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000)
+
+#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0)
+#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000)
+#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000)
+
+#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0)
+#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000)
+#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000)
+
+/*
+ * Bank 3 (NAND)
+ */
+#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0)
+#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000)
+
+#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0)
+#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000)
+#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000)
+
+#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0)
+#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000)
+#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000)
+
+/*
+ * Bank 4 (PC card)
+ */
+#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0)
+#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000)
+#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000)
+
+/*
+ * More convenient typedefs than CMSIS has
+ */
+typedef struct {
+ __IO uint32_t PCR; /**< NAND Flash control */
+ __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */
+ __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */
+ __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */
+ uint32_t RESERVED0; /**< Reserved, 0x70 */
+ __IO uint32_t ECCR; /**< NAND Flash ECC result registers */
+} FSMC_NAND_TypeDef;
+
+typedef struct {
+ __IO uint32_t PCR; /**< PC Card control */
+ __IO uint32_t SR; /**< PC Card FIFO status and interrupt */
+ __IO uint32_t PMEM; /**< PC Card Common memory space timing */
+ __IO uint32_t PATT; /**< PC Card Attribute memory space timing */
+ __IO uint32_t PIO; /**< PC Card I/O space timing */
+} FSMC_PCCard_TypeDef;
+
+typedef struct {
+ __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
+ __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
+ uint32_t RESERVED[63]; /**< Reserved */
+ __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
+} FSMC_SRAM_TypeDef;
+
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F7))
+
+typedef struct {
+ __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */
+ __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */
+ __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */
+ __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */
+ __IO uint32_t SDCMR; /**< SDRAM comand mode register */
+ __IO uint32_t SDRTR; /**< SDRAM refresh timer register */
+ __IO uint32_t SDSR; /**< SDRAM status register */
+} FSMC_SDRAM_TypeDef;
+
+#endif
+
+/**
+ * @brief PCR register
+ */
+#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1)
+#define FSMC_PCR_PBKEN ((uint32_t)1 << 2)
+#define FSMC_PCR_PTYP ((uint32_t)1 << 3)
+#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4)
+#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4)
+#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4)
+#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4)
+#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4)
+#define FSMC_PCR_ECCEN ((uint32_t)1 << 6)
+#define FSMC_PCR_PTYP_PCCARD 0
+#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP
+
+/**
+ * @brief SR register
+ */
+#define FSMC_SR_IRS ((uint8_t)0x01)
+#define FSMC_SR_ILS ((uint8_t)0x02)
+#define FSMC_SR_IFS ((uint8_t)0x04)
+#define FSMC_SR_IREN ((uint8_t)0x08)
+#define FSMC_SR_ILEN ((uint8_t)0x10)
+#define FSMC_SR_IFEN ((uint8_t)0x20)
+#define FSMC_SR_FEMPT ((uint8_t)0x40)
+#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
+
+/**
+ * @brief BCR register
+ */
+#define FSMC_BCR_MBKEN ((uint32_t)1 << 0)
+#define FSMC_BCR_MUXEN ((uint32_t)1 << 1)
+#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2)
+#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2)
+#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2)
+#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2)
+#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4)
+#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F7))
+#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
+#else
+#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
+#endif
+#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4)
+#define FSMC_BCR_FACCEN ((uint32_t)1 << 6)
+#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8)
+#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9)
+#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10)
+#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11)
+#define FSMC_BCR_WREN ((uint32_t)1 << 12)
+#define FSMC_BCR_WAITEN ((uint32_t)1 << 13)
+#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14)
+#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15)
+#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F7))
+#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
+#endif
+#if (defined(STM32F7))
+#define FSMC_BCR_WFDIS ((uint32_t)1 << 21)
+#endif
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief FSMC driver enable switch.
+ * @details If set to @p TRUE the support for FSMC is included.
+ */
+#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__)
+#define STM32_FSMC_USE_FSMC1 FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+#if !STM32_FSMC_USE_FSMC1
+#error "FSMC driver activated but no FSMC peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an FSMC driver.
+ */
+typedef struct FSMCDriver FSMCDriver;
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ FSMC_UNINIT = 0, /**< Not initialized. */
+ FSMC_STOP = 1, /**< Stopped. */
+ FSMC_READY = 2, /**< Ready. */
+} fsmcstate_t;
+
+/**
+ * @brief Structure representing an FSMC driver.
+ */
+struct FSMCDriver {
+ /**
+ * @brief Driver state.
+ */
+ fsmcstate_t state;
+ /* End of the mandatory fields.*/
+
+#if HAL_USE_SRAM
+ #if STM32_SRAM_USE_SRAM1
+ FSMC_SRAM_TypeDef *sram1;
+ #endif
+ #if STM32_SRAM_USE_SRAM2
+ FSMC_SRAM_TypeDef *sram2;
+ #endif
+ #if STM32_SRAM_USE_SRAM3
+ FSMC_SRAM_TypeDef *sram3;
+ #endif
+ #if STM32_SRAM_USE_SRAM4
+ FSMC_SRAM_TypeDef *sram4;
+ #endif
+#endif
+
+#if HAL_USE_NAND
+ #if STM32_NAND_USE_NAND1
+ FSMC_NAND_TypeDef *nand1;
+ #endif
+ #if STM32_NAND_USE_NAND1
+ FSMC_NAND_TypeDef *nand2;
+ #endif
+#endif
+
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F7))
+ #if HAL_USE_SDRAM
+ FSMC_SDRAM_TypeDef *sdram;
+ #endif
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__)
+extern FSMCDriver FSMCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void fsmcInit(void);
+ void fsmcStart(FSMCDriver *fsmcp);
+ void fsmcStop(FSMCDriver *fsmcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_FSMC */
+
+#endif /* HAL_FSMC_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h
index f907152..0c95e89 100644
--- a/os/hal/include/hal_nand.h
+++ b/os/hal/include/hal_nand.h
@@ -51,6 +51,7 @@
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+
/**
* @brief Enables the mutual exclusion APIs on the NAND.
*/
diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h
new file mode 100644
index 0000000..eaca0fb
--- /dev/null
+++ b/os/hal/include/hal_sdram.h
@@ -0,0 +1,244 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ SDRAM routines added by Nick Klimov aka progfin.
+ */
+
+/**
+ * @file hal_sdram.h
+ * @brief SDRAM Driver subsystem low level driver header.
+ *
+ * @addtogroup SDRAM
+ * @{
+ */
+
+#ifndef HAL_SDRAM_H_
+#define HAL_SDRAM_H_
+
+#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * FMC SDRAM Mode definition register defines
+ */
+#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
+/*
+ * FMC_ReadPipe_Delay
+ */
+#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
+
+/*
+ * FMC_Read_Burst
+ */
+#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
+
+/*
+ * FMC_SDClock_Period
+ */
+#define FMC_SDClock_Disable ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
+#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
+
+/*
+ * FMC_ColumnBits_Number
+ */
+#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
+
+/*
+ * FMC_RowBits_Number
+ */
+#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
+
+/*
+ * FMC_SDMemory_Data_Width
+ */
+#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
+
+/*
+ * FMC_InternalBank_Number
+ */
+#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
+
+/*
+ * FMC_CAS_Latency
+ */
+#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
+
+/*
+ * FMC_Write_Protection
+ */
+#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief SDRAM driver enable switch.
+ * @details If set to @p TRUE the support for SDRAM1 is included.
+ */
+#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__)
+#define STM32_SDRAM_USE_SDRAM1 FALSE
+#else
+#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
+#endif
+
+/**
+ * @brief SDRAM driver enable switch.
+ * @details If set to @p TRUE the support for SDRAM2 is included.
+ */
+#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__)
+#define STM32_SDRAM_USE_SDRAM2 FALSE
+#else
+#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2
+#error "SDRAM driver activated but no SDRAM peripheral assigned"
+#endif
+
+#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC
+#error "FMC not present in the selected device"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ SDRAM_UNINIT = 0, /**< Not initialized. */
+ SDRAM_STOP = 1, /**< Stopped. */
+ SDRAM_READY = 2, /**< Ready. */
+} sdramstate_t;
+
+/**
+ * @brief Type of a structure representing an SDRAM driver.
+ */
+typedef struct SDRAMDriver SDRAMDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief SDRAM control register.
+ * @note Its value will be used for both banks.
+ */
+ uint32_t sdcr;
+
+ /**
+ * @brief SDRAM timing register.
+ * @note Its value will be used for both banks.
+ */
+ uint32_t sdtr;
+
+ /**
+ * @brief SDRAM command mode register.
+ * @note Only its MRD and NRFS bits will be used.
+ */
+ uint32_t sdcmr;
+
+ /**
+ * @brief SDRAM refresh timer register.
+ * @note Only its COUNT bits will be used.
+ */
+ uint32_t sdrtr;
+} SDRAMConfig;
+
+/**
+ * @brief Structure representing an SDRAM driver.
+ */
+struct SDRAMDriver {
+ /**
+ * @brief Driver state.
+ */
+ sdramstate_t state;
+ /**
+ * @brief Pointer to the FMC SDRAM registers block.
+ */
+ FSMC_SDRAM_TypeDef *sdram;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern SDRAMDriver SDRAMD1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sdramInit(void);
+ void sdramObjectInit(SDRAMDriver *sdramp);
+ void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
+ void sdramStop(SDRAMDriver *sdramp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDRAM */
+
+#endif /* HAL_SDRAM_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_sram.h b/os/hal/include/hal_sram.h
new file mode 100644
index 0000000..bcf362a
--- /dev/null
+++ b/os/hal/include/hal_sram.h
@@ -0,0 +1,171 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_fsmc_sram.h
+ * @brief SRAM Driver subsystem low level driver header.
+ *
+ * @addtogroup SRAM
+ * @{
+ */
+
+#ifndef HAL_SRAM_H_
+#define HAL_SRAM_H_
+
+#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM1 is included.
+ */
+#if !defined(STM32_SRAM_USE_SRAM1) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_SRAM1 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM2 is included.
+ */
+#if !defined(STM32_SRAM_USE_SRAM2) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_SRAM2 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM3 is included.
+ */
+#if !defined(STM32_SRAM_USE_SRAM3) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_SRAM3 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM4 is included.
+ */
+#if !defined(STM32_SRAM_USE_SRAM4) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_SRAM4 FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !STM32_SRAM_USE_SRAM1 && !STM32_SRAM_USE_SRAM2 && \
+ !STM32_SRAM_USE_SRAM3 && !STM32_SRAM_USE_SRAM4
+#error "SRAM driver activated but no SRAM peripheral assigned"
+#endif
+
+#if (STM32_SRAM_USE_SRAM1 || STM32_SRAM_USE_SRAM2 || \
+ STM32_SRAM_USE_SRAM3 || STM32_SRAM_USE_SRAM4) && !STM32_HAS_FSMC
+#error "FSMC not present in the selected device"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ SRAM_UNINIT = 0, /**< Not initialized. */
+ SRAM_STOP = 1, /**< Stopped. */
+ SRAM_READY = 2, /**< Ready. */
+} sramstate_t;
+
+/**
+ * @brief Type of a structure representing an NAND driver.
+ */
+typedef struct SRAMDriver SRAMDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ * @note Some bits in BCR register will be forced by driver.
+ */
+typedef struct {
+ uint32_t bcr;
+ uint32_t btr;
+ uint32_t bwtr;
+} SRAMConfig;
+
+/**
+ * @brief Structure representing an NAND driver.
+ */
+struct SRAMDriver {
+ /**
+ * @brief Driver state.
+ */
+ sramstate_t state;
+ /**
+ * @brief Pointer to the FSMC SRAM registers block.
+ */
+ FSMC_SRAM_TypeDef *sram;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD1;
+#endif
+
+#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD2;
+#endif
+
+#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD3;
+#endif
+
+#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sramInit(void);
+ void sramObjectInit(SRAMDriver *sdramp);
+ void sramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
+ void sramStop(SRAMDriver *sramp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SRAM */
+
+#endif /* HAL_SRAM_H_ */
+
+/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 06:54:30 +0000