diff options
Diffstat (limited to 'os/hal/include')
| -rw-r--r-- | os/hal/include/fsmc/nand.h | 293 | ||||
| -rw-r--r-- | os/hal/include/fsmc/sdram.h | 173 | ||||
| -rw-r--r-- | os/hal/include/fsmc/sram.h | 170 | ||||
| -rw-r--r-- | os/hal/include/hal_community.h | 5 | ||||
| -rw-r--r-- | os/hal/include/hal_fsmc.h | 400 |
5 files changed, 1041 insertions, 0 deletions
diff --git a/os/hal/include/fsmc/nand.h b/os/hal/include/fsmc/nand.h new file mode 100644 index 0000000..b2d9001 --- /dev/null +++ b/os/hal/include/fsmc/nand.h @@ -0,0 +1,293 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_nand_lld.h + * @brief NAND Driver subsystem low level driver header. + * + * @addtogroup NAND + * @{ + */ + +#ifndef NAND_H_ +#define NAND_H_ + +#include "bitmap.h" + +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC1 interrupt priority level setting. + */ +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. + */ +#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND1 FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. + */ +#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND2 FALSE +#endif + +/** + * @brief NAND DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +/** + * @brief NAND interrupt enable switch. + * @details If set to @p TRUE the support for internal FSMC interrupt included. + */ +#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_NAND_USE_INT FALSE +#endif + +/** +* @brief NAND1 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND1_DMA_PRIORITY 0 +#endif + +/** +* @brief NAND2 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND2_DMA_PRIORITY 0 +#endif + +/** + * @brief DMA stream used for NAND operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct NANDDriver NANDDriver; + +/** + * @brief Type of interrupt handler function. + */ +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Number of erase blocks in NAND device. + */ + uint32_t blocks; + /** + * @brief Number of data bytes in page. + */ + uint32_t page_data_size; + /** + * @brief Number of spare bytes in page. + */ + uint32_t page_spare_size; + /** + * @brief Number of pages in block. + */ + uint32_t pages_per_block; + /** + * @brief Number of write cycles for row addressing. + */ + uint8_t rowcycles; + /** + * @brief Number of write cycles for column addressing. + */ + uint8_t colcycles; + + /* End of the mandatory fields.*/ + /** + * @brief Number of wait cycles. This value will be used both for + * PMEM and PATTR registers + * + * @note For proper calculation procedure please look at AN2784 document + * from STMicroelectronics. + */ + uint32_t pmem; +} NANDConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct NANDDriver { + /** + * @brief Driver state. + */ + nandstate_t state; + /** + * @brief Current configuration data. + */ + const NANDConfig *config; + /** + * @brief Array to store bad block map. + */ +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif /* NAND_USE_MUTUAL_EXCLUSION */ + /* End of the mandatory fields.*/ + /** + * @brief Function enabling interrupts from FSMC. + */ + nandisrhandler_t isr_handler; + /** + * @brief Pointer to current transaction buffer. + */ + void *rxdata; + /** + * @brief Current transaction length in bytes. + */ + size_t datalen; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Thread waiting for I/O completion. + */ + thread_t *thread; + /** + * @brief Pointer to the FSMC NAND registers block. + */ + FSMC_NAND_TypeDef *nand; + /** + * @brief Memory mapping for data. + */ + uint16_t *map_data; + /** + * @brief Memory mapping for commands. + */ + uint16_t *map_cmd; + /** + * @brief Memory mapping for addresses. + */ + uint16_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; +#endif + +#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_NAND */ + +#endif /* NAND_H_ */ + +/** @} */ diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h new file mode 100644 index 0000000..83b78a6 --- /dev/null +++ b/os/hal/include/fsmc/sdram.h @@ -0,0 +1,173 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef SDRAM_H_ +#define SDRAM_H_ + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDRAM_UNINIT = 0, /**< Not initialized. */ + SDRAM_STOP = 1, /**< Stopped. */ + SDRAM_READY = 2, /**< Ready. */ +} sdramstate_t; + +/** + * @brief Type of a structure representing an SDRAM driver. + */ +typedef struct SDRAMDriver SDRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief SDRAM control register. + * @note Its value will be used for both banks. + */ + uint32_t sdcr; + + /** + * @brief SDRAM timing register. + * @note Its value will be used for both banks. + */ + uint32_t sdtr; + + /** + * @brief SDRAM command mode register. + * @note Only its MRD and NRFS bits will be used. + */ + uint32_t sdcmr; + + /** + * @brief SDRAM refresh timer register. + * @note Only its COUNT bits will be used. + */ + uint32_t sdrtr; +} SDRAMConfig; + +/** + * @brief Structure representing an SDRAM driver. + */ +struct SDRAMDriver { + /** + * @brief Driver state. + */ + sdramstate_t state; + /** + * @brief Pointer to the FMC SDRAM registers block. + */ + FSMC_SDRAM_TypeDef *sdram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD; + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSdramInit(void); + void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void fsmcSdramStop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +#endif /* SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h new file mode 100644 index 0000000..6eed97a --- /dev/null +++ b/os/hal/include/fsmc/sram.h @@ -0,0 +1,170 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef SRAM_H_ +#define SRAM_H_ + +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM1 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM2 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM3 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM4 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ + !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ + STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SRAM_UNINIT = 0, /**< Not initialized. */ + SRAM_STOP = 1, /**< Stopped. */ + SRAM_READY = 2, /**< Ready. */ +} sramstate_t; + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct SRAMDriver SRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + * @note Some bits in BCR register will be forced by driver. + */ +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct SRAMDriver { + /** + * @brief Driver state. + */ + sramstate_t state; + /** + * @brief Pointer to the FSMC SRAM registers block. + */ + FSMC_SRAM_NOR_TypeDef *sram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSramInit(void); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_SRAM */ + +#endif /* SRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index f84e90a..ad5c472 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -79,6 +79,10 @@ #define HAL_USE_OPAMP FALSE
#endif
+#if !defined(HAL_USE_FSMC)
+#define HAL_USE_FSMC FALSE
+#endif
+
/* Abstract interfaces.*/
/* Shared headers.*/
@@ -99,6 +103,7 @@ #include "hal_eeprom.h"
#include "hal_usb_hid.h"
#include "hal_usb_msd.h"
+#include "hal_fsmc.h"
/*===========================================================================*/
/* Driver constants. */
diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h new file mode 100644 index 0000000..f85079a --- /dev/null +++ b/os/hal/include/hal_fsmc.h @@ -0,0 +1,400 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc.h + * @brief FSMC Driver subsystem low level driver header. + * + * @addtogroup FSMC + * @{ + */ + +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ + +#include "hal.h" + +#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * (Re)define if needed base address constants supplied in ST's CMSIS + */ +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) + #endif + #if !defined(FSMC_Bank5_R_BASE) + #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + #endif +#else + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + #endif +#endif + +/* + * Base bank mappings + */ +#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) +#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) +#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) +#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) + #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#endif + +/* + * Subbunks of bank1 + */ +#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) +#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) +#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) + +/* + * Bank 2 (NAND) + */ +#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) +#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) + +#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) +#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) +#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) + +#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) +#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) +#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) + +/* + * Bank 3 (NAND) + */ +#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) +#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) + +#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) +#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) +#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) + +#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) +#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) +#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) + +/* + * Bank 4 (PC card) + */ +#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) +#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) +#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) + +/* + * More convenient typedefs than CMSIS has + */ +typedef struct { + __IO uint32_t PCR; /**< NAND Flash control */ + __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ + __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ + __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ + uint32_t RESERVED0; /**< Reserved, 0x70 */ + __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ +} FSMC_NAND_TypeDef; + +typedef struct { + __IO uint32_t PCR; /**< PC Card control */ + __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ + __IO uint32_t PMEM; /**< PC Card Common memory space timing */ + __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ + __IO uint32_t PIO; /**< PC Card I/O space timing */ +} FSMC_PCCard_TypeDef; + +typedef struct { + __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ + __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ + uint32_t RESERVED[63]; /**< Reserved */ + __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ +} FSMC_SRAM_NOR_TypeDef; + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + +typedef struct { + __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ + __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ + __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ + __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ + __IO uint32_t SDCMR; /**< SDRAM comand mode register */ + __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ + __IO uint32_t SDSR; /**< SDRAM status register */ +} FSMC_SDRAM_TypeDef; + +#endif + +/** + * @brief PCR register + */ +#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) +#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) +#define FSMC_PCR_PTYP ((uint32_t)1 << 3) +#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) +#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) +#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) +#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) +#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) +#define FSMC_PCR_PTYP_PCCARD 0 +#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP + +/** + * @brief SR register + */ +#define FSMC_SR_IRS ((uint8_t)0x01) +#define FSMC_SR_ILS ((uint8_t)0x02) +#define FSMC_SR_IFS ((uint8_t)0x04) +#define FSMC_SR_IREN ((uint8_t)0x08) +#define FSMC_SR_ILEN ((uint8_t)0x10) +#define FSMC_SR_IFEN ((uint8_t)0x20) +#define FSMC_SR_FEMPT ((uint8_t)0x40) +#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) + +/** + * @brief BCR register + */ +#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) +#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) +#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) +#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) +#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) +#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) +#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) +#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) +#else +#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) +#endif +#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) +#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) +#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) +#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) +#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) +#define FSMC_BCR_WREN ((uint32_t)1 << 12) +#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) +#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) +#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) +#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) +#endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC driver enable switch. + * @details If set to @p TRUE the support for FSMC is included. + */ +#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_FSMC1 FALSE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM is included. + */ +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM is included. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND is included. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE +#endif + + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#if !STM32_FSMC_USE_FSMC1 +#error "FSMC driver activated but no FSMC peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an FSMC driver. + */ +typedef struct FSMCDriver FSMCDriver; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + FSMC_UNINIT = 0, /**< Not initialized. */ + FSMC_STOP = 1, /**< Stopped. */ + FSMC_READY = 2, /**< Ready. */ +} fsmcstate_t; + +/** + * @brief Structure representing an FSMC driver. + */ +struct FSMCDriver { + /** + * @brief Driver state. + */ + fsmcstate_t state; + /* End of the mandatory fields.*/ + +#if HAL_USE_FSMC_SRAM + #if STM32_SRAM_USE_FSMC_SRAM1 + FSMC_SRAM_NOR_TypeDef *sram1; + #endif + #if STM32_SRAM_USE_FSMC_SRAM2 + FSMC_SRAM_NOR_TypeDef *sram2; + #endif + #if STM32_SRAM_USE_FSMC_SRAM3 + FSMC_SRAM_NOR_TypeDef *sram3; + #endif + #if STM32_SRAM_USE_FSMC_SRAM4 + FSMC_SRAM_NOR_TypeDef *sram4; + #endif +#endif + +#if HAL_USE_FSMC_NAND + #if STM32_NAND_USE_FSMC_NAND1 + FSMC_NAND_TypeDef *nand1; + #endif + #if STM32_NAND_USE_FSMC_NAND2 + FSMC_NAND_TypeDef *nand2; + #endif +#endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + #if HAL_USE_FSMC_SDRAM + FSMC_SDRAM_TypeDef *sdram; + #endif +#endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) +extern FSMCDriver FSMCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcInit(void); + void fsmcStart(FSMCDriver *fsmcp); + void fsmcStop(FSMCDriver *fsmcp); +#ifdef __cplusplus +} +#endif + +#if HAL_USE_FSMC_SDRAM == TRUE +#include "fsmc/sdram.h" +#endif + +#if HAL_USE_FSMC_SRAM == TRUE +#include "fsmc/sram.h" +#endif + +#if HAL_USE_FSMC_NAND == TRUE +#include "fsmc/nand.h" +#endif + +#endif /* HAL_USE_FSMC */ + +#endif /* HAL_FSMC_H_ */ + +/** @} */ |