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-rw-r--r--os/hal/hal.mk3
-rw-r--r--os/hal/include/crc.h158
-rw-r--r--os/hal/include/hal_community.h1
-rw-r--r--os/hal/ports/STM32/LLD/CRCv1/crc_lld.c328
-rw-r--r--os/hal/ports/STM32/LLD/CRCv1/crc_lld.h249
-rw-r--r--os/hal/ports/STM32/STM32F0xx/platform.mk6
-rw-r--r--os/hal/src/crc.c263
-rw-r--r--os/hal/src/hal_community.c4
-rw-r--r--os/various/crcsw.c338
-rw-r--r--os/various/crcsw.h215
-rw-r--r--testhal/STM32/STM32F0xx/crc/Makefile212
-rw-r--r--testhal/STM32/STM32F0xx/crc/chconf.h499
-rw-r--r--testhal/STM32/STM32F0xx/crc/halconf.h340
-rw-r--r--testhal/STM32/STM32F0xx/crc/halconf_community.h104
-rw-r--r--testhal/STM32/STM32F0xx/crc/main.c244
-rw-r--r--testhal/STM32/STM32F0xx/crc/mcuconf.h166
-rw-r--r--testhal/STM32/STM32F0xx/crc/mcuconf_community.h33
-rw-r--r--testhal/STM32/STM32F0xx/crc/readme.txt36
18 files changed, 3198 insertions, 1 deletions
diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index 51cda56..c193ef4 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -3,6 +3,7 @@ include ${CHIBIOS}/os/hal/hal.mk
HALSRC += ${CHIBIOS}/community/os/hal/src/hal_community.c \
${CHIBIOS}/community/os/hal/src/nand.c \
${CHIBIOS}/community/os/hal/src/onewire.c \
- ${CHIBIOS}/community/os/hal/src/eicu.c
+ ${CHIBIOS}/community/os/hal/src/eicu.c \
+ ${CHIBIOS}/community/os/hal/src/crc.c
HALINC += ${CHIBIOS}/community/os/hal/include
diff --git a/os/hal/include/crc.h b/os/hal/include/crc.h
new file mode 100644
index 0000000..baa274b
--- /dev/null
+++ b/os/hal/include/crc.h
@@ -0,0 +1,158 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _CRC_H_
+#define _CRC_H_
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief Enable DMA CRC
+ * @note Enables DMA when doing CRC calculations. This may be less
+ * efficient with smaller CRC calculations.
+ */
+#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__)
+#define CRC_USE_DMA FALSE
+#endif
+
+/**
+ * @brief Enables the @p crcAcquireBus() and @p crcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define CRC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_CRC_USE_CRC1 != TRUE && CRCSW_USE_CRC1 != TRUE
+#error "CRC requires at least one LLD driver."
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ CRC_UNINIT, /* Not initialized. */
+ CRC_STOP, /* Stopped. */
+ CRC_READY, /* Ready. */
+ CRC_ACTIVE, /* Calculating CRC. */
+ CRC_COMPLETE /* Asynchronous operation complete. */
+} crcstate_t;
+
+#include "crc_lld.h" /* Include software LL driver */
+#include "crcsw.h"
+
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Low level driver helper macros
+ * @{
+ */
+
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+#define _crc_wakeup_isr(crcp) { \
+ osalSysLockFromISR(); \
+ osalThreadResumeI(&(crcp)->thread, MSG_OK); \
+ osalSysUnlockFromISR(); \
+}
+
+/**
+ * @brief Common ISR code.
+ * @details This code handles the portable part of the ISR code:
+ * - Callback invocation.
+ * - Waiting thread wakeup, if any.
+ * - Driver state transitions.
+ * .
+ * @note This macro is meant to be used in the low level drivers
+ * implementation only.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+#define _crc_isr_code(crcp, crc) { \
+ if ((crcp)->config->end_cb) { \
+ (crcp)->state = CRC_COMPLETE; \
+ (crcp)->config->end_cb(crcp, crc); \
+ if ((crcp)->state == CRC_COMPLETE) \
+ (crcp)->state = CRC_READY; \
+ } \
+ else \
+ (crcp)->state = CRC_READY; \
+ _crc_wakeup_isr(crcp); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void crcInit(void);
+ void crcObjectInit(CRCDriver *crcp);
+ void crcStart(CRCDriver *crcp, const CRCConfig *config);
+ void crcStop(CRCDriver *crcp);
+ void crcReset(CRCDriver *crcp);
+ void crcResetI(CRCDriver *crcp);
+ uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf);
+ uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf);
+#if CRC_USE_DMA == TRUE
+ void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf);
+ void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf);
+#endif
+#if CRC_USE_MUTUAL_EXCLUSION == TRUE
+ void crcAcquireUnit(CRCDriver *crcp);
+ void crcReleaseUnit(CRCDriver *crcp);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_CRC */
+
+#endif /* _CRC_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index 6cd6b66..426fadd 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -35,6 +35,7 @@
/* Complex drivers.*/
#include "onewire.h"
+#include "crc.h"
/*===========================================================================*/
/* Driver constants. */
diff --git a/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c
new file mode 100644
index 0000000..4bcb771
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c
@@ -0,0 +1,328 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32/CRCv1/crc_lld.c
+ * @brief STM32 CRC subsystem low level driver source.
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+/**
+ * Allow CRC Software override for ST drivers. Some ST CRC implimentations
+ * have limited capabilities.
+ */
+#if CRCSW_USE_CRC1 != TRUE
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/**
+ * @brief CRC default configuration.
+ */
+static const CRCConfig default_config = {
+ .poly_size = 32,
+ .poly = 0x04C11DB7,
+ .initial_val = 0xFFFFFFFF,
+ .final_val = 0xFFFFFFFF,
+ .reflect_data = 1,
+ .reflect_remainder = 1
+};
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief CRC1 driver identifier.*/
+#if STM32_CRC_USE_CRC1 || defined(__DOXYGEN__)
+CRCDriver CRCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void _crc_lld_calc_byte(CRCDriver *crcp, uint8_t data) {
+ __IO uint8_t *crc8 = (__IO uint8_t*)&(crcp->crc->DR);
+ *crc8 = data;
+}
+
+/*
+ * @brief Returns calculated CRC from last reset
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] data data to be added to crc
+ *
+ * @notapi
+ */
+void _crc_lld_calc_halfword(CRCDriver *crcp, uint16_t data) {
+ __IO uint16_t *crc16 = (__IO uint16_t*)&(crcp->crc->DR);
+ *crc16 = data;
+}
+
+/*
+ * @brief Returns calculated CRC from last reset
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] data data to be added to crc
+ *
+ * @notapi
+ */
+void _crc_lld_calc_word(CRCDriver *crcp, uint32_t data) {
+ crcp->crc->DR = data;
+}
+
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief Shared end-of-rx service routine.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+#if CRC_USE_DMA == TRUE
+static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) {
+
+ /* DMA errors handling.*/
+#if defined(STM32_CRC_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_CRC_DMA_ERROR_HOOK(crcp);
+ }
+#else
+ (void)flags;
+#endif
+
+ /* Stop everything.*/
+ dmaStreamDisable(crcp->dma);
+
+ /* Portable CRC ISR code defined in the high level driver, note, it is
+ a macro.*/
+ _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val);
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level CRC driver initialization.
+ *
+ * @notapi
+ */
+void crc_lld_init(void) {
+ crcObjectInit(&CRCD1);
+ CRCD1.crc = CRC;
+#if CRC_USE_DMA == TRUE
+ CRCD1.dma = STM32_CRC_CRC1_DMA_STREAM;
+#endif
+}
+
+/**
+ * @brief Configures and activates the CRC peripheral.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_start(CRCDriver *crcp) {
+ if (crcp->config == NULL)
+ crcp->config = &default_config;
+
+ rccEnableCRC(FALSE);
+
+#if STM32_CRC_PROGRAMMABLE == TRUE
+ crcp->crc->INIT = crcp->config->initial_val;
+ crcp->crc->POL = crcp->config->poly;
+
+ crcp->crc->CR = 0;
+ switch(crcp->config->poly_size) {
+ case 32:
+ break;
+ case 16:
+ crcp->crc->CR |= CRC_CR_POLYSIZE_0;
+ break;
+ case 8:
+ crcp->crc->CR |= CRC_CR_POLYSIZE_1;
+ break;
+ case 7:
+ crcp->crc->CR |= CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0;
+ break;
+ default:
+ osalDbgAssert(false, "hardware doesn't support polynomial size");
+ break;
+ };
+ if (crcp->config->reflect_data) {
+ crcp->crc->CR |= CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0;
+ }
+ if (crcp->config->reflect_remainder) {
+ crcp->crc->CR |= CRC_CR_REV_OUT;
+ }
+#else
+ osalDbgAssert(crcp->config->initial_val != default_config.initial_val,
+ "hardware doesn't support programmable initial value");
+ osalDbgAssert(crcp->config->poly_size != default_config.poly_size,
+ "hardware doesn't support programmable polynomial size");
+ osalDbgAssert(crcp->config->poly != default_config.poly,
+ "hardware doesn't support programmable polynomial");
+ osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data,
+ "hardware doesn't support reflect of input data");
+ osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder,
+ "hardware doesn't support reflect of output remainder");
+#endif
+
+#if CRC_USE_DMA == TRUE
+#if STM32_CRC_PROGRAMMABLE == TRUE
+ crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC |
+ STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY);
+#else
+ crcp->dmamode = STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_PINC |
+ STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD |
+ STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_PL(STM32_CRC_CRC1_DMA_PRIORITY);
+#endif
+ {
+ bool b;
+ b = dmaStreamAllocate(crcp->dma,
+ STM32_CRC_CRC1_DMA_IRQ_PRIORITY,
+ (stm32_dmaisr_t)crc_lld_serve_interrupt,
+ (void *)crcp);
+ osalDbgAssert(!b, "stream already allocated");
+ }
+#endif
+}
+
+
+/**
+ * @brief Deactivates the CRC peripheral.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_stop(CRCDriver *crcp) {
+#if CRC_USE_DMA == TRUE
+ dmaStreamRelease(crcp->dma);
+#else
+ (void)crcp;
+#endif
+ rccDisableCRC(FALSE);
+}
+
+/**
+ * @brief Resets current CRC calculation.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_reset(CRCDriver *crcp) {
+ crcp->crc->CR |= CRC_CR_RESET;
+}
+
+/**
+ * @brief Returns calculated CRC from last reset
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n size of buf in bytes
+ * @param[in] buf @p buffer location
+ *
+ * @notapi
+ */
+uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
+#if CRC_USE_DMA == TRUE
+ crc_lld_start_calc(crcp, n, buf);
+ (void) osalThreadSuspendS(&crcp->thread);
+#else
+ /**
+ * BUG: Only peform byte writes to DR reg if reflect_data is disabled.
+ * The STM32 hardware unit seems to incorrectly calculate CRCs when all
+ * of the following is true: reflect_data(rev_in) is 0, dma is disable, and
+ * you are writing more than a byte into the DR register.
+ */
+ if (crcp->config->reflect_data != 0) {
+ while(n > 3) {
+ _crc_lld_calc_word(crcp, *(uint32_t*)buf);
+ buf+=4;
+ n-=4;
+ }
+ }
+
+#if STM32_CRC_PROGRAMMABLE == TRUE
+ /* Programmable CRC units allow variable register width accesses.*/
+
+ /**
+ * BUG: Only peform byte writes to DR reg if reflect_data is disabled.
+ * The STM32 hardware unit seems to incorrectly calculate CRCs when all
+ * of the following is true: reflect_data(rev_in) is 0, dma is disable, and
+ * you are writing more than a byte into the DR register.
+ */
+ if (crcp->config->reflect_data != 0) {
+ while(n > 1) {
+ _crc_lld_calc_halfword(crcp, *(uint16_t*)buf);
+ buf+=2;
+ n-=2;
+ }
+ }
+
+ while(n > 0) {
+ _crc_lld_calc_byte(crcp, *(uint8_t*)buf);
+ buf++;
+ n--;
+ }
+#else
+ osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses");
+#endif
+
+#endif
+ return crcp->crc->DR ^ crcp->config->final_val;
+}
+
+#if CRC_USE_DMA == TRUE
+void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) {
+ dmaStreamSetPeripheral(crcp->dma, buf);
+ dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR);
+#if STM32_CRC_PROGRAMMABLE == TRUE
+ dmaStreamSetTransactionSize(crcp->dma, n);
+#else
+ dmaStreamSetTransactionSize(crcp->dma, (n / 4));
+#endif
+ dmaStreamSetMode(crcp->dma, crcp->dmamode);
+
+ dmaStreamEnable(crcp->dma);
+}
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h
new file mode 100644
index 0000000..6f70b42
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h
@@ -0,0 +1,249 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32/CRCv1/crc_lld.h
+ * @brief STM32 CRC subsystem low level driver header.
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#ifndef _CRC_LLD_H_
+#define _CRC_LLD_H_
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+/*
+ * This error check must occur outsite of CRCSW_USE_CRC1 to check if
+ * two LLD drivers are enabled at the same time
+ */
+#if STM32_CRC_USE_CRC1 == TRUE && \
+ CRCSW_USE_CRC1 == TRUE
+#error "Software CRC can't be enable with STM32_CRC_USE_CRC1"
+#endif
+
+/**
+ * Allow CRC Software override for ST drivers. Some ST CRC implimentations
+ * have limited capabilities.
+ */
+#if CRCSW_USE_CRC1 != TRUE
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief CRC1 driver enable switch.
+ * @details If set to @p TRUE the support for CRC1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(STM32_CRC_USE_CRC1) || defined(__DOXYGEN__)
+#define STM32_CRC_USE_CRC1 FALSE
+#endif
+
+/**
+ * @brief CRC1 DMA priority (0..3|lowest..highest).
+ * @note The priority level is for CRC DMA stream.
+ */
+#if !defined(STM32_CRC_CRC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_CRC_CRC1_DMA_PRIORITY 2
+#endif
+
+/**
+ * @brief CRC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_CRC_CRC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
+#endif
+
+/**
+ * @brief CRC1 DMA STREAM to use when performing CRC calculation.
+ */
+#if !defined(STM32_CRC_CRC1_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
+#endif
+
+/**
+ * @brief CRC DMA error hook.
+ */
+#if !defined(STM32_CRC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_CRC_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_CRC_USE_CRC1 && !STM32_HAS_CRC
+#error "Hardware CRC not present in the selected device"
+#error "Use CRCSW_USE_CRC1 for software implementation"
+#endif
+
+#if CRC_USE_DMA
+#if STM32_CRC_USE_CRC1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to CRC1"
+#endif
+
+#if STM32_CRC_USE_CRC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_CRC_CRC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to CRC1"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an CRC driver.
+ */
+typedef struct CRCDriver CRCDriver;
+
+/**
+ * @brief CRC notification callback type
+ *
+ * @param[in] crcp pointer to the @ CRCDriver object triggering the
+ * callback
+ */
+typedef void (*crccallback_t)(CRCDriver *crcp, uint32_t crc);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief The size of polynomial to be used for CRC.
+ */
+ uint32_t poly_size;
+ /**
+ * @brief The coefficients of the polynomial to be used for CRC.
+ */
+ uint32_t poly;
+ /**
+ * @brief The inital value
+ */
+ uint32_t initial_val;
+ /**
+ * @brief The final XOR value
+ */
+ uint32_t final_val;
+ /**
+ * @brief Reflect bit order data going into CRC
+ */
+ bool reflect_data;
+ /**
+ * @brief Reflect bit order of final remainder
+ */
+ bool reflect_remainder;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Operation complete callback or @p NULL
+ */
+ crccallback_t end_cb;
+} CRCConfig;
+
+
+/**
+ * @brief Structure representing an CRC driver.
+ */
+struct CRCDriver {
+ /**
+ * @brief Driver state.
+ */
+ crcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const CRCConfig *config;
+#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* CRC_USE_MUTUAL_EXCLUSION */
+#if defined(CRC_DRIVER_EXT_FIELDS)
+ CRC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the CRCx registers block.
+ */
+ CRC_TypeDef *crc;
+
+#if CRC_USE_DMA == TRUE
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+ /**
+ * @brief CRC DMA stream
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_CRC_USE_CRC1 && !defined(__DOXYGEN__)
+extern CRCDriver CRCD1;
+#endif /* STM32_CRC_USE_CRC1 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void crc_lld_init(void);
+ void crc_lld_start(CRCDriver *crcp);
+ void crc_lld_stop(CRCDriver *crcp);
+ void crc_lld_reset(CRCDriver *crcp);
+ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf);
+#if CRC_USE_DMA
+ void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
+
+#endif /* _CRC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk
new file mode 100644
index 0000000..c1c0650
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -0,0 +1,6 @@
+include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c
+
+PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/CRCv1 \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD
diff --git a/os/hal/src/crc.c b/os/hal/src/crc.c
new file mode 100644
index 0000000..a238d91
--- /dev/null
+++ b/os/hal/src/crc.c
@@ -0,0 +1,263 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * Hardware Abstraction Layer for CRC Unit
+ */
+#include "hal.h"
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief CRC Driver initialization.
+ *
+ * @init
+ */
+void crcInit(void) {
+ crc_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p CRCDriver structure.
+ *
+ * @param[out] crcp Pointer to the @p CRCDriver object
+ *
+ * @init
+ */
+void crcObjectInit(CRCDriver *crcp) {
+ crcp->state = CRC_STOP;
+ crcp->config = NULL;
+#if CRC_USE_DMA == TRUE
+ crcp->thread = NULL;
+#endif
+#if CRC_USE_MUTUAL_EXCLUSION == TRUE
+ osalMutexObjectInit(&crcp->mutex);
+#endif
+#if defined(CRC_DRIVER_EXT_INIT_HOOK)
+ CRC_DRIVER_EXT_INIT_HOOK(crcp);
+#endif
+}
+
+/**
+ * @brief Configures and activates the CRC peripheral.
+ *
+ * @param[in] crcp Pointer to the @p CRCDriver object
+ * @param[in] config Pointer to the @p CRCConfig object
+ * @p NULL if the low level driver implementation
+ * supports a default configuration
+ *
+ * @api
+ */
+void crcStart(CRCDriver *crcp, const CRCConfig *config) {
+ osalDbgCheck(crcp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY),
+ "invalid state");
+ crcp->config = config;
+ crc_lld_start(crcp);
+ crcp->state = CRC_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the CRC peripheral.
+ *
+ * @param[in] crcp Pointer to the @p CRCDriver object
+ *
+ * @api
+ */
+void crcStop(CRCDriver *crcp) {
+ osalDbgCheck(crcp != NULL);
+
+ osalSysLock();
+ osalDbgAssert((crcp->state == CRC_STOP) || (crcp->state == CRC_READY),
+ "invalid state");
+ crc_lld_stop(crcp);
+ crcp->state = CRC_STOP;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Resets the CRC calculation
+ *
+ * @param[in] crcp Pointer to the @p CRCDriver object
+ *
+ * @api
+ */
+void crcReset(CRCDriver *crcp) {
+ osalSysLock();
+ crcResetI(crcp);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Resets the current CRC calculation
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @iclass
+ */
+void crcResetI(CRCDriver *crcp) {
+ osalDbgCheck(crcp != NULL);
+ osalDbgAssert(crcp->state == CRC_READY, "Not ready");
+ crc_lld_reset(crcp);
+}
+
+/**
+ * @brief Performs a CRC calculation.
+ * @details This synchronous function performs a crc calculation operation.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n number of bytes to send
+ * @param[in] buf the pointer to the buffer
+ *
+ * @api
+ */
+uint32_t crcCalc(CRCDriver *crcp, size_t n, const void *buf) {
+ uint32_t crc;
+ osalSysLock();
+ crc = crcCalcI(crcp, n, buf);
+ osalSysUnlock();
+ return crc;
+}
+
+/**
+ * @brief Performs a CRC calculation.
+ * @details This synchronous function performs a crc calcuation operation.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n number of bytes to send
+ * @param[in] buf the pointer to the buffer
+ *
+ * @iclass
+ */
+uint32_t crcCalcI(CRCDriver *crcp, size_t n, const void *buf) {
+ osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL));
+ osalDbgAssert(crcp->state == CRC_READY, "not ready");
+#if CRC_USE_DMA
+ osalDbgAssert(crcp->config->end_cb == NULL, "callback defined");
+ (crcp)->state = CRC_ACTIVE;
+#endif
+ return crc_lld_calc(crcp, n, buf);
+}
+
+#if CRC_USE_DMA == TRUE
+/**
+ * @brief Performs a CRC calculation.
+ * @details This asynchronous function starts a crc calcuation operation.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n number of bytes to send
+ * @param[in] buf the pointer to the buffer
+ *
+ * @api
+ */
+void crcStartCalc(CRCDriver *crcp, size_t n, const void *buf) {
+ osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL));
+ osalSysLock();
+ osalDbgAssert(crcp->state == CRC_READY, "not ready");
+ osalDbgAssert(crcp->config->end_cb != NULL, "callback not defined");
+ crcStartCalcI(crcp, n, buf);
+ osalSysUnlock();
+}
+
+/**
+ * @brief Performs a CRC calculation.
+ * @details This asynchronous function starts a crc calcuation operation.
+ * @pre In order to use this function the driver must have been configured
+ * without callbacks (@p end_cb = @p NULL).
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n number of bytes to send
+ * @param[in] buf the pointer to the buffer
+ *
+ *
+ * @iclass
+ */
+void crcStartCalcI(CRCDriver *crcp, size_t n, const void *buf) {
+ osalDbgCheck((crcp != NULL) && (n > 0U) && (buf != NULL));
+ osalDbgAssert(crcp->state == CRC_READY, "not ready");
+ osalDbgAssert(crcp->config->end_cb != NULL, "callback defined");
+ (crcp)->state = CRC_ACTIVE;
+ crc_lld_start_calc(crcp, n, buf);
+}
+#endif
+
+#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Gains exclusive access to the CRC unit.
+ * @details This function tries to gain ownership to the CRC, if the CRC is
+ * already being used then the invoking thread is queued.
+ * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @api
+ */
+void crcAcquireUnit(CRCDriver *crcp) {
+ osalDbgCheck(crcp != NULL);
+
+ osalMutexLock(&crcp->mutex);
+}
+
+/**
+ * @brief Releases exclusive access to the CRC unit.
+ * @pre In order to use this function the option @p CRC_USE_MUTUAL_EXCLUSION
+ * must be enabled.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @api
+ */
+void crcReleaseUnit(CRCDriver *crcp) {
+ osalDbgCheck(crcp != NULL);
+
+ osalMutexUnlock(&crcp->mutex);
+}
+#endif /* CRC_USE_MUTUAL_EXCLUSION == TRUE */
+
+#endif /* HAL_USE_CRC */
diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c
index 7c71e3f..b9700ba 100644
--- a/os/hal/src/hal_community.c
+++ b/os/hal/src/hal_community.c
@@ -60,6 +60,10 @@ void halCommunityInit(void) {
#if HAL_USE_EICU || defined(__DOXYGEN__)
eicuInit();
#endif
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+ crcInit();
+#endif
}
#endif /* HAL_USE_COMMUNITY */
diff --git a/os/various/crcsw.c b/os/various/crcsw.c
new file mode 100644
index 0000000..0f8f07a
--- /dev/null
+++ b/os/various/crcsw.c
@@ -0,0 +1,338 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crcsw.c
+ * @brief CRC software driver.
+ @note SW implementation was based from:
+ * @note http://www.barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+#if CRCSW_USE_CRC1 || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/**
+ * @brief CRC default configuration.
+ */
+
+#if CRCSW_CRC32_TABLE == TRUE || defined(__DOXYGEN__)
+static const uint32_t crc32_table[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
+ 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+ 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+ 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+ 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
+ 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+ 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+ 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
+ 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
+ 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+ 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+ 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
+ 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
+ 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+ 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+ 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
+ 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+ 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+ 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+ 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
+ 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
+ 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+ 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+ 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+ 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
+ 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+ 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+ 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
+ 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
+ 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+ 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+ 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
+ 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
+ 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+ 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+ 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
+ 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+ 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+ 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+ 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
+ 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
+ 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+ 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+#endif
+
+#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__)
+static const uint32_t crc16_table[256] = {
+ 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+ 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+ 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+ 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+ 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+ 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+ 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+ 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+ 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+ 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+ 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+ 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+ 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+ 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+ 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+ 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+ 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+ 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+ 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+ 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+ 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+ 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+ 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+ 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+ 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+ 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+ 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+ 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+ 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+ 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+ 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+ 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief CRC1 driver identifier.*/
+#if CRCSW_USE_CRC1 || defined(__DOXYGEN__)
+CRCDriver CRCD1;
+#endif
+
+#if CRCSW_CRC32_TABLE || defined(__DOXYGEN__)
+const CRCConfig crcsw_crc32_config = {
+ .poly_size = 32,
+ .poly = 0x04C11DB7,
+ .initial_val = 0xFFFFFFFF,
+ .final_val = 0xFFFFFFFF,
+ .reflect_data = 1,
+ .reflect_remainder = 1,
+ .table = crc32_table
+};
+#endif
+
+#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__)
+const CRCConfig crcsw_crc16_config = {
+ .poly_size = 16,
+ .poly = 0x8005,
+ .initial_val = 0x0,
+ .final_val = 0x0,
+ .reflect_data = 1,
+ .reflect_remainder = 1,
+ .table = crc16_table
+};
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#if (CRCSW_PROGRAMMABLE == TRUE)
+static uint32_t reflect(uint32_t data, uint8_t nBits) {
+ uint32_t reflection = 0x00000000;
+ uint8_t bit;
+
+ /* Reflect the data about the center bit. */
+ for (bit = 0; bit < nBits; ++bit) {
+ /* If the LSB bit is set, set the reflection of it. */
+ if (data & 0x01) {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+
+ data = (data >> 1);
+ }
+
+ return reflection;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level CRC software initialization.
+ *
+ * @notapi
+ */
+void crc_lld_init(void) {
+ crcObjectInit(&CRCD1);
+ CRCD1.crc = CRCD1.config->initial_val;
+}
+
+/**
+ * @brief Configures and activates the CRC peripheral.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_start(CRCDriver *crcp) {
+ osalDbgAssert(crcp->config != NULL, "config must not be NULL");
+
+#if CRCSW_PROGRAMMABLE == FALSE
+#if CRCSW_CRC32_TABLE == TRUE && CRCSW_CRC16_TABLE == TRUE
+ osalDbgAssert((crcp->config == CRCSW_CRC32_TABLE_CONFIG) ||
+ (crcp->config == CRCSW_CRC16_TABLE_CONFIG), "config must be CRCSW_CRC32_TABLE_CONFIG or CRCSW_CRC16_TABLE_CONFIG");
+#elif CRCSW_CRC32_TABLE == TRUE && CRCSW_CRC16_TABLE == FALSE
+ osalDbgAssert(crcp->config == CRCSW_CRC32_TABLE_CONFIG,
+ "config must be CRCSW_CRC32_TABLE_CONFIG");
+#else
+ osalDbgAssert(crcp->config == CRCSW_CRC16_TABLE_CONFIG,
+ "config must be CRCSW_CRC16_TABLE_CONFIG");
+#endif
+#endif
+ crc_lld_reset(crcp);
+}
+
+
+/**
+ * @brief Deactivates the CRC peripheral.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_stop(CRCDriver *crcp) {
+ (void)crcp;
+}
+
+/**
+ * @brief Resets current CRC calculation.
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_reset(CRCDriver *crcp) {
+ crcp->crc = crcp->config->initial_val;
+}
+
+/**
+ * @brief Returns calculated CRC from last reset
+ *
+ * @param[in] crcp pointer to the @p CRCDriver object
+ * @param[in] n size of buf in bytes
+ * @param[in] buf @p buffer location
+ *
+ * @notapi
+ */
+uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
+ uint32_t i;
+ uint32_t crc;
+#if (CRCSW_CRC32_TABLE == TRUE) || (CRCSW_CRC16_TABLE == TRUE)
+ if (crcp->config->table != NULL) {
+ for (i = 0; i < n; i++) {
+ uint8_t data = *((uint8_t*)buf + i);
+ uint8_t idx = (crcp->crc ^ data);
+ crcp->crc = (crcp->config->table[idx] ^ (crcp->crc >> 8));
+ }
+ crc = crcp->crc;
+ }
+#endif
+
+#if (CRCSW_PROGRAMMABLE == TRUE)
+ // Mask off bits to poly size
+ uint32_t mask = 1 << (crcp->config->poly_size - 1);
+ mask |= (mask - 1);
+
+ crc = crcp->crc;
+ if (crcp->config->table == NULL) {
+ for (i = 0; i < n; i++) {
+ uint8_t data = *((uint8_t*)buf + i);
+ uint8_t bit;
+
+ if (crcp->config->reflect_data) {
+ data = reflect(data, 8);
+ }
+
+ /* Bring the next byte into the remainder. */
+ crc ^= (data << (crcp->config->poly_size - 8));
+
+ /* Perform modulo-2 division, a bit at a time. */
+ for (bit = 8; bit > 0; --bit) {
+ /* Try to divide the current data bit. */
+ if (crc & (1 << (crcp->config->poly_size - 1))) {
+ crc = (crc << 1) ^ crcp->config->poly;
+ } else {
+ crc <<= 1;
+ }
+ }
+ }
+
+ crcp->crc = crc;
+
+ if (crcp->config->reflect_remainder) {
+ crc = reflect(crc, crcp->config->poly_size);
+ }
+ }
+#endif
+
+ return (crc ^ crcp->config->final_val) & mask;
+}
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
diff --git a/os/various/crcsw.h b/os/various/crcsw.h
new file mode 100644
index 0000000..4483a34
--- /dev/null
+++ b/os/various/crcsw.h
@@ -0,0 +1,215 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file crcsw.h
+ * @brief CRC software driver.
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_CRC || defined(__DOXYGEN__)
+
+#if CRCSW_USE_CRC1 || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief CRC1 software driver enable switch.
+ * @details If set to @p TRUE the support for CRC1 is included.
+ * @note The default is @p FALSE
+ */
+#if !defined(CRCSW_USE_CRC1) || defined(__DOXYGEN__)
+#define CRCSW_USE_CRC1 FALSE
+#endif
+
+/**
+ * @brief Enables software CRC32
+ */
+#if !defined(CRCSW_CRC32_TABLE) || defined(__DOXYGEN__)
+#define CRCSW_CRC32_TABLE FALSE
+#endif
+
+/**
+ * @brief Enables software CRC16
+ */
+#if !defined(CRCSW_CRC16_TABLE) || defined(__DOXYGEN__)
+#define CRCSW_CRC16_TABLE FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if CRCSW_USE_CRC1 && CRC_USE_DMA
+#error "Software CRC does not support DMA(CRC_USE_DMA)"
+#endif
+
+#if CRCSW_CRC32_TABLE == FALSE && CRCSW_CRC16_TABLE == FALSE && \
+ CRCSW_PROGRAMMABLE == FALSE
+#error "At least one of CRCSW_PROGRAMMABLE, CRCSW_CRC32_TABLE, or CRCSW_CRC16_TABLE must be defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Type of a structure representing an CRC driver.
+ */
+typedef struct CRCDriver CRCDriver;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief The size of polynomial to be used for CRC.
+ */
+ uint32_t poly_size;
+ /**
+ * @brief The coefficients of the polynomial to be used for CRC.
+ */
+ uint32_t poly;
+ /**
+ * @brief The inital value
+ */
+ uint32_t initial_val;
+ /**
+ * @brief The final XOR value
+ */
+ uint32_t final_val;
+ /**
+ * @brief Reflect bit order data going into CRC
+ */
+ bool reflect_data;
+ /**
+ * @brief Reflect bit order of final remainder
+ */
+ bool reflect_remainder;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief The crc lookup table to use when calculating CRC.
+ */
+ const uint32_t *table;
+} CRCConfig;
+
+
+/**
+ * @brief Structure representing an CRC driver.
+ */
+struct CRCDriver {
+ /**
+ * @brief Driver state.
+ */
+ crcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const CRCConfig *config;
+#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* CRC_USE_MUTUAL_EXCLUSION */
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Current value of calculated CRC.
+ */
+ uint32_t crc;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+#if CRCSW_CRC32_TABLE || defined(__DOXYGEN__)
+/**
+ * @brief Configuration that represents CRC32
+ */
+#define CRCSW_CRC32_TABLE_CONFIG (&crcsw_crc32_config)
+#endif
+
+#if CRCSW_CRC16_TABLE || defined(__DOXYGEN__)
+/**
+ * @brief Configuration that represents CRC16
+ */
+#define CRCSW_CRC16_TABLE_CONFIG (&crcsw_crc16_config)
+#endif
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern CRCDriver CRCD1;
+
+#if CRCSW_CRC32_TABLE
+extern const CRCConfig crcsw_crc32_config;
+#endif
+
+#if CRCSW_CRC16_TABLE
+extern const CRCConfig crcsw_crc16_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void crc_lld_init(void);
+ void crc_lld_start(CRCDriver *crcp);
+ void crc_lld_stop(CRCDriver *crcp);
+ void crc_lld_reset(CRCDriver *crcp);
+ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
+
+/** @} */
diff --git a/testhal/STM32/STM32F0xx/crc/Makefile b/testhal/STM32/STM32F0xx/crc/Makefile
new file mode 100644
index 0000000..835f072
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/Makefile
@@ -0,0 +1,212 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x200
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/community/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F0xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
+# Other files (optional).
+#include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/STM32F051x8.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ main.c \
+ $(CHIBIOS)/community/os/various/crcsw.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various $(CHIBIOS)/community/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m0
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/STM32/STM32F0xx/crc/chconf.h b/testhal/STM32/STM32F0xx/crc/chconf.h
new file mode 100644
index 0000000..1884649
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/chconf.h
@@ -0,0 +1,499 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 10000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM FALSE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F0xx/crc/halconf.h b/testhal/STM32/STM32F0xx/crc/halconf.h
new file mode 100644
index 0000000..17118b0
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/halconf.h
@@ -0,0 +1,340 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* Community drivers's includes */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F0xx/crc/halconf_community.h b/testhal/STM32/STM32F0xx/crc/halconf_community.h
new file mode 100644
index 0000000..9f2aa99
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/halconf_community.h
@@ -0,0 +1,104 @@
+/*
+ ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _HALCONF_COMMUNITY_H_
+#define _HALCONF_COMMUNITY_H_
+
+/**
+ * @brief Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY TRUE
+#endif
+
+/**
+ * @brief Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND FALSE
+#endif
+
+/**
+ * @brief Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE FALSE
+#endif
+
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables strong pull up feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP FALSE
+
+/**
+ * @brief Enables search ROM feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM TRUE
+
+/*===========================================================================*/
+/* CRC driver settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the community subsystem.
+ */
+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
+#define HAL_USE_CRC TRUE
+#endif
+
+/**
+ * @brief Enables DMA engine when performing CRC transactions.
+ * @note Enabling this option also enables asynchronous API.
+ */
+#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__)
+#define CRC_USE_DMA FALSE
+#endif
+
+/**
+ * @brief Enables the @p crcAcquireUnit() and @p crcReleaseUnit() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define CRC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_COMMUNITY_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F0xx/crc/main.c b/testhal/STM32/STM32F0xx/crc/main.c
new file mode 100644
index 0000000..6da0808
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/main.c
@@ -0,0 +1,244 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+
+/*
+ * Data used for CRC calculation.
+ */
+uint8_t data[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
+};
+
+uint32_t gCrc = 0;
+
+
+/*
+ * CRC Callback used with DMA testing
+ */
+void crc_callback(CRCDriver *crcp, uint32_t crc) {
+ (void)crcp;
+ gCrc = crc;
+}
+
+
+/*
+ * CRC32 configuration
+ */
+static const CRCConfig crc32_config = {
+ .poly_size = 32,
+ .poly = 0x04C11DB7,
+ .initial_val = 0xFFFFFFFF,
+ .final_val = 0xFFFFFFFF,
+ .reflect_data = 1,
+ .reflect_remainder = 1
+};
+
+/*
+ * CRC16 configuration
+ */
+static const CRCConfig crc16_config = {
+ .poly_size = 16,
+ .poly = 0x8005,
+ .initial_val = 0x0,
+ .final_val = 0x0,
+ .reflect_data = 1,
+ .reflect_remainder = 1
+};
+
+/*
+ * CRC OpenPGP
+ */
+static const CRCConfig crc8_config = {
+ .poly_size = 8,
+ .poly = 0x07,
+ .initial_val = 0x0,
+ .final_val = 0x0,
+ .reflect_data = 0,
+ .reflect_remainder = 0
+};
+
+
+#if CRC_USE_DMA == TRUE
+/*
+ * CRC32 configuration with DMA
+ */
+static const CRCConfig crc32_dma_config = {
+ .poly_size = 32,
+ .poly = 0x04C11DB7,
+ .initial_val = 0xFFFFFFFF,
+ .final_val = 0xFFFFFFFF,
+ .reflect_data = 1,
+ .reflect_remainder = 1,
+ .end_cb = crc_callback
+};
+
+/*
+ * CRC16 configuration with DMA
+ */
+static const CRCConfig crc16_dma_config = {
+ .poly_size = 16,
+ .poly = 0x8005,
+ .initial_val = 0x0,
+ .final_val = 0x0,
+ .reflect_data = 1,
+ .reflect_remainder = 1,
+ .end_cb = crc_callback
+};
+#endif
+
+
+static void testCrc(const CRCConfig *config, uint32_t result) {
+ uint32_t crc;
+
+ crcAcquireUnit(&CRCD1); /* Acquire ownership of the bus. */
+ crcStart(&CRCD1, config); /* Activate CRC driver */
+ crcReset(&CRCD1);
+ crc = crcCalc(&CRCD1, sizeof(data), &data);
+ osalDbgAssert(crc == result, "CRC does not match expected result");
+ crcStop(&CRCD1); /* Deactive CRC driver); */
+ crcReleaseUnit(&CRCD1); /* Acquire ownership of the bus. */
+}
+
+
+#if CRC_USE_DMA
+static void testCrcDma(const CRCConfig *config, uint32_t result) {
+ gCrc = 0;
+
+ crcAcquireUnit(&CRCD1); /* Acquire ownership of the bus. */
+ crcStart(&CRCD1, config); /* Activate CRC driver */
+ crcReset(&CRCD1);
+ crcStartCalc(&CRCD1, sizeof(data), &data);
+ while (gCrc == 0); /* Wait for callback to verify */
+ crcStop(&CRCD1); /* Deactive CRC driver); */
+ crcReleaseUnit(&CRCD1); /* Acquire ownership of the bus. */
+
+ osalDbgAssert(gCrc == result, "CRC does not match expected result");
+}
+#endif
+
+/*
+ * CRC thread
+ */
+static THD_WORKING_AREA(crc_thread_1_wa, 256);
+static THD_FUNCTION(crc_thread_1, p) {
+ (void)p;
+ chRegSetThreadName("CRC thread 1");
+ while (true) {
+
+/* Test ST hardware CRC */
+/* if CRC_USE_DMA == TRUE these sync function internally use DMA and put the
+ * calling thread to sleep */
+#if STM32_CRC_USE_CRC1 == TRUE
+ /* CRC32 Calculation */
+ testCrc(&crc32_config, 0x91267e8a);
+ /* CRC16 Calculation */
+ testCrc(&crc16_config, 0xc36a);
+ /* CRC8 Calculation */
+ testCrc(&crc8_config, 0x06);
+
+/* Test ST CRC with DMA */
+#if CRC_USE_DMA == TRUE
+ /* CRC32 Calculation */
+ testCrcDma(&crc32_dma_config, 0x91267e8a);
+ /* CRC16 Calculation */
+ testCrcDma(&crc16_dma_config, 0xc36a);
+#endif
+
+#endif /* STM32_CRC_USE_CRC1 */
+
+
+/* Test software CRC */
+#if CRCSW_USE_CRC1 == TRUE
+/* Test CRCSW with compute CRC */
+#if CRCSW_PROGRAMMABLE == TRUE
+ /* CRC32 Calculation */
+ testCrc(&crc32_config, 0x91267e8a);
+ /* CRC16 Calculation */
+ testCrc(&crc16_config, 0xc36a);
+ testCrc(&crc8_config, 0x06);
+#endif
+/* Test CRCSW with table lookups. */
+#if CRCSW_CRC32_TABLE == TRUE
+ /* CRC32 Calculation with table lookup */
+ testCrc(CRCSW_CRC32_TABLE_CONFIG, 0x91267e8a);
+#endif
+#if CRCSW_CRC16_TABLE == TRUE
+ /* CRC16 Calculation with table lookup */
+ testCrc(CRCSW_CRC16_TABLE_CONFIG, 0xc36a);
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+ }
+}
+
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ palClearPad(GPIOC, GPIOC_LED_RED);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOC, GPIOC_LED_RED);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Starting the CRC thread
+ */
+ chThdCreateStatic(crc_thread_1_wa, sizeof(crc_thread_1_wa),
+ NORMALPRIO + 1, crc_thread_1, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (true) {
+ chThdSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf.h b/testhal/STM32/STM32F0xx/crc/mcuconf.h
new file mode 100644
index 0000000..ad184cd
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/mcuconf.h
@@ -0,0 +1,166 @@
+/*
+ ChibiOS - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * STM32F0xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 3...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F0xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_HSI_ENABLED TRUE
+#define STM32_HSI14_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
+#define STM32_PREDIV_VALUE 1
+#define STM32_PLLMUL_VALUE 12
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE STM32_PPRE_DIV1
+#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_CECSW STM32_CECSW_HSI
+#define STM32_I2C1SW STM32_I2C1SW_HSI
+#define STM32_USART1SW STM32_USART1SW_PCLK
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 2
+#define STM32_GPT_TIM2_IRQ_PRIORITY 2
+#define STM32_GPT_TIM3_IRQ_PRIORITY 2
+#define STM32_GPT_TIM14_IRQ_PRIORITY 2
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_IRQ_PRIORITY 3
+#define STM32_I2C_I2C2_IRQ_PRIORITY 3
+#define STM32_I2C_USE_DMA TRUE
+#define STM32_I2C_I2C1_DMA_PRIORITY 1
+#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 3
+#define STM32_ICU_TIM2_IRQ_PRIORITY 3
+#define STM32_ICU_TIM3_IRQ_PRIORITY 3
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 3
+#define STM32_PWM_TIM2_IRQ_PRIORITY 3
+#define STM32_PWM_TIM3_IRQ_PRIORITY 3
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 3
+#define STM32_SERIAL_USART2_PRIORITY 3
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 2
+#define STM32_SPI_SPI2_IRQ_PRIORITY 2
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 2
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USART1_IRQ_PRIORITY 3
+#define STM32_UART_USART2_IRQ_PRIORITY 3
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * header for community drivers.
+ */
+#include "mcuconf_community.h"
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h
new file mode 100644
index 0000000..8df78ec
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h
@@ -0,0 +1,33 @@
+/*
+ ChibiOS/RT - Copyright (C) 2015 Michael D. Spradling
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_COMMUNITY_H_
+#define _MCUCONF_COMMUNITY_H_
+
+/*
+ * CRC driver system settings.
+ */
+#define STM32_CRC_USE_CRC1 TRUE
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
+#define STM32_CRC_CRC1_DMA_PRIORITY 2
+#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
+
+#define CRCSW_USE_CRC1 FALSE
+#define CRCSW_CRC32_TABLE TRUE
+#define CRCSW_CRC16_TABLE TRUE
+#define CRCSW_PROGRAMMABLE TRUE
+
+#endif
diff --git a/testhal/STM32/STM32F0xx/crc/readme.txt b/testhal/STM32/STM32F0xx/crc/readme.txt
new file mode 100644
index 0000000..b10413a
--- /dev/null
+++ b/testhal/STM32/STM32F0xx/crc/readme.txt
@@ -0,0 +1,36 @@
+*****************************************************************************
+** ChibiOS/HAL - CRC driver demo for STM32F0xx (also sw driver) **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an ST STM32F0-Discovery board.
+
+** The Demo **
+
+The application demonstrates the use of the STM32F0xx CRC driver. There are
+many different ways to configure and setup the CRC. This demo has be
+configured to test the following:
+ * ST hardware block configured with CRC32 with or without DMA
+ * ST hardware block configured with CRC16 with or without DMA
+ * Software CRC32
+ * Software CRC16
+
+** Board Setup **
+
+- No requirements
+
+** Build Procedure **
+
+The demo has been tested using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 00:59:04 +0000