Merge branch 'master' of https://github.com/ChibiOS/ChibiOS-Contrib

3 files changed, 385 insertions, 0 deletions

diff --git a/tools/templates/board_gpio.tpl b/tools/templates/board_gpio.tpl
new file mode 100644
index 0000000..07a316d
--- /dev/null
+++ b/tools/templates/board_gpio.tpl
@@ -0,0 +1,55 @@
+#ifndef _BOARD_GPIO_H_
+#define _BOARD_GPIO_H_
+
+/* Generated by mx2board.py */
+
+{% for d, v in defines %}
+#define {{ d }} {{ v }}
+{%- endfor %}
+
+{% for p, v in ports %}
+/* PORT {{p}} */
+#define VAL_GPIO{{p}}_MODER ( \
+    {%- for i in v.MODER %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_OTYPER ( \
+    {%- for i in v.OTYPER %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_OSPEEDR ( \
+    {%- for i in v.OSPEEDR %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_PUPDR ( \
+    {%- for i in v.PUPDR %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_ODR ( \
+    {%- for i in v.ODR %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_AFRL ( \
+    {%- for i in v.AFRL %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+
+#define VAL_GPIO{{p}}_AFRH ( \
+    {%- for i in v.AFRH %}
+    {{ i }} | \
+    {%- endfor %}
+    0)
+{% endfor %}
+
+#endif
\ No newline at end of file
diff --git a/tools/templates/halconf_community.h b/tools/templates/halconf_community.h
new file mode 100644
index 0000000..631bb9f
--- /dev/null
+++ b/tools/templates/halconf_community.h
@@ -0,0 +1,173 @@
+/*

+    ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef HALCONF_COMMUNITY_H

+#define HALCONF_COMMUNITY_H

+

+/**

+ * @brief   Enables the community overlay.

+ */

+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)

+#define HAL_USE_COMMUNITY           TRUE

+#endif

+

+/**

+ * @brief   Enables the FSMC subsystem.

+ */

+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)

+#define HAL_USE_FSMC                FALSE

+#endif

+

+/**

+ * @brief   Enables the NAND subsystem.

+ */

+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)

+#define HAL_USE_NAND                FALSE

+#endif

+

+/**

+ * @brief   Enables the 1-wire subsystem.

+ */

+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)

+#define HAL_USE_ONEWIRE             FALSE

+#endif

+

+/**

+ * @brief   Enables the EICU subsystem.

+ */

+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)

+#define HAL_USE_EICU                FALSE

+#endif

+

+/**

+ * @brief   Enables the CRC subsystem.

+ */

+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)

+#define HAL_USE_CRC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the RNG subsystem.

+ */

+#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)

+#define HAL_USE_RNG                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EEPROM subsystem.

+ */

+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)

+#define HAL_USE_EEPROM              FALSE

+#endif

+

+/**

+ * @brief   Enables the TIMCAP subsystem.

+ */

+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)

+#define HAL_USE_TIMCAP              FALSE

+#endif

+

+/**

+ * @brief   Enables the TIMCAP subsystem.

+ */

+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)

+#define HAL_USE_COMP                FALSE

+#endif

+

+/**

+ * @brief   Enables the QEI subsystem.

+ */

+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)

+#define HAL_USE_QEI                 FALSE

+#endif

+

+/**

+ * @brief   Enables the USBH subsystem.

+ */

+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)

+#define HAL_USE_USBH                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB_MSD subsystem.

+ */

+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)

+#define HAL_USE_USB_MSD             FALSE

+#endif

+

+/*===========================================================================*/

+/* FSMCNAND driver related settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define NAND_USE_MUTUAL_EXCLUSION   TRUE

+#endif

+

+/*===========================================================================*/

+/* 1-wire driver related settings.                                           */

+/*===========================================================================*/

+/**

+ * @brief   Enables strong pull up feature.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define ONEWIRE_USE_STRONG_PULLUP   FALSE

+

+/**

+ * @brief   Enables search ROM feature.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define ONEWIRE_USE_SEARCH_ROM      TRUE

+

+/*===========================================================================*/

+/* QEI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables discard of overlow

+ */

+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)

+#define QEI_USE_OVERFLOW_DISCARD    FALSE

+#endif

+

+/**

+ * @brief   Enables min max of overlow

+ */

+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)

+#define QEI_USE_OVERFLOW_MINMAX     FALSE

+#endif

+

+/*===========================================================================*/

+/* EEProm driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables 24xx series I2C eeprom device driver.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define EEPROM_USE_EE24XX FALSE

+ /**

+ * @brief   Enables 25xx series SPI eeprom device driver.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define EEPROM_USE_EE25XX FALSE

+

+#endif /* HALCONF_COMMUNITY_H */

+

+/** @} */

diff --git a/tools/templates/mcuconf_community.h b/tools/templates/mcuconf_community.h
new file mode 100644
index 0000000..1ebe24c
--- /dev/null
+++ b/tools/templates/mcuconf_community.h
@@ -0,0 +1,157 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * FSMC driver system settings.
+ */
+#define STM32_FSMC_USE_FSMC1                FALSE
+#define STM32_FSMC_FSMC1_IRQ_PRIORITY       10
+
+/*
+ * FSMC NAND driver system settings.
+ */
+#define STM32_NAND_USE_FSMC_NAND1           FALSE
+#define STM32_NAND_USE_FSMC_NAND2           FALSE
+#define STM32_NAND_USE_EXT_INT              FALSE
+#define STM32_NAND_DMA_STREAM               STM32_DMA_STREAM_ID(2, 7)
+#define STM32_NAND_DMA_PRIORITY             0
+#define STM32_NAND_DMA_ERROR_HOOK(nandp)    osalSysHalt("DMA failure")
+
+/*
+ * FSMC SRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SRAM                 FALSE
+#define STM32_SRAM_USE_FSMC_SRAM1           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM2           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM3           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM4           FALSE
+
+/*
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM                FALSE
+#define STM32_SDRAM_USE_FSMC_SDRAM1         FALSE
+#define STM32_SDRAM_USE_FSMC_SDRAM2         TRUE
+
+/*
+ * TIMCAP driver system settings.
+ */
+#define STM32_TIMCAP_USE_TIM1                  TRUE
+#define STM32_TIMCAP_USE_TIM2                  FALSE
+#define STM32_TIMCAP_USE_TIM3                  TRUE
+#define STM32_TIMCAP_USE_TIM4                  TRUE
+#define STM32_TIMCAP_USE_TIM5                  TRUE
+#define STM32_TIMCAP_USE_TIM8                  TRUE
+#define STM32_TIMCAP_USE_TIM9                  TRUE
+#define STM32_TIMCAP_TIM1_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM2_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM3_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM4_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM5_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM8_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM9_IRQ_PRIORITY         3
+
+/*
+ * COMP driver system settings.
+ */
+#define STM32_COMP_USE_COMP1                  TRUE
+#define STM32_COMP_USE_COMP2                  TRUE
+#define STM32_COMP_USE_COMP3                  TRUE
+#define STM32_COMP_USE_COMP4                  TRUE
+#define STM32_COMP_USE_COMP5                  TRUE
+#define STM32_COMP_USE_COMP6                  TRUE
+#define STM32_COMP_USE_COMP7                  TRUE
+
+#define STM32_COMP_USE_INTERRUPTS             TRUE
+#define STM32_COMP_1_2_3_IRQ_PRIORITY         5
+#define STM32_COMP_4_5_6_IRQ_PRIORITY         5
+#define STM32_COMP_7_IRQ_PRIORITY             5
+
+#if STM32_COMP_USE_INTERRUPTS
+#define STM32_DISABLE_EXTI21_22_29_HANDLER
+#define STM32_DISABLE_EXTI30_32_HANDLER
+#define STM32_DISABLE_EXTI33_HANDLER
+#endif
+
+/*
+ * USBH driver system settings.
+ */
+#define STM32_OTG1_CHANNELS_NUMBER          8
+#define STM32_OTG2_CHANNELS_NUMBER          12
+
+#define STM32_USBH_USE_OTG1                 1
+#define STM32_OTG1_RXFIFO_SIZE              1024
+#define STM32_OTG1_PTXFIFO_SIZE             128
+#define STM32_OTG1_NPTXFIFO_SIZE            128
+
+#define STM32_USBH_USE_OTG2                 0
+#define STM32_OTG2_RXFIFO_SIZE              2048
+#define STM32_OTG2_PTXFIFO_SIZE             1024
+#define STM32_OTG2_NPTXFIFO_SIZE            1024
+
+#define STM32_USBH_MIN_QSPACE               4
+#define STM32_USBH_CHANNELS_NP              4
+
+/*
+ * CRC driver system settings.
+ */
+#define STM32_CRC_USE_CRC1                  TRUE
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY     1
+#define STM32_CRC_CRC1_DMA_PRIORITY         2
+#define STM32_CRC_CRC1_DMA_STREAM           STM32_DMA1_STREAM2
+
+#define CRCSW_USE_CRC1                      FALSE
+#define CRCSW_CRC32_TABLE                   TRUE
+#define CRCSW_CRC16_TABLE                   TRUE
+#define CRCSW_PROGRAMMABLE                  TRUE
+
+/*
+ * EICU driver system settings.
+ */
+#define STM32_EICU_USE_TIM1                 TRUE
+#define STM32_EICU_USE_TIM2                 FALSE
+#define STM32_EICU_USE_TIM3                 TRUE
+#define STM32_EICU_USE_TIM4                 TRUE
+#define STM32_EICU_USE_TIM5                 TRUE
+#define STM32_EICU_USE_TIM8                 TRUE
+#define STM32_EICU_USE_TIM9                 TRUE
+#define STM32_EICU_USE_TIM10                TRUE
+#define STM32_EICU_USE_TIM11                TRUE
+#define STM32_EICU_USE_TIM12                TRUE
+#define STM32_EICU_USE_TIM13                TRUE
+#define STM32_EICU_USE_TIM14                TRUE
+#define STM32_EICU_TIM1_IRQ_PRIORITY        7
+#define STM32_EICU_TIM2_IRQ_PRIORITY        7
+#define STM32_EICU_TIM3_IRQ_PRIORITY        7
+#define STM32_EICU_TIM4_IRQ_PRIORITY        7
+#define STM32_EICU_TIM5_IRQ_PRIORITY        7
+#define STM32_EICU_TIM8_IRQ_PRIORITY        7
+#define STM32_EICU_TIM9_IRQ_PRIORITY        7
+#define STM32_EICU_TIM10_IRQ_PRIORITY       7
+#define STM32_EICU_TIM11_IRQ_PRIORITY       7
+#define STM32_EICU_TIM12_IRQ_PRIORITY       7
+#define STM32_EICU_TIM13_IRQ_PRIORITY       7
+#define STM32_EICU_TIM14_IRQ_PRIORITY       7
+
+/*
+ * QEI driver system settings.
+ */
+#define STM32_QEI_USE_TIM1                TRUE
+#define STM32_QEI_USE_TIM2                FALSE
+#define STM32_QEI_USE_TIM3                TRUE
+#define STM32_QEI_TIM1_IRQ_PRIORITY         3
+#define STM32_QEI_TIM2_IRQ_PRIORITY         3
+#define STM32_QEI_TIM3_IRQ_PRIORITY         3