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author | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-14 20:15:13 +0100 |
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committer | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-14 20:15:13 +0100 |
commit | 424c7a2717fb6b2a847cec5c0060e3236f25e97f (patch) | |
tree | b41f66639a1bcafa9d8ddbf8feb800d8cd7ffbbd /testhal/STM32/STM32F3xx/COMP/mcuconf_community.h | |
parent | 1bfe2ef9f7f39d93174b1f62ac4b079aac2dea59 (diff) | |
download | ChibiOS-Contrib-424c7a2717fb6b2a847cec5c0060e3236f25e97f.tar.gz ChibiOS-Contrib-424c7a2717fb6b2a847cec5c0060e3236f25e97f.tar.bz2 ChibiOS-Contrib-424c7a2717fb6b2a847cec5c0060e3236f25e97f.zip |
Fixed most testhal examples for STM32, updated configs using script. Fixed deprecated MS2ST calls.
Diffstat (limited to 'testhal/STM32/STM32F3xx/COMP/mcuconf_community.h')
-rw-r--r-- | testhal/STM32/STM32F3xx/COMP/mcuconf_community.h | 82 |
1 files changed, 76 insertions, 6 deletions
diff --git a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h index 1f89e54..cf6a1ce 100644 --- a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h @@ -47,13 +47,13 @@ /* * TIMCAP driver system settings. */ -#define STM32_TIMCAP_USE_TIM1 FALSE +#define STM32_TIMCAP_USE_TIM1 TRUE #define STM32_TIMCAP_USE_TIM2 FALSE -#define STM32_TIMCAP_USE_TIM3 FALSE -#define STM32_TIMCAP_USE_TIM4 FALSE -#define STM32_TIMCAP_USE_TIM5 FALSE -#define STM32_TIMCAP_USE_TIM8 FALSE -#define STM32_TIMCAP_USE_TIM9 FALSE +#define STM32_TIMCAP_USE_TIM3 TRUE +#define STM32_TIMCAP_USE_TIM4 TRUE +#define STM32_TIMCAP_USE_TIM5 TRUE +#define STM32_TIMCAP_USE_TIM8 TRUE +#define STM32_TIMCAP_USE_TIM9 TRUE #define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3 #define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3 #define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3 @@ -83,3 +83,73 @@ #define STM32_DISABLE_EXTI30_32_HANDLER #define STM32_DISABLE_EXTI33_HANDLER #endif + +/* + * USBH driver system settings. + */ +#define STM32_OTG1_CHANNELS_NUMBER 8 +#define STM32_OTG2_CHANNELS_NUMBER 12 + +#define STM32_USBH_USE_OTG1 1 +#define STM32_OTG1_RXFIFO_SIZE 1024 +#define STM32_OTG1_PTXFIFO_SIZE 128 +#define STM32_OTG1_NPTXFIFO_SIZE 128 + +#define STM32_USBH_USE_OTG2 0 +#define STM32_OTG2_RXFIFO_SIZE 2048 +#define STM32_OTG2_PTXFIFO_SIZE 1024 +#define STM32_OTG2_NPTXFIFO_SIZE 1024 + +#define STM32_USBH_MIN_QSPACE 4 +#define STM32_USBH_CHANNELS_NP 4 + +/* + * CRC driver system settings. + */ +#define STM32_CRC_USE_CRC1 TRUE +#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1 +#define STM32_CRC_CRC1_DMA_PRIORITY 2 +#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2 + +#define CRCSW_USE_CRC1 FALSE +#define CRCSW_CRC32_TABLE TRUE +#define CRCSW_CRC16_TABLE TRUE +#define CRCSW_PROGRAMMABLE TRUE + +/* + * EICU driver system settings. + */ +#define STM32_EICU_USE_TIM1 TRUE +#define STM32_EICU_USE_TIM2 FALSE +#define STM32_EICU_USE_TIM3 TRUE +#define STM32_EICU_USE_TIM4 TRUE +#define STM32_EICU_USE_TIM5 TRUE +#define STM32_EICU_USE_TIM8 TRUE +#define STM32_EICU_USE_TIM9 TRUE +#define STM32_EICU_USE_TIM10 TRUE +#define STM32_EICU_USE_TIM11 TRUE +#define STM32_EICU_USE_TIM12 TRUE +#define STM32_EICU_USE_TIM13 TRUE +#define STM32_EICU_USE_TIM14 TRUE +#define STM32_EICU_TIM1_IRQ_PRIORITY 7 +#define STM32_EICU_TIM2_IRQ_PRIORITY 7 +#define STM32_EICU_TIM3_IRQ_PRIORITY 7 +#define STM32_EICU_TIM4_IRQ_PRIORITY 7 +#define STM32_EICU_TIM5_IRQ_PRIORITY 7 +#define STM32_EICU_TIM8_IRQ_PRIORITY 7 +#define STM32_EICU_TIM9_IRQ_PRIORITY 7 +#define STM32_EICU_TIM10_IRQ_PRIORITY 7 +#define STM32_EICU_TIM11_IRQ_PRIORITY 7 +#define STM32_EICU_TIM12_IRQ_PRIORITY 7 +#define STM32_EICU_TIM13_IRQ_PRIORITY 7 +#define STM32_EICU_TIM14_IRQ_PRIORITY 7 + +/* + * QEI driver system settings. + */ +#define STM32_QEI_USE_TIM1 TRUE +#define STM32_QEI_USE_TIM2 FALSE +#define STM32_QEI_USE_TIM3 TRUE +#define STM32_QEI_TIM1_IRQ_PRIORITY 3 +#define STM32_QEI_TIM2_IRQ_PRIORITY 3 +#define STM32_QEI_TIM3_IRQ_PRIORITY 3 |