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authorbarthess <barthess@yandex.ru>2016-12-09 18:00:28 +0300
committerbarthess <barthess@yandex.ru>2016-12-09 18:00:28 +0300
commit53d3fd07f381f2dac8a39913ebe7062c8076cd30 (patch)
treed3df55d1672dbe1fc735cf055148c4c9e490e9c2 /testhal/KINETIS/TEENSY3_x/ADC
parent319c9f9ee259cc7ae05bbff952b149118e6dc032 (diff)
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FSMC. Sync mode improvements.
1) Control registers writes reordered in init sequence to eliminate incorrect output clock frequnency in short period after CCLKEN bit set and B(W)TR registers set. 2) Added reset of CCLEN bit in stop procedure.
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0 files changed, 0 insertions, 0 deletions