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| author | Michael Walker <walkerstop@gmail.com> | 2018-05-02 06:49:29 -0700 |
|---|---|---|
| committer | Michael Walker <walkerstop@gmail.com> | 2018-05-02 06:49:29 -0700 |
| commit | 5bec0d7abc33169ef468e194297853a4d7f6ba79 (patch) | |
| tree | 824cc39336e153db86937eb40e7372908cbe7145 /os | |
| parent | 0f3af19758181dde931d3889ccc8eef0f00b4e39 (diff) | |
| download | ChibiOS-Contrib-5bec0d7abc33169ef468e194297853a4d7f6ba79.tar.gz ChibiOS-Contrib-5bec0d7abc33169ef468e194297853a4d7f6ba79.tar.bz2 ChibiOS-Contrib-5bec0d7abc33169ef468e194297853a4d7f6ba79.zip | |
Always use IRC48M clock for USB on MK66F18
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c index fee91c5..694f5e2 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -405,11 +405,6 @@ void usb_lld_init(void) { /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
-#if defined(MK66F18)
- /* Switch from default MCGPLLCLK to IRC48M for USB */
- SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
-#endif
-
#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
#define KINETIS_USBCLK_FREQUENCY 48000000UL
@@ -429,6 +424,12 @@ void usb_lld_init(void) { #error USB clock setting not implemented for this KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE == ... */
+#if defined(MK66F18)
+ /* Switch from default MCGPLLCLK to IRC48M for USB */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#endif
+
#elif defined(KL25) || defined (KL26) || defined(KL27)
/* No extra clock dividers for USB clock */
|