FSMC. SDRAM architecture reworked. Needs review.

4 files changed, 119 insertions, 240 deletions

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
index 65f3baf..6cadfb1 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
@@ -107,11 +107,7 @@ void fsmc_init(void) {
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx))
   #if STM32_SDRAM_USE_FSMC_SDRAM1
-    FSMCD1.sdram1 = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE;
-  #endif
-
-  #if STM32_SDRAM_USE_FSMC_SDRAM2
-    FSMCD1.sdram2 = (FSMC_SDRAM_TypeDef *)FSMC_Bank6_R_BASE;
+    FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
   #endif
 #endif
   }
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
index 21c58bd..4ca6e58 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
@@ -56,10 +56,7 @@
   #define FSMC_Bank4_R_BASE               (FMC_R_BASE + 0x00A0)
   #endif
   #if !defined(FSMC_Bank5_R_BASE)
-  #define FSMC_Bank5_R_BASE               (FMC_R_BASE + 0x0140)
-  #endif
-  #if !defined(FSMC_Bank_R_BASE)
-  #define FSMC_Bank6_R_BASE               (FMC_R_BASE + 0x0144)
+  #define FSMC_Bank5_6_R_BASE             (FMC_R_BASE + 0x0140)
   #endif
 #else
   #if !defined(FSMC_Bank1_R_BASE)
@@ -165,11 +162,20 @@ typedef struct {
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx))
-  typedef struct {
-    __IO uint32_t SDCR;         /**< SDRAM control register */
-    uint32_t      RESERVED0;    /**< Reserved */
-    __IO uint32_t SDTR;         /**< SDRAM timing register */
-  } FSMC_SDRAM_TypeDef;
+
+typedef struct {
+  __IO uint32_t SDCR;         /**< SDRAM control register */
+  uint32_t      RESERVED;     /**< Reserved */
+  __IO uint32_t SDTR;         /**< SDRAM timing register */
+} FSMC_SDRAM_BANK_TypeDef;
+
+typedef struct {
+  FSMC_SDRAM_BANK_TypeDef banks[2]; /**< Banks mapping */
+  __IO uint32_t SDCMR;              /**< SDRAM comand mode register */
+  __IO uint32_t SDRTR;              /**< SDRAM refresh timer register */
+  __IO uint32_t SDSR;               /**< SDRAM status register */
+} FSMC_SDRAM_TypeDef;
+
 #endif
 
 /**
@@ -296,11 +302,8 @@ struct FSMCDriver {
 #endif
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx))
-  #if STM32_SDRAM_USE_FSMC_SDRAM1
-    FSMC_SDRAM_TypeDef       *sdram1;
-  #endif
-  #if STM32_SDRAM_USE_FSMC_SDRAM2
-    FSMC_SDRAM_TypeDef       *sdram2;
+  #if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM1)
+    FSMC_SDRAM_TypeDef       *sdram;
   #endif
 #endif
 };
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
index b738185..6ac6966 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
@@ -54,18 +54,9 @@
 /* Driver exported variables.                                                */
 /*===========================================================================*/
 /**
- * @brief   SDRAM1 driver identifier.
+ * @brief   SDRAM driver identifier.
  */
-#if STM32_SDRAM_USE_FSMC_SDRAM1 || defined(__DOXYGEN__)
-SDRAMDriver SDRAMD1;
-#endif
-
-/**
- * @brief   SDRAM2 driver identifier.
- */
-#if STM32_SDRAM_USE_FSMC_SDRAM2 || defined(__DOXYGEN__)
-SDRAMDriver SDRAMD2;
-#endif
+SDRAMDriver SDRAMD;
 
 /*===========================================================================*/
 /* Driver local types.                                                       */
@@ -80,77 +71,90 @@ SDRAMDriver SDRAMD2;
 /*===========================================================================*/
 
 /**
+ * @brief   Wait until the SDRAM controller is ready.
+ *
+ * @notapi
+ */
+static void _sdram_wait_ready(void) {
+  /* Wait until the SDRAM controller is ready */
+  while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY);
+}
+
+/**
  * @brief   Executes the SDRAM memory initialization sequence.
  *
  * @param[in] sdramp         pointer to the @p SDRAMDriver object
  *
  * @notapi
  */
-static void fsmc_sdram_init_sequence(uint32_t command_target) {
-  uint32_t tmpreg;
-  /* Step 3 -----------------------------------------------------------------*/
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-  /* Configure a clock configuration enable command */
-  FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_CLK_Enabled |
-    command_target | 
-    ((1 -1) <<  5) | // FMC_AutoRefreshNumber = 1
-    (0 << 9);        // FMC_ModeRegisterDefinition = 0
-  /* Step 4 -----------------------------------------------------------------*/
-  /* Insert 10 ms delay */
+static void _sdram_init_sequence(void) {
+
+  uint32_t tmp = 0;
+  uint32_t command_target = 0;
+
+#if STM32_SDRAM_USE_FSMC_SDRAM1
+  command_target |= FMC_SDCMR_CTB1;
+#endif
+#if STM32_SDRAM_USE_FSMC_SDRAM2
+  command_target |= FMC_SDCMR_CTB2;
+#endif
+
+  /* Step 3: Configure a clock configuration enable command.*/
+  _sdram_wait_ready();
+  SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_CLK_Enabled |
+          command_target |
+          ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+          (0 << 9);        // FMC_ModeRegisterDefinition = 0
+
+  /* Step 4: Insert 10 ms delay.*/
   chSysPolledDelayX(MS2ST(10));
-  /* Step 5 -----------------------------------------------------------------*/
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-  /* Configure a PALL (precharge all) command */
-  FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_PALL |
-    command_target |
-    ((1 -1) <<  5) | // FMC_AutoRefreshNumber = 1
-    (0 << 9);        // FMC_ModeRegisterDefinition = 0
-  /* Step 6 -----------------------------------------------------------------*/
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-  /* Configure a Auto-Refresh command: Send the first command */
-  FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
-    command_target |
-    ((4 -1) <<  5) | // FMC_AutoRefreshNumber = 4
-    (0 << 9);        // FMC_ModeRegisterDefinition = 0
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-  /* Configure a Auto-Refresh command: Send the second command*/
-  FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
-    command_target |
-    ((4 -1) <<  5) | // FMC_AutoRefreshNumber = 4
-    (0 << 9);        // FMC_ModeRegisterDefinition = 0
-  /* Step 7 -----------------------------------------------------------------*/
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-  /* Program the external memory mode register */
-  tmpreg = FMC_SDCMR_MRD_BURST_LENGTH_2 |
-    FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
-    FMC_SDCMR_MRD_CAS_LATENCY_3 |
-    FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
-    FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE;
-  /* Send the command */
-  FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_LoadMode |
-    command_target |
-    ((1 -1) <<  5) | // FMC_AutoRefreshNumber = 1
-    (tmpreg << 9);
-  /* Step 8 -----------------------------------------------------------------*/
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
+
+  /* Step 5: Configure a PALL (precharge all) command.*/
+  _sdram_wait_ready();
+  SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_PALL |
+          command_target |
+          ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+          (0 << 9);        // FMC_ModeRegisterDefinition = 0
+
+  /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
+  _sdram_wait_ready();
+  SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
+          command_target |
+          ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
+          (0 << 9);        // FMC_ModeRegisterDefinition = 0
+
+  /* Step 6.2: Send the second command.*/
+  SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
+          command_target |
+          ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
+          (0 << 9);        // FMC_ModeRegisterDefinition = 0
+
+  /* Step 7: Program the external memory mode register.*/
+  _sdram_wait_ready();
+  tmp = FMC_SDCMR_MRD_BURST_LENGTH_2 |
+          FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
+          FMC_SDCMR_MRD_CAS_LATENCY_3 |
+          FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
+          FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE;
+  SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_LoadMode |
+          command_target |
+          ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+          (tmp << 9);
+
+  /* Step 8: Set clock.*/
+  _sdram_wait_ready();
   // 64ms/4096=15.625us
 #if (STM32_SYSCLK == 180000000)
   //15.625us*90MHz=1406-20=1386
-  FMC_Bank5_6->SDRTR=1386<<1;
+  SDRAMD.sdram->SDRTR=1386<<1;
 #elif (STM32_SYSCLK == 168000000)
   //15.625us*84MHz=1312-20=1292
-  FMC_Bank5_6->SDRTR=1292<<1;
+  SDRAMD.sdram->SDRTR=1292<<1;
 #else
   #error No refresh timings for this clock
 #endif
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
+
+  _sdram_wait_ready();
 }
 
 /*===========================================================================*/
@@ -168,15 +172,8 @@ void fsmcSdramInit(void) {
 
   fsmc_init();
 
-#if STM32_SDRAM_USE_FSMC_SDRAM1
-  SDRAMD1.sdram = FSMCD1.sdram1;
-  SDRAMD1.state = SDRAM_STOP;
-#endif /* STM32_SDRAM_USE_FSMC_SDRAM1 */
-
-#if STM32_SDRAM_USE_FSMC_SDRAM2
-  SDRAMD2.sdram = FSMCD1.sdram2;
-  SDRAMD2.state = SDRAM_STOP;
-#endif /* STM32_SDRAM_USE_FSMC_SDRAM2 */
+  SDRAMD.sdram = FSMCD1.sdram;
+  SDRAMD.state = SDRAM_STOP;
 }
 
 /**
@@ -191,24 +188,19 @@ void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
     fsmc_start(&FSMCD1);
 
   osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
-              "invalid state");
+              "SDRAM. Invalid state.");
 
   if (sdramp->state == SDRAM_STOP) {
-    // Executes the SDRAM memory initialization sequence.
-    if (sdramp->sdram == (FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE) {
-      sdramp->sdram->SDCR = cfgp->sdcr;
-      sdramp->sdram->SDTR = cfgp->sdtr;
-      fsmc_sdram_init_sequence(FMC_Command_Target_bank1);
-    }
-    else { /* SDCR2 "don't care" bits configuration */
-      ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDCR = 
-        cfgp->sdcr & SDCR2_DONTCARE_BITS;
-      sdramp->sdram->SDCR = cfgp->sdcr;
-      ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDTR = 
-        cfgp->sdtr & SDTR2_DONTCARE_BITS;
-      sdramp->sdram->SDTR = cfgp->sdtr;
-      fsmc_sdram_init_sequence(FMC_Command_Target_bank2);
-    }
+#if STM32_SDRAM_USE_FSMC_SDRAM1
+    sdramp->sdram->banks[0].SDCR = cfgp->sdcr1;
+    sdramp->sdram->banks[0].SDTR = cfgp->sdtr1;
+#endif
+#if STM32_SDRAM_USE_FSMC_SDRAM2
+    sdramp->sdram->banks[1].SDCR = cfgp->sdcr2;
+    sdramp->sdram->banks[1].SDTR = cfgp->sdtr2;
+#endif
+    _sdram_init_sequence();
+
     sdramp->state = SDRAM_READY;
   }
 }
@@ -228,16 +220,6 @@ void fsmcSdramStop(SDRAMDriver *sdramp) {
 }
 
 /**
- * @brief   Wait until the SDRAM controller is ready.
- *
- * @notapi
- */
-void fsmcSdram_WaitReady(void) {
-  /* Wait until the SDRAM controller is ready */
-  while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-}
-
-/**
  * @brief  Enables or disables write protection to the specified SDRAM Bank.
  * @param  SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
@@ -245,13 +227,13 @@ void fsmcSdram_WaitReady(void) {
  *          This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
-void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state) {
-
-  if (state)
-    sdramp->sdram->SDCR |= FMC_Write_Protection_Enable;
-  else
-    sdramp->sdram->SDCR &= SDCR_WriteProtection_RESET;
-}
+//void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state) {
+//
+//  if (state)
+//    sdramp->sdram->SDCR |= FMC_Write_Protection_Enable;
+//  else
+//    sdramp->sdram->SDCR &= SDCR_WriteProtection_RESET;
+//}
 
 #endif /* STM32_USE_FSMC_SDRAM */
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h
index 010fb58..0cb6fef 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h
@@ -48,13 +48,6 @@
 #define FMC_ColumnBits_Number_9b           ((uint32_t)0x00000001)
 #define FMC_ColumnBits_Number_10b          ((uint32_t)0x00000002)
 #define FMC_ColumnBits_Number_11b          ((uint32_t)0x00000003)
-
-#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) \
-    (((COLUMN) == FMC_ColumnBits_Number_8b)  || \
-    ((COLUMN) == FMC_ColumnBits_Number_9b)  || \
-    ((COLUMN) == FMC_ColumnBits_Number_10b) || \
-    ((COLUMN) == FMC_ColumnBits_Number_11b))
-
 /**
  * @}
  */
@@ -66,12 +59,6 @@
 #define FMC_RowBits_Number_11b             ((uint32_t)0x00000000)
 #define FMC_RowBits_Number_12b             ((uint32_t)0x00000004)
 #define FMC_RowBits_Number_13b             ((uint32_t)0x00000008)
-
-#define IS_FMC_ROWBITS_NUMBER(ROW) \
-    (((ROW) == FMC_RowBits_Number_11b) || \
-    ((ROW) == FMC_RowBits_Number_12b) || \
-    ((ROW) == FMC_RowBits_Number_13b))
-
 /**
  * @}
  */
@@ -83,12 +70,6 @@
 #define FMC_SDMemory_Width_8b                ((uint32_t)0x00000000)
 #define FMC_SDMemory_Width_16b               ((uint32_t)0x00000010)
 #define FMC_SDMemory_Width_32b               ((uint32_t)0x00000020)
-
-#define IS_FMC_SDMEMORY_WIDTH(WIDTH) \
-    (((WIDTH) == FMC_SDMemory_Width_8b)  || \
-    ((WIDTH) == FMC_SDMemory_Width_16b) || \
-    ((WIDTH) == FMC_SDMemory_Width_32b))
-
 /**
  * @}
  */
@@ -99,11 +80,6 @@
  */
 #define FMC_InternalBank_Number_2          ((uint32_t)0x00000000)
 #define FMC_InternalBank_Number_4          ((uint32_t)0x00000040)
-
-#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) \
-    (((NUMBER) == FMC_InternalBank_Number_2) || \
-    ((NUMBER) == FMC_InternalBank_Number_4))
-
 /**
  * @}
  */
@@ -116,12 +92,6 @@
 #define FMC_CAS_Latency_1                  ((uint32_t)0x00000080)
 #define FMC_CAS_Latency_2                  ((uint32_t)0x00000100)
 #define FMC_CAS_Latency_3                  ((uint32_t)0x00000180)
-
-#define IS_FMC_CAS_LATENCY(LATENCY) \
-    (((LATENCY) == FMC_CAS_Latency_1) || \
-    ((LATENCY) == FMC_CAS_Latency_2) || \
-    ((LATENCY) == FMC_CAS_Latency_3))
-
 /**
  * @}
  */
@@ -132,11 +102,6 @@
  */
 #define FMC_Write_Protection_Disable       ((uint32_t)0x00000000)
 #define FMC_Write_Protection_Enable        ((uint32_t)0x00000200)
-
-#define IS_FMC_WRITE_PROTECTION(WRITE) \
-    (((WRITE) == FMC_Write_Protection_Disable) || \
-    ((WRITE) == FMC_Write_Protection_Enable))
-
 /**
  * @}
  */
@@ -150,12 +115,6 @@
 #define FMC_SDClock_Period_2               ((uint32_t)0x00000800)
 #define FMC_SDClock_Period_3               ((uint32_t)0x00000C00)
 #define FMC_SDClock_Period_Mask            ((uint32_t)0x00000C00)
-
-#define IS_FMC_SDCLOCK_PERIOD(PERIOD) \
-    (((PERIOD) == FMC_SDClock_Disable) || \
-    ((PERIOD) == FMC_SDClock_Period_2) || \
-    ((PERIOD) == FMC_SDClock_Period_3))
-
 /**
  * @}
  */
@@ -167,11 +126,6 @@
 #define FMC_Read_Burst_Disable             ((uint32_t)0x00000000)
 #define FMC_Read_Burst_Enable              ((uint32_t)0x00001000)
 #define FMC_Read_Burst_Mask                ((uint32_t)0x00001000)
-
-#define IS_FMC_READ_BURST(RBURST) \
-    (((RBURST) == FMC_Read_Burst_Disable) || \
-    ((RBURST) == FMC_Read_Burst_Enable))
-
 /**
  * @}
  */
@@ -184,12 +138,6 @@
 #define FMC_ReadPipe_Delay_1               ((uint32_t)0x00002000)
 #define FMC_ReadPipe_Delay_2               ((uint32_t)0x00004000)
 #define FMC_ReadPipe_Delay_Mask            ((uint32_t)0x00006000)
-
-#define IS_FMC_READPIPE_DELAY(DELAY) \
-    (((DELAY) == FMC_ReadPipe_Delay_0) || \
-    ((DELAY) == FMC_ReadPipe_Delay_1) || \
-    ((DELAY) == FMC_ReadPipe_Delay_2))
-
 /**
  * @}
  */
@@ -205,57 +153,9 @@
 #define FMC_Command_Mode_LoadMode          ((uint32_t)0x00000004)
 #define FMC_Command_Mode_Selfrefresh       ((uint32_t)0x00000005)
 #define FMC_Command_Mode_PowerDown         ((uint32_t)0x00000006)
-
-#define IS_FMC_COMMAND_MODE(COMMAND) \
-    (((COMMAND) == FMC_Command_Mode_normal)      || \
-    ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \
-    ((COMMAND) == FMC_Command_Mode_PALL)        || \
-    ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \
-    ((COMMAND) == FMC_Command_Mode_LoadMode)    || \
-    ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \
-    ((COMMAND) == FMC_Command_Mode_PowerDown))
-
-/**
- * @}
- */
-
-/**
- *  @defgroup FMC_Command_Target
- * @{
- */
-#define FMC_Command_Target_bank2           ((uint32_t)0x00000008)
-#define FMC_Command_Target_bank1           ((uint32_t)0x00000010)
-#define FMC_Command_Target_bank1_2         ((uint32_t)0x00000018)
-
-#define IS_FMC_COMMAND_TARGET(TARGET) \
-    (((TARGET) == FMC_Command_Target_bank1) || \
-    ((TARGET) == FMC_Command_Target_bank2) || \
-    ((TARGET) == FMC_Command_Target_bank1_2))
-
 /**
  * @}
  */
-  
-/**
- * @defgroup FMC_AutoRefresh_Number
- * @{
- */
-#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
-
-/**
- * @}
- */
-
-/**
- * @defgroup FMC_ModeRegister_Definition
- * @{
- */
-#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
-
-/**
- * @}
- */
-
 
 /**
  * @brief  FMC SDRAM Mode definition register defines
@@ -340,8 +240,14 @@ typedef struct SDRAMDriver SDRAMDriver;
  * @note    It could be empty on some architectures.
  */
 typedef struct {
-  uint32_t                  sdcr;
-  uint32_t                  sdtr;
+#if STM32_SDRAM_USE_FSMC_SDRAM1
+  uint32_t                  sdcr1;
+  uint32_t                  sdtr1;
+#endif
+#if STM32_SDRAM_USE_FSMC_SDRAM2
+  uint32_t                  sdcr2;
+  uint32_t                  sdtr2;
+#endif
 } SDRAMConfig;
 
 /**
@@ -349,7 +255,7 @@ typedef struct {
  */
 struct SDRAMDriver {
   /**
-   * @brief   Driver state.
+   * @brief     Driver state.
    */
   sdramstate_t              state;
   /**
@@ -366,13 +272,7 @@ struct SDRAMDriver {
 /* External declarations.                                                    */
 /*===========================================================================*/
 
-#if STM32_SDRAM_USE_FSMC_SDRAM1 && !defined(__DOXYGEN__)
-extern SDRAMDriver SDRAMD1;
-#endif
-
-#if STM32_SDRAM_USE_FSMC_SDRAM2 && !defined(__DOXYGEN__)
-extern SDRAMDriver SDRAMD2;
-#endif
+extern SDRAMDriver SDRAMD;
 
 #ifdef __cplusplus
 extern "C" {
@@ -380,8 +280,6 @@ extern "C" {
   void fsmcSdramInit(void);
   void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
   void fsmcSdramStop(SDRAMDriver *sdramp);
-  void fsmcSdram_WaitReady(void);
-  void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state);
 #ifdef __cplusplus
 }
 #endif