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| author | Fabio Utzig <utzig@utzig.org> | 2016-03-07 12:33:00 -0300 |
|---|---|---|
| committer | Fabio Utzig <utzig@utzig.org> | 2016-03-07 12:33:00 -0300 |
| commit | b67ecdfeca2d1d5289e4c9b577a1940cf8702ab3 (patch) | |
| tree | 9c78c9da3117a04f99d651ad8b774b6de18e4d83 /os/hal | |
| parent | 37ac6a4611ca3625343ef1a17943e66459f825af (diff) | |
| download | ChibiOS-Contrib-b67ecdfeca2d1d5289e4c9b577a1940cf8702ab3.tar.gz ChibiOS-Contrib-b67ecdfeca2d1d5289e4c9b577a1940cf8702ab3.tar.bz2 ChibiOS-Contrib-b67ecdfeca2d1d5289e4c9b577a1940cf8702ab3.zip | |
[KINETIS] Move from main repo to contrib
Diffstat (limited to 'os/hal')
48 files changed, 12611 insertions, 0 deletions
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c new file mode 100644 index 0000000..b803d1f --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c @@ -0,0 +1,127 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ .port = IOPORT1, // PORTA
+ .pads = {
+ /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_UNCONNECTED, /* PTA2*/ PAL_MODE_OUTPUT_PUSHPULL,
+ /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_UNCONNECTED, /* PTA5*/ PAL_MODE_UNCONNECTED,
+ /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
+ /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
+ /*PTA12*/ PAL_MODE_UNCONNECTED, /*PTA13*/ PAL_MODE_UNCONNECTED, /*PTA14*/ PAL_MODE_UNCONNECTED,
+ /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
+ /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_UNCONNECTED,
+ /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
+ /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
+ /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
+ /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT2, // PORTB
+ .pads = {
+ /* PTB0*/ PAL_MODE_ALTERNATIVE_2, /* PTB1*/ PAL_MODE_ALTERNATIVE_2, /* PTB2*/ PAL_MODE_UNCONNECTED,
+ /* PTB3*/ PAL_MODE_UNCONNECTED, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
+ /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_UNCONNECTED,
+ /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
+ /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
+ /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_ALTERNATIVE_3, /*PTB17*/ PAL_MODE_ALTERNATIVE_3,
+ /*PTB18*/ PAL_MODE_UNCONNECTED, /*PTB19*/ PAL_MODE_UNCONNECTED, /*PTB20*/ PAL_MODE_UNCONNECTED,
+ /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
+ /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
+ /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
+ /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT3, // PORTC
+ .pads = {
+ /* PTC0*/ PAL_MODE_UNCONNECTED, /* PTC1*/ PAL_MODE_UNCONNECTED, /* PTC2*/ PAL_MODE_UNCONNECTED,
+ /* PTC3*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTC4*/ PAL_MODE_UNCONNECTED, /* PTC5*/ PAL_MODE_UNCONNECTED,
+ /* PTC6*/ PAL_MODE_UNCONNECTED, /* PTC7*/ PAL_MODE_UNCONNECTED, /* PTC8*/ PAL_MODE_UNCONNECTED,
+ /* PTC9*/ PAL_MODE_UNCONNECTED, /*PTC10*/ PAL_MODE_UNCONNECTED, /*PTC11*/ PAL_MODE_UNCONNECTED,
+ /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
+ /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
+ /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
+ /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
+ /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
+ /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
+ /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT4, // PORTD
+ .pads = {
+ /* PTD0*/ PAL_MODE_UNCONNECTED, /* PTD1*/ PAL_MODE_UNCONNECTED, /* PTD2*/ PAL_MODE_UNCONNECTED,
+ /* PTD3*/ PAL_MODE_UNCONNECTED, /* PTD4*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD5*/ PAL_MODE_UNCONNECTED,
+ /* PTD6*/ PAL_MODE_UNCONNECTED, /* PTD7*/ PAL_MODE_UNCONNECTED, /* PTD8*/ PAL_MODE_UNCONNECTED,
+ /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
+ /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
+ /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
+ /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
+ /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
+ /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
+ /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
+ /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT5, // PORTE
+ .pads = {
+ /* PTE0*/ PAL_MODE_UNCONNECTED, /* PTE1*/ PAL_MODE_UNCONNECTED, /* PTE2*/ PAL_MODE_UNCONNECTED,
+ /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
+ /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
+ /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
+ /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
+ /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
+ /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_UNCONNECTED,
+ /*PTE21*/ PAL_MODE_UNCONNECTED, /*PTE22*/ PAL_MODE_UNCONNECTED, /*PTE23*/ PAL_MODE_UNCONNECTED,
+ /*PTE24*/ PAL_MODE_UNCONNECTED, /*PTE25*/ PAL_MODE_UNCONNECTED, /*PTE26*/ PAL_MODE_UNCONNECTED,
+ /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_UNCONNECTED,
+ /*PTE30*/ PAL_MODE_UNCONNECTED, /*PTE31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ mk20d50_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h new file mode 100644 index 0000000..41ce877 --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h @@ -0,0 +1,40 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Freescale Freedom K20D50M board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_K20D50M
+#define BOARD_NAME "Freescale Freedom K20D50M"
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk new file mode 100644 index 0000000..e09d821 --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c new file mode 100644 index 0000000..f5bd3ac --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c @@ -0,0 +1,127 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ .port = IOPORT1, // PORTA
+ .pads = {
+ /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_ALTERNATIVE_2, /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
+ /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_INPUT_ANALOG, /* PTA5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
+ /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
+ /*PTA12*/ PAL_MODE_INPUT_ANALOG, /*PTA13*/ PAL_MODE_INPUT_ANALOG, /*PTA14*/ PAL_MODE_INPUT_ANALOG,
+ /*PTA15*/ PAL_MODE_INPUT_ANALOG, /*PTA16*/ PAL_MODE_INPUT_ANALOG, /*PTA17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTA18*/ PAL_MODE_INPUT_ANALOG, /*PTA19*/ PAL_MODE_INPUT_ANALOG, /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
+ /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
+ /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
+ /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
+ /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT2, // PORTB
+ .pads = {
+ /* PTB0*/ PAL_MODE_INPUT_ANALOG, /* PTB1*/ PAL_MODE_INPUT_ANALOG, /* PTB2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB3*/ PAL_MODE_INPUT_ANALOG, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
+ /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTB9*/ PAL_MODE_INPUT_ANALOG, /*PTB10*/ PAL_MODE_INPUT_ANALOG, /*PTB11*/ PAL_MODE_INPUT_ANALOG,
+ /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
+ /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_INPUT_ANALOG, /*PTB17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTB18*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB19*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB20*/ PAL_MODE_UNCONNECTED,
+ /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
+ /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
+ /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
+ /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT3, // PORTC
+ .pads = {
+ /* PTC0*/ PAL_MODE_INPUT_ANALOG, /* PTC1*/ PAL_MODE_INPUT_ANALOG, /* PTC2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC3*/ PAL_MODE_INPUT_ANALOG, /* PTC4*/ PAL_MODE_INPUT_ANALOG, /* PTC5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC6*/ PAL_MODE_INPUT_ANALOG, /* PTC7*/ PAL_MODE_INPUT_ANALOG, /* PTC8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTC9*/ PAL_MODE_INPUT_ANALOG, /*PTC10*/ PAL_MODE_INPUT_ANALOG, /*PTC11*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC12*/ PAL_MODE_INPUT_ANALOG, /*PTC13*/ PAL_MODE_INPUT_ANALOG, /*PTC14*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC15*/ PAL_MODE_INPUT_ANALOG, /*PTC16*/ PAL_MODE_INPUT_ANALOG, /*PTC17*/ PAL_MODE_INPUT_ANALOG,
+ /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
+ /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
+ /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
+ /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
+ /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT4, // PORTD
+ .pads = {
+ /* PTD0*/ PAL_MODE_INPUT_ANALOG, /* PTD1*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD3*/ PAL_MODE_INPUT_ANALOG, /* PTD4*/ PAL_MODE_INPUT_ANALOG, /* PTD5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD6*/ PAL_MODE_INPUT_ANALOG, /* PTD7*/ PAL_MODE_INPUT_ANALOG, /* PTD8*/ PAL_MODE_INPUT_ANALOG,
+ /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
+ /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
+ /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
+ /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
+ /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
+ /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
+ /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
+ /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT5, // PORTE
+ .pads = {
+ /* PTE0*/ PAL_MODE_INPUT_ANALOG, /* PTE1*/ PAL_MODE_INPUT_ANALOG, /* PTE2*/ PAL_MODE_INPUT_ANALOG,
+ /* PTE3*/ PAL_MODE_INPUT_ANALOG, /* PTE4*/ PAL_MODE_INPUT_ANALOG, /* PTE5*/ PAL_MODE_INPUT_ANALOG,
+ /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
+ /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
+ /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
+ /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
+ /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE21*/ PAL_MODE_INPUT_ANALOG, /*PTE22*/ PAL_MODE_INPUT_ANALOG, /*PTE23*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE24*/ PAL_MODE_ALTERNATIVE_5, /*PTE25*/ PAL_MODE_ALTERNATIVE_5, /*PTE26*/ PAL_MODE_UNCONNECTED,
+ /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_INPUT_ANALOG,
+ /*PTE30*/ PAL_MODE_INPUT_ANALOG, /*PTE31*/ PAL_MODE_INPUT_ANALOG,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ kl2x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h new file mode 100644 index 0000000..beeeef1 --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h @@ -0,0 +1,44 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Freescale Freedom KL25Z board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_KL25Z
+#define BOARD_NAME "Freescale Freedom KL25Z"
+
+/* External 8 MHz crystal with PLL for 48 MHz core/system clock. */
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk new file mode 100644 index 0000000..9ae0f5e --- /dev/null +++ b/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
diff --git a/os/hal/boards/MCHCK_K20/board.c b/os/hal/boards/MCHCK_K20/board.c new file mode 100644 index 0000000..9d2b698 --- /dev/null +++ b/os/hal/boards/MCHCK_K20/board.c @@ -0,0 +1,126 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ .port = IOPORT1, // PORTA
+ .pads = {
+ /* PTA0*/ PAL_MODE_ALTERNATIVE_7, /* PTA1*/ PAL_MODE_UNCONNECTED, /* PTA2*/ PAL_MODE_UNCONNECTED,
+ /* PTA3*/ PAL_MODE_ALTERNATIVE_7, /* PTA4*/ PAL_MODE_UNCONNECTED, /* PTA5*/ PAL_MODE_UNCONNECTED,
+ /* PTA6*/ PAL_MODE_UNCONNECTED, /* PTA7*/ PAL_MODE_UNCONNECTED, /* PTA8*/ PAL_MODE_UNCONNECTED,
+ /* PTA9*/ PAL_MODE_UNCONNECTED, /*PTA10*/ PAL_MODE_UNCONNECTED, /*PTA11*/ PAL_MODE_UNCONNECTED,
+ /*PTA12*/ PAL_MODE_UNCONNECTED, /*PTA13*/ PAL_MODE_UNCONNECTED, /*PTA14*/ PAL_MODE_UNCONNECTED,
+ /*PTA15*/ PAL_MODE_UNCONNECTED, /*PTA16*/ PAL_MODE_UNCONNECTED, /*PTA17*/ PAL_MODE_UNCONNECTED,
+ /*PTA18*/ PAL_MODE_UNCONNECTED, /*PTA19*/ PAL_MODE_UNCONNECTED, /*PTA20*/ PAL_MODE_UNCONNECTED,
+ /*PTA21*/ PAL_MODE_UNCONNECTED, /*PTA22*/ PAL_MODE_UNCONNECTED, /*PTA23*/ PAL_MODE_UNCONNECTED,
+ /*PTA24*/ PAL_MODE_UNCONNECTED, /*PTA25*/ PAL_MODE_UNCONNECTED, /*PTA26*/ PAL_MODE_UNCONNECTED,
+ /*PTA27*/ PAL_MODE_UNCONNECTED, /*PTA28*/ PAL_MODE_UNCONNECTED, /*PTA29*/ PAL_MODE_UNCONNECTED,
+ /*PTA30*/ PAL_MODE_UNCONNECTED, /*PTA31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT2, // PORTB
+ .pads = {
+ /* PTB0*/ PAL_MODE_UNCONNECTED, /* PTB1*/ PAL_MODE_UNCONNECTED, /* PTB2*/ PAL_MODE_UNCONNECTED,
+ /* PTB3*/ PAL_MODE_UNCONNECTED, /* PTB4*/ PAL_MODE_UNCONNECTED, /* PTB5*/ PAL_MODE_UNCONNECTED,
+ /* PTB6*/ PAL_MODE_UNCONNECTED, /* PTB7*/ PAL_MODE_UNCONNECTED, /* PTB8*/ PAL_MODE_UNCONNECTED,
+ /* PTB9*/ PAL_MODE_UNCONNECTED, /*PTB10*/ PAL_MODE_UNCONNECTED, /*PTB11*/ PAL_MODE_UNCONNECTED,
+ /*PTB12*/ PAL_MODE_UNCONNECTED, /*PTB13*/ PAL_MODE_UNCONNECTED, /*PTB14*/ PAL_MODE_UNCONNECTED,
+ /*PTB15*/ PAL_MODE_UNCONNECTED, /*PTB16*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB17*/ PAL_MODE_UNCONNECTED,
+ /*PTB18*/ PAL_MODE_UNCONNECTED, /*PTB19*/ PAL_MODE_UNCONNECTED, /*PTB20*/ PAL_MODE_UNCONNECTED,
+ /*PTB21*/ PAL_MODE_UNCONNECTED, /*PTB22*/ PAL_MODE_UNCONNECTED, /*PTB23*/ PAL_MODE_UNCONNECTED,
+ /*PTB24*/ PAL_MODE_UNCONNECTED, /*PTB25*/ PAL_MODE_UNCONNECTED, /*PTB26*/ PAL_MODE_UNCONNECTED,
+ /*PTB27*/ PAL_MODE_UNCONNECTED, /*PTB28*/ PAL_MODE_UNCONNECTED, /*PTB29*/ PAL_MODE_UNCONNECTED,
+ /*PTB30*/ PAL_MODE_UNCONNECTED, /*PTB31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT3, // PORTC
+ .pads = {
+ /* PTC0*/ PAL_MODE_UNCONNECTED, /* PTC1*/ PAL_MODE_UNCONNECTED, /* PTC2*/ PAL_MODE_UNCONNECTED,
+ /* PTC3*/ PAL_MODE_UNCONNECTED, /* PTC4*/ PAL_MODE_UNCONNECTED, /* PTC5*/ PAL_MODE_UNCONNECTED,
+ /* PTC6*/ PAL_MODE_UNCONNECTED, /* PTC7*/ PAL_MODE_UNCONNECTED, /* PTC8*/ PAL_MODE_UNCONNECTED,
+ /* PTC9*/ PAL_MODE_UNCONNECTED, /*PTC10*/ PAL_MODE_UNCONNECTED, /*PTC11*/ PAL_MODE_UNCONNECTED,
+ /*PTC12*/ PAL_MODE_UNCONNECTED, /*PTC13*/ PAL_MODE_UNCONNECTED, /*PTC14*/ PAL_MODE_UNCONNECTED,
+ /*PTC15*/ PAL_MODE_UNCONNECTED, /*PTC16*/ PAL_MODE_UNCONNECTED, /*PTC17*/ PAL_MODE_UNCONNECTED,
+ /*PTC18*/ PAL_MODE_UNCONNECTED, /*PTC19*/ PAL_MODE_UNCONNECTED, /*PTC20*/ PAL_MODE_UNCONNECTED,
+ /*PTC21*/ PAL_MODE_UNCONNECTED, /*PTC22*/ PAL_MODE_UNCONNECTED, /*PTC23*/ PAL_MODE_UNCONNECTED,
+ /*PTC24*/ PAL_MODE_UNCONNECTED, /*PTC25*/ PAL_MODE_UNCONNECTED, /*PTC26*/ PAL_MODE_UNCONNECTED,
+ /*PTC27*/ PAL_MODE_UNCONNECTED, /*PTC28*/ PAL_MODE_UNCONNECTED, /*PTC29*/ PAL_MODE_UNCONNECTED,
+ /*PTC30*/ PAL_MODE_UNCONNECTED, /*PTC31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT4, // PORTD
+ .pads = {
+ /* PTD0*/ PAL_MODE_UNCONNECTED, /* PTD1*/ PAL_MODE_UNCONNECTED, /* PTD2*/ PAL_MODE_UNCONNECTED,
+ /* PTD3*/ PAL_MODE_UNCONNECTED, /* PTD4*/ PAL_MODE_UNCONNECTED, /* PTD5*/ PAL_MODE_UNCONNECTED,
+ /* PTD6*/ PAL_MODE_UNCONNECTED, /* PTD7*/ PAL_MODE_UNCONNECTED, /* PTD8*/ PAL_MODE_UNCONNECTED,
+ /* PTD9*/ PAL_MODE_UNCONNECTED, /*PTD10*/ PAL_MODE_UNCONNECTED, /*PTD11*/ PAL_MODE_UNCONNECTED,
+ /*PTD12*/ PAL_MODE_UNCONNECTED, /*PTD13*/ PAL_MODE_UNCONNECTED, /*PTD14*/ PAL_MODE_UNCONNECTED,
+ /*PTD15*/ PAL_MODE_UNCONNECTED, /*PTD16*/ PAL_MODE_UNCONNECTED, /*PTD17*/ PAL_MODE_UNCONNECTED,
+ /*PTD18*/ PAL_MODE_UNCONNECTED, /*PTD19*/ PAL_MODE_UNCONNECTED, /*PTD20*/ PAL_MODE_UNCONNECTED,
+ /*PTD21*/ PAL_MODE_UNCONNECTED, /*PTD22*/ PAL_MODE_UNCONNECTED, /*PTD23*/ PAL_MODE_UNCONNECTED,
+ /*PTD24*/ PAL_MODE_UNCONNECTED, /*PTD25*/ PAL_MODE_UNCONNECTED, /*PTD26*/ PAL_MODE_UNCONNECTED,
+ /*PTD27*/ PAL_MODE_UNCONNECTED, /*PTD28*/ PAL_MODE_UNCONNECTED, /*PTD29*/ PAL_MODE_UNCONNECTED,
+ /*PTD30*/ PAL_MODE_UNCONNECTED, /*PTD31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ .port = IOPORT5, // PORTE
+ .pads = {
+ /* PTE0*/ PAL_MODE_UNCONNECTED, /* PTE1*/ PAL_MODE_UNCONNECTED, /* PTE2*/ PAL_MODE_UNCONNECTED,
+ /* PTE3*/ PAL_MODE_UNCONNECTED, /* PTE4*/ PAL_MODE_UNCONNECTED, /* PTE5*/ PAL_MODE_UNCONNECTED,
+ /* PTE6*/ PAL_MODE_UNCONNECTED, /* PTE7*/ PAL_MODE_UNCONNECTED, /* PTE8*/ PAL_MODE_UNCONNECTED,
+ /* PTE9*/ PAL_MODE_UNCONNECTED, /*PTE10*/ PAL_MODE_UNCONNECTED, /*PTE11*/ PAL_MODE_UNCONNECTED,
+ /*PTE12*/ PAL_MODE_UNCONNECTED, /*PTE13*/ PAL_MODE_UNCONNECTED, /*PTE14*/ PAL_MODE_UNCONNECTED,
+ /*PTE15*/ PAL_MODE_UNCONNECTED, /*PTE16*/ PAL_MODE_UNCONNECTED, /*PTE17*/ PAL_MODE_UNCONNECTED,
+ /*PTE18*/ PAL_MODE_UNCONNECTED, /*PTE19*/ PAL_MODE_UNCONNECTED, /*PTE20*/ PAL_MODE_UNCONNECTED,
+ /*PTE21*/ PAL_MODE_UNCONNECTED, /*PTE22*/ PAL_MODE_UNCONNECTED, /*PTE23*/ PAL_MODE_UNCONNECTED,
+ /*PTE24*/ PAL_MODE_UNCONNECTED, /*PTE25*/ PAL_MODE_UNCONNECTED, /*PTE26*/ PAL_MODE_UNCONNECTED,
+ /*PTE27*/ PAL_MODE_UNCONNECTED, /*PTE28*/ PAL_MODE_UNCONNECTED, /*PTE29*/ PAL_MODE_UNCONNECTED,
+ /*PTE30*/ PAL_MODE_UNCONNECTED, /*PTE31*/ PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+ mk20d50_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/MCHCK_K20/board.h b/os/hal/boards/MCHCK_K20/board.h new file mode 100644 index 0000000..ed22891 --- /dev/null +++ b/os/hal/boards/MCHCK_K20/board.h @@ -0,0 +1,42 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for MCHCL K20 board with MX20DX128 processor.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MCHCK_K20_MX20DX128
+#define BOARD_NAME "MCHCK K20 MX20DX128"
+
+#define GPIOB_LED 16
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/MCHCK_K20/board.mk b/os/hal/boards/MCHCK_K20/board.mk new file mode 100644 index 0000000..dbf42c3 --- /dev/null +++ b/os/hal/boards/MCHCK_K20/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/MCHCK_K20/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/MCHCK_K20
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.c b/os/hal/boards/PJRC_TEENSY_3/board.c new file mode 100644 index 0000000..68b13d0 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3/board.c @@ -0,0 +1,182 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ /*
+ * PORTA setup.
+ *
+ * PTA4 - PIN33
+ * PTA5 - PIN24
+ * PTA12 - PIN3
+ * PTA13 - PIN4
+ */
+ .port = IOPORT1,
+ .pads = {
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTB setup.
+ *
+ * PTB0 - PIN16
+ * PTB1 - PIN17
+ * PTB2 - PIN19
+ * PTB3 - PIN18
+ * PTB16 - PIN0 - UART0_TX
+ * PTB17 - PIN1 - UART0_RX
+ * PTB18 - PIN32
+ * PTB19 - PIN25
+ */
+ .port = IOPORT2,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTC setup.
+ *
+ * PTC0 - PIN15
+ * PTC1 - PIN22
+ * PTC2 - PIN23
+ * PTC3 - PIN9
+ * PTC4 - PIN10
+ * PTC5 - PIN13
+ * PTC6 - PIN11
+ * PTC7 - PIN12
+ * PTC8 - PIN28
+ * PTC9 - PIN27
+ * PTC10 - PIN29
+ * PTC11 - PIN30
+ */
+ .port = IOPORT3,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTD setup.
+ *
+ * PTD0 - PIN2
+ * PTD1 - PIN14
+ * PTD2 - PIN7
+ * PTD3 - PIN8
+ * PTD4 - PIN6
+ * PTD5 - PIN20
+ * PTD6 - PIN21
+ * PTD7 - PIN5
+ */
+ .port = IOPORT4,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTE setup.
+ *
+ * PTE0 - PIN31
+ * PTE1 - PIN26
+ */
+ .port = IOPORT5,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ mk20d50_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.h b/os/hal/boards/PJRC_TEENSY_3/board.h new file mode 100644 index 0000000..4f7ecdb --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3/board.h @@ -0,0 +1,213 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.0 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3
+#define BOARD_NAME "PJRC Teensy 3.0"
+
+/* External 16 MHz crystal with PLL for 48 MHz core/system clock. */
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_XTAL_FREQUENCY 16000000UL
+
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0 0
+#define PORTA_PIN1 1
+#define PORTA_PIN2 2
+#define PORTA_PIN3 3
+#define PORTA_TEENSY_PIN33 4
+#define PORTA_TEENSY_PIN24 5
+#define PORTA_PIN6 6
+#define PORTA_PIN7 7
+#define PORTA_PIN8 8
+#define PORTA_PIN9 9
+#define PORTA_PIN10 10
+#define PORTA_PIN11 11
+#define PORTA_TEENSY_PIN3 12
+#define PORTA_TEENSY_PIN4 13
+#define PORTA_PIN14 14
+#define PORTA_PIN15 15
+#define PORTA_PIN16 16
+#define PORTA_PIN17 17
+#define PORTA_PIN18 18
+#define PORTA_PIN19 19
+#define PORTA_PIN20 20
+#define PORTA_PIN21 21
+#define PORTA_PIN22 22
+#define PORTA_PIN23 23
+#define PORTA_PIN24 24
+#define PORTA_PIN25 25
+#define PORTA_PIN26 26
+#define PORTA_PIN27 27
+#define PORTA_PIN28 28
+#define PORTA_PIN29 29
+#define PORTA_PIN30 30
+#define PORTA_PIN31 31
+
+#define PORTB_TEENSY_PIN16 0
+#define PORTB_TEENSY_PIN17 1
+#define PORTB_TEENSY_PIN19 2
+#define PORTB_TEENSY_PIN18 3
+#define PORTB_PIN4 4
+#define PORTB_PIN5 5
+#define PORTB_PIN6 6
+#define PORTB_PIN7 7
+#define PORTB_PIN8 8
+#define PORTB_PIN9 9
+#define PORTB_PIN10 10
+#define PORTB_PIN11 11
+#define PORTB_PIN12 12
+#define PORTB_PIN13 13
+#define PORTB_PIN14 14
+#define PORTB_PIN15 15
+#define PORTB_TEENSY_PIN0 16
+#define PORTB_TEENSY_PIN1 17
+#define PORTB_TEENSY_PIN32 18
+#define PORTB_TEENSY_PIN25 19
+#define PORTB_PIN20 20
+#define PORTB_PIN21 21
+#define PORTB_PIN22 22
+#define PORTB_PIN23 23
+#define PORTB_PIN24 24
+#define PORTB_PIN25 25
+#define PORTB_PIN26 26
+#define PORTB_PIN27 27
+#define PORTB_PIN28 28
+#define PORTB_PIN29 29
+#define PORTB_PIN30 30
+#define PORTB_PIN31 31
+
+#define PORTC_TEENSY_PIN15 0
+#define PORTC_TEENSY_PIN22 1
+#define PORTC_TEENSY_PIN23 2
+#define PORTC_TEENSY_PIN9 3
+#define PORTC_TEENSY_PIN10 4
+#define PORTC_TEENSY_PIN13 5
+#define PORTC_TEENSY_PIN11 6
+#define PORTC_TEENSY_PIN12 7
+#define PORTC_TEENSY_PIN28 8
+#define PORTC_TEENSY_PIN27 9
+#define PORTC_TEENSY_PIN29 10
+#define PORTC_TEENSY_PIN30 11
+#define PORTC_PIN12 12
+#define PORTC_PIN13 13
+#define PORTC_PIN14 14
+#define PORTC_PIN15 15
+#define PORTC_PIN16 16
+#define PORTC_PIN17 17
+#define PORTC_PIN18 18
+#define PORTC_PIN19 19
+#define PORTC_PIN20 20
+#define PORTC_PIN21 21
+#define PORTC_PIN22 22
+#define PORTC_PIN23 23
+#define PORTC_PIN24 24
+#define PORTC_PIN25 25
+#define PORTC_PIN26 26
+#define PORTC_PIN27 27
+#define PORTC_PIN28 28
+#define PORTC_PIN29 29
+#define PORTC_PIN30 30
+#define PORTC_PIN31 31
+
+#define PORTD_TEENSY_PIN2 0
+#define PORTD_TEENSY_PIN14 1
+#define PORTD_TEENSY_PIN7 2
+#define PORTD_TEENSY_PIN8 3
+#define PORTD_TEENSY_PIN6 4
+#define PORTD_TEENSY_PIN20 5
+#define PORTD_TEENSY_PIN21 6
+#define PORTD_TEENSY_PIN5 7
+#define PORTD_PIN8 8
+#define PORTD_PIN9 9
+#define PORTD_PIN10 10
+#define PORTD_PIN11 11
+#define PORTD_PIN12 12
+#define PORTD_PIN13 13
+#define PORTD_PIN14 14
+#define PORTD_PIN15 15
+#define PORTD_PIN16 16
+#define PORTD_PIN17 17
+#define PORTD_PIN18 18
+#define PORTD_PIN19 19
+#define PORTD_PIN20 20
+#define PORTD_PIN21 21
+#define PORTD_PIN22 22
+#define PORTD_PIN23 23
+#define PORTD_PIN24 24
+#define PORTD_PIN25 25
+#define PORTD_PIN26 26
+#define PORTD_PIN27 27
+#define PORTD_PIN28 28
+#define PORTD_PIN29 29
+#define PORTD_PIN30 30
+#define PORTD_PIN31 31
+
+#define PORTE_TEENSY_PIN31 0
+#define PORTE_TEENSY_PIN26 1
+#define PORTE_PIN2 2
+#define PORTE_PIN3 3
+#define PORTE_PIN4 4
+#define PORTE_PIN5 5
+#define PORTE_PIN6 6
+#define PORTE_PIN7 7
+#define PORTE_PIN8 8
+#define PORTE_PIN9 9
+#define PORTE_PIN10 10
+#define PORTE_PIN11 11
+#define PORTE_PIN12 12
+#define PORTE_PIN13 13
+#define PORTE_PIN14 14
+#define PORTE_PIN15 15
+#define PORTE_PIN16 16
+#define PORTE_PIN17 17
+#define PORTE_PIN18 18
+#define PORTE_PIN19 19
+#define PORTE_PIN20 20
+#define PORTE_PIN21 21
+#define PORTE_PIN22 22
+#define PORTE_PIN23 23
+#define PORTE_PIN24 24
+#define PORTE_PIN25 25
+#define PORTE_PIN26 26
+#define PORTE_PIN27 27
+#define PORTE_PIN28 28
+#define PORTE_PIN29 29
+#define PORTE_PIN30 30
+#define PORTE_PIN31 31
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/PJRC_TEENSY_3/board.mk b/os/hal/boards/PJRC_TEENSY_3/board.mk new file mode 100644 index 0000000..d19a654 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/PJRC_TEENSY_3/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/PJRC_TEENSY_3
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.c b/os/hal/ports/KINETIS/K20x/gpt_lld.c new file mode 100644 index 0000000..09d759b --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/gpt_lld.c @@ -0,0 +1,372 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/gpt_lld.c
+ * @brief KINETIS GPT subsystem low level driver source.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define KINETIS_PIT0_HANDLER VectorB8
+#define KINETIS_PIT1_HANDLER VectorBC
+#define KINETIS_PIT2_HANDLER VectorC0
+#define KINETIS_PIT3_HANDLER VectorC4
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief GPTD1 driver identifier.
+ * @note The driver GPTD1 allocates the complex timer PIT0 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT0 || defined(__DOXYGEN__)
+GPTDriver GPTD1;
+#endif
+
+/**
+ * @brief GPTD2 driver identifier.
+ * @note The driver GPTD2 allocates the timer PIT1 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT1 || defined(__DOXYGEN__)
+GPTDriver GPTD2;
+#endif
+
+/**
+ * @brief GPTD3 driver identifier.
+ * @note The driver GPTD3 allocates the timer PIT2 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT2 || defined(__DOXYGEN__)
+GPTDriver GPTD3;
+#endif
+
+/**
+ * @brief GPTD4 driver identifier.
+ * @note The driver GPTD4 allocates the timer PIT3 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT3 || defined(__DOXYGEN__)
+GPTDriver GPTD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Shared IRQ handler.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ */
+static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
+
+ /* Clear the interrupt */
+ gptp->channel->TFLG |= PIT_TCTRL_TIE;
+
+ if (gptp->state == GPT_ONESHOT) {
+ gptp->state = GPT_READY; /* Back in GPT_READY state. */
+ gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
+ }
+ gptp->config->callback(gptp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_GPT_USE_PIT0
+#if !defined(KINETIS_PIT0_HANDLER)
+#error "KINETIS_PIT0_HANDLER not defined"
+#endif
+/**
+ * @brief PIT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT0_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ gpt_lld_serve_interrupt(&GPTD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT0 */
+
+#if KINETIS_GPT_USE_PIT1
+#if !defined(KINETIS_PIT1_HANDLER)
+#error "KINETIS_PIT1_HANDLER not defined"
+#endif
+/**
+ * @brief PIT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ gpt_lld_serve_interrupt(&GPTD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT1 */
+
+#if KINETIS_GPT_USE_PIT2
+#if !defined(KINETIS_PIT2_HANDLER)
+#error "KINETIS_PIT2_HANDLER not defined"
+#endif
+/**
+ * @brief PIT2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ gpt_lld_serve_interrupt(&GPTD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT2 */
+
+#if KINETIS_GPT_USE_PIT3
+#if !defined(KINETIS_PIT3_HANDLER)
+#error "KINETIS_PIT3_HANDLER not defined"
+#endif
+/**
+ * @brief PIT3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ gpt_lld_serve_interrupt(&GPTD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT3 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level GPT driver initialization.
+ *
+ * @notapi
+ */
+void gpt_lld_init(void) {
+
+#if KINETIS_GPT_USE_PIT0
+ /* Driver initialization.*/
+ GPTD1.channel = &PIT->CHANNEL[0];
+ gptObjectInit(&GPTD1);
+#endif
+
+#if KINETIS_GPT_USE_PIT1
+ /* Driver initialization.*/
+ GPTD2.channel = &PIT->CHANNEL[1];
+ gptObjectInit(&GPTD2);
+#endif
+
+#if KINETIS_GPT_USE_PIT2
+ /* Driver initialization.*/
+ GPTD3.channel = &PIT->CHANNEL[2];
+ gptObjectInit(&GPTD3);
+#endif
+
+#if KINETIS_GPT_USE_PIT3
+ /* Driver initialization.*/
+ GPTD4.channel = &PIT->CHANNEL[3];
+ gptObjectInit(&GPTD4);
+#endif
+}
+
+/**
+ * @brief Configures and activates the GPT peripheral.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_start(GPTDriver *gptp) {
+ uint16_t psc;
+
+ if (gptp->state == GPT_STOP) {
+ /* Clock activation.*/
+ SIM->SCGC6 |= SIM_SCGC6_PIT;
+ gptp->clock = KINETIS_SYSCLK_FREQUENCY;
+
+#if KINETIS_GPT_USE_PIT0
+ if (&GPTD1 == gptp) {
+ nvicEnableVector(PITChannel0_IRQn, KINETIS_GPT_PIT0_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT1
+ if (&GPTD2 == gptp) {
+ nvicEnableVector(PITChannel1_IRQn, KINETIS_GPT_PIT1_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT2
+ if (&GPTD3 == gptp) {
+ nvicEnableVector(PITChannel2_IRQn, KINETIS_GPT_PIT2_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT3
+ if (&GPTD4 == gptp) {
+ nvicEnableVector(PITChannel3_IRQn, KINETIS_GPT_PIT3_IRQ_PRIORITY);
+ }
+#endif
+
+ }
+
+ /* Prescaler value calculation.*/
+ psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
+ osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
+ "invalid frequency");
+
+ /* Enable the PIT */
+ PIT->MCR = 0;
+}
+
+/**
+ * @brief Deactivates the GPT peripheral.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop(GPTDriver *gptp) {
+
+ if (gptp->state == GPT_READY) {
+ SIM->SCGC6 &= ~SIM_SCGC6_PIT;
+
+ /* Disable the channel */
+ gptp->channel->TCTRL = 0;
+
+ /* Clear pending interrupts */
+ gptp->channel->TFLG |= PIT_TFLG_TIF;
+
+#if KINETIS_GPT_USE_PIT0
+ if (&GPTD1 == gptp) {
+ nvicDisableVector(PITChannel0_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT1
+ if (&GPTD2 == gptp) {
+ nvicDisableVector(PITChannel1_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT2
+ if (&GPTD3 == gptp) {
+ nvicDisableVector(PITChannel2_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT3
+ if (&GPTD4 == gptp) {
+ nvicDisableVector(PITChannel3_IRQn);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts the timer in continuous mode.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ * @param[in] interval period in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
+
+ /* Clear pending interrupts */
+ gptp->channel->TFLG |= PIT_TFLG_TIF;
+
+ /* Set the interval */
+ gptp->channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
+
+ /* Start the timer */
+ gptp->channel->TCTRL |= PIT_TCTRL_TIE | PIT_TCTRL_TEN;
+}
+
+/**
+ * @brief Stops the timer.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop_timer(GPTDriver *gptp) {
+
+ /* Stop the timer */
+ gptp->channel->TCTRL = 0;
+}
+
+/**
+ * @brief Starts the timer in one shot mode and waits for completion.
+ * @details This function specifically polls the timer waiting for completion
+ * in order to not have extra delays caused by interrupt servicing,
+ * this function is only recommended for short delays.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ * @param[in] interval time interval in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
+ struct PIT_CHANNEL *channel = gptp->channel;
+
+ /* Disable timer and disable interrupts */
+ channel->TCTRL = 0;
+
+ /* Clear the interrupt flag */
+ channel->TFLG |= PIT_TFLG_TIF;
+
+ /* Set the interval */
+ channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
+
+ /* Enable Timer but keep interrupts disabled */
+ channel->TCTRL = PIT_TCTRL_TEN;
+
+ /* Wait for the interrupt flag to be set */
+ while (!(channel->TFLG & PIT_TFLG_TIF))
+ ;
+
+ /* Disable timer and disable interrupts */
+ channel->TCTRL = 0;
+}
+
+#endif /* HAL_USE_GPT */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/gpt_lld.h b/os/hal/ports/KINETIS/K20x/gpt_lld.h new file mode 100644 index 0000000..0e72309 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/gpt_lld.h @@ -0,0 +1,292 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/gpt_lld.h
+ * @brief KINETIS GPT subsystem low level driver header.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#ifndef _GPT_LLD_H_
+#define _GPT_LLD_H_
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief GPTD1 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT0) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT0 FALSE
+#endif
+
+/**
+ * @brief GPTD2 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT1) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT1 FALSE
+#endif
+
+/**
+ * @brief GPTD3 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT2) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT2 FALSE
+#endif
+
+/**
+ * @brief GPTD4 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD4 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT3) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT3 FALSE
+#endif
+
+/**
+ * @brief GPTD1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT0_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT1_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT2_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT3_IRQ_PRIORITY 7
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT0
+#error "PIT0 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT1
+#error "PIT1 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT2
+#error "PIT2 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT3
+#error "PIT3 not present in the selected device"
+#endif
+
+#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
+ !KINETIS_GPT_USE_PIT2 && !KINETIS_GPT_USE_PIT3
+#error "GPT driver activated but no PIT peripheral assigned"
+#endif
+
+#if KINETIS_GPT_USE_PIT0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT0"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT1"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT2"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT3"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief GPT frequency type.
+ */
+typedef uint32_t gptfreq_t;
+
+/**
+ * @brief GPT counter type.
+ */
+typedef uint32_t gptcnt_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ gptfreq_t frequency;
+ /**
+ * @brief Timer callback pointer.
+ * @note This callback is invoked on GPT counter events.
+ * @note This callback can be set to @p NULL but in that case the
+ * one-shot mode cannot be used.
+ */
+ gptcallback_t callback;
+ /* End of the mandatory fields.*/
+} GPTConfig;
+
+/**
+ * @brief Structure representing a GPT driver.
+ */
+struct GPTDriver {
+ /**
+ * @brief Driver state.
+ */
+ gptstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const GPTConfig *config;
+#if defined(GPT_DRIVER_EXT_FIELDS)
+ GPT_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Timer base clock.
+ */
+ uint32_t clock;
+ /**
+ * @brief Channel structure in PIT registers block.
+ */
+ struct PIT_CHANNEL *channel;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the interval of GPT peripheral.
+ * @details This function changes the interval of a running GPT unit.
+ * @pre The GPT unit must be running in continuous mode.
+ * @post The GPT unit interval is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @param[in] interval new cycle time in timer ticks
+ *
+ * @notapi
+ */
+#define gpt_lld_change_interval(gptp, interval) \
+ ((gptp)->channel->LDVAL = (uint32_t)((interval)))
+
+/**
+ * @brief Returns the interval of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current interval.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_interval(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].LDVAL)
+
+/**
+ * @brief Returns the counter value of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ * @note The nature of the counter is not defined, it may count upward
+ * or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current counter value.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].CVAL)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_GPT_USE_PIT0 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD1;
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD2;
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD3;
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void gpt_lld_init(void);
+ void gpt_lld_start(GPTDriver *gptp);
+ void gpt_lld_stop(GPTDriver *gptp);
+ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
+ void gpt_lld_stop_timer(GPTDriver *gptp);
+ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_GPT */
+
+#endif /* _GPT_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c new file mode 100644 index 0000000..1e10241 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/hal_lld.c @@ -0,0 +1,204 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/hal_lld.c
+ * @brief HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used, section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ * @todo Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+}
+
+/**
+ * @brief MK20D5 clock initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ * @todo This function needs to be more generic.
+ *
+ * @special
+ */
+void mk20d50_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ int ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ int i;
+#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+
+ /* Disable the watchdog */
+ WDOG->UNLOCK = 0xC520;
+ WDOG->UNLOCK = 0xD928;
+ WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI */
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] = 0;
+ PORTA->PCR[19] = 0;
+
+ /*
+ * Start in FEI mode
+ */
+
+ /* Disable capacitors for crystal */
+ OSC->CR = 0;
+
+ /* TODO: need to add more flexible calculation, specially regarding
+ * divisors which may not be available depending on the XTAL
+ * frequency, which would required other registers to be modified.
+ */
+ /* Enable OSC, low power mode */
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
+ if (KINETIS_XTAL_FREQUENCY > 8000000)
+ MCG->C2 |= MCG_C2_RANGE0(2);
+ else
+ MCG->C2 |= MCG_C2_RANGE0(1);
+
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+ /* Wait for crystal oscillator to begin */
+ while (!(MCG->S & MCG_S_OSCINIT0));
+
+ /* Wait for the FLL to use the oscillator */
+ while (MCG->S & MCG_S_IREFST);
+
+ /* Wait for the MCGOUTCLK to use the oscillator */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+ /*
+ * Now in FBE mode
+ */
+
+ /* Config PLL input for 2 MHz */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY / 2000000) - 1);
+
+ /* Config PLL for 96 MHz output */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+ /* Wait for PLL to start using crystal as its input */
+ while (!(MCG->S & MCG_S_PLLST));
+
+ /* Wait for PLL to lock */
+ while (!(MCG->S & MCG_S_LOCK0));
+
+ /*
+ * Now in PBE mode
+ */
+
+ /* Switch to PLL as clock source */
+ MCG->C1 = MCG_C1_CLKS(0);
+
+ /* Wait for PLL clock to be used */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+ /*
+ * Now in PEE mode
+ */
+#endif /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.h b/os/hal/ports/KINETIS/K20x/hal_lld.h new file mode 100644 index 0000000..3544797 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/hal_lld.h @@ -0,0 +1,269 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.h
+ * @brief Kinetis KL2x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "mk20d5.h"
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
+ * @note The allowed range is 1...16.
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV1 2
+#endif
+
+/**
+ * @brief Additional clock divider bus/flash clocks (OUTDIV4).
+ * @note The allowed range is 1...8.
+ * @note This divider is on top of the OUTDIV1 divider.
+ * @note The default value is calculated for 24 MHz bus/flash clocks
+ * from a 96 MHz PLL output and 48 MHz core/system clock.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV4 2
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/**
+ * @brief MCU bus/flash clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#endif
+
+/**
+ * @brief UART0 clock frequency.
+ * @note The default value is based on 96 MHz PLL/2 source.
+ * If you use a different source, such as the FLL,
+ * you must set this properly.
+ */
+#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+/**
+ * @brief UART0 clock source.
+ * @note The default value is to use PLL/2 or FLL source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+#error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+#error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+#error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+#error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
+ KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
+#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
+ KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
+#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void mk20d50_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/kinetis_registry.h b/os/hal/ports/KINETIS/K20x/kinetis_registry.h new file mode 100644 index 0000000..024a424 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/kinetis_registry.h @@ -0,0 +1,58 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/kinetis_registry.h
+ * @brief KL2x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _KINETIS_REGISTRY_H_
+#define _KINETIS_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name KL2x capabilities
+ * @{
+ */
+/* EXT attributes.*/
+
+#define KINETIS_PORTA_IRQ_VECTOR VectorE0
+#define KINETIS_PORTB_IRQ_VECTOR VectorE4
+#define KINETIS_PORTC_IRQ_VECTOR VectorE8
+#define KINETIS_PORTD_IRQ_VECTOR VectorEC
+#define KINETIS_PORTE_IRQ_VECTOR VectorF0
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector98
+
+/* I2C attributes.*/
+#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+
+/* USB attributes */
+#define KINETIS_USB_IRQ_VECTOR VectorCC
+
+/** @} */
+
+#endif /* _KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/mk20d5.h b/os/hal/ports/KINETIS/K20x/mk20d5.h new file mode 100644 index 0000000..aa70723 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/mk20d5.h @@ -0,0 +1,2394 @@ +/* + * Copyright (C) 2014 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _MK20D5_H_ +#define _MK20D5_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + InitialSP_IRQn = -15, + InitialPC_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** K20x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + DMAError_IRQn = 4, + DMA_IRQn = 5, + FlashMemComplete_IRQn = 6, + FlashMemReadCollision_IRQn = 7, + LowVoltageWarning_IRQn = 8, + LLWU_IRQn = 9, + WDOG_IRQn = 10, + I2C0_IRQn = 11, + SPI0_IRQn = 12, + I2S0_IRQn = 13, + I2S1_IRQn = 14, + UART0LON_IRQn = 15, + UART0Status_IRQn = 16, + UART0Error_IRQn = 17, + UART1Status_IRQn = 18, + UART1Error_IRQn = 19, + UART2Status_IRQn = 20, + UART2Error_IRQn = 21, + ADC0_IRQn = 22, + CMP0_IRQn = 23, + CMP1_IRQn = 24, + FTM0_IRQn = 25, + FTM1_IRQn = 26, + CMT_IRQn = 27, + RTCAlarm_IRQn = 28, + RTCSeconds_IRQn = 29, + PITChannel0_IRQn = 30, + PITChannel1_IRQn = 31, + PITChannel2_IRQn = 32, + PITChannel3_IRQn = 33, + PDB_IRQn = 34, + USB_OTG_IRQn = 35, + USBChargerDetect_IRQn = 36, + TSI_IRQn = 37, + MCG_IRQn = 38, + LowPowerTimer_IRQn = 39, + PINA_IRQn = 40, + PINB_IRQn = 41, + PINC_IRQn = 42, + PIND_IRQn = 43, + PINE_IRQn = 44, + SoftInitInt_IRQn = 45, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief K20x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __FPU_PRESENT 0 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __I uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + __IO uint32_t CLKDIV2; + __I uint32_t FCFG1; + __I uint32_t FCFG2; + __I uint32_t UIDH; + __I uint32_t UIDMH; + __I uint32_t UIDML; + __I uint32_t UIDL; +} SIM_TypeDef; + +typedef struct +{ + __IO uint8_t PE1; + __IO uint8_t PE2; + __IO uint8_t PE3; + __IO uint8_t PE4; + __IO uint8_t ME; + __IO uint8_t F1; + __IO uint8_t F2; + __I uint8_t F3; + __IO uint8_t FILT1; + __IO uint8_t FILT2; +} LLWU_TypeDef; + +typedef struct +{ + __IO uint32_t PCR[32]; + __O uint32_t GPCLR; + __O uint32_t GPCHR; + uint32_t RESERVED0[6]; + __IO uint32_t ISFR; +} PORT_TypeDef; + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __I uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; +} MCG_TypeDef; + +typedef struct +{ + __IO uint8_t CR; +} OSC_TypeDef; + +typedef struct { + uint32_t SADDR; /* TCD Source Address */ + uint16_t SOFF; /* TCD Signed Source Address Offset */ + uint16_t ATTR; /* TCD Transfer Attributes */ + union { + uint32_t NBYTES_MLNO; /* TCD Minor Byte Count (Minor Loop Disabled) */ + uint32_t NBYTES_MLOFFNO; /* TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ + uint32_t NBYTES_MLOFFYES; /* TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ + }; + uint32_t SLAST; /* TCD Last Source Address Adjustment */ + uint32_t DADDR; /* TCD Destination Address */ + uint16_t DOFF; /* TCD Signed Destination Address Offset */ + union { + uint16_t CITER_ELINKNO; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ + uint16_t CITER_ELINKYES; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ + }; + uint32_t DLASTSGA; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t CSR; /* TCD Control and Status */ + union { + uint16_t BITER_ELINKNO; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ + uint16_t BITER_ELINKYES; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ + }; +} DMA_TCD_TypeDef; + +/** DMA - Peripheral register structure */ +typedef struct { + __IO uint32_t CR; /* Control Register */ + __IO uint32_t ES; /* Error Status Register */ + __IO uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /* Enable Request Register */ + __IO uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /* Enable Error Interrupt Register */ + __IO uint8_t CEEI; /* Clear Enable Error Interrupt Register */ + __IO uint8_t SEEI; /* Set Enable Error Interrupt Register */ + __IO uint8_t CERQ; /* Clear Enable Request Register */ + __IO uint8_t SERQ; /* Set Enable Request Register */ + __IO uint8_t CDNE; /* Clear DONE Status Bit Register */ + __IO uint8_t SSRT; /* Set START Bit Register */ + __IO uint8_t CERR; /* Clear Error Register */ + __IO uint8_t CINT; /* Clear Interrupt Request Register */ + __IO uint8_t RESERVED_2[4]; + __IO uint32_t INT; /* Interrupt Request Register */ + __IO uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /* Error Register */ + __IO uint8_t RESERVED_4[4]; + __IO uint32_t HRS; /* Hardware Request Status Register */ + __IO uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /* Channel 3 Priority Register */ + __IO uint8_t DCHPRI2; /* Channel 2 Priority Register */ + __IO uint8_t DCHPRI1; /* Channel 1 Priority Register */ + __IO uint8_t DCHPRI0; /* Channel 0 Priority Register */ + __IO uint8_t RESERVED_6[3836]; + DMA_TCD_TypeDef TCD[4]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint8_t CHCFG[4]; +} DMAMUX_TypeDef; + +/** PIT - Peripheral register structure */ +typedef struct { + __IO uint32_t MCR; /* PIT Module Control Register */ + uint8_t RESERVED0[252]; + struct PIT_CHANNEL { + __IO uint32_t LDVAL; /* Timer Load Value Register */ + __IO uint32_t CVAL; /* Current Timer Value Register */ + __IO uint32_t TCTRL; /* Timer Control Register */ + __IO uint32_t TFLG; /* Timer Flag Register */ + } CHANNEL[4]; +} PIT_TypeDef; + +typedef struct +{ + __IO uint32_t SC; /* Status and Control */ + __IO uint32_t CNT; /* Counter */ + __IO uint32_t MOD; /* Modulo */ + struct FTM_Channel { + __IO uint32_t CnSC; /* Channel Status and Control */ + __IO uint32_t CnV; /* Channel Value */ + } CHANNEL[8]; + __IO uint32_t CNTIN; /* Counter Initial Value */ + __IO uint32_t STATUS; /* Capture and Compare Status */ + __IO uint32_t MODE; /* Features Mode Selection */ + __IO uint32_t SYNC; /* Synchronization */ + __IO uint32_t OUTINIT; /* Initial State for Channels Output */ + __IO uint32_t OUTMASK; /* Output Mask */ + __IO uint32_t COMBINE; /* Function for Linked Channels */ + __IO uint32_t DEADTIME; /* Deadtime Insertion Control */ + __IO uint32_t EXTTRIG; /* FTM External Trigger */ + __IO uint32_t POL; /* Channels Polarity */ + __IO uint32_t FMS; /* Fault Mode Status */ + __IO uint32_t FILTER; /* Input Capture Filter Control */ + __IO uint32_t FLTCTRL; /* Fault Control */ + __IO uint32_t QDCTRL; /* Quadrature Decode Control and Status */ + __IO uint32_t CONF; /* Configuration */ + __IO uint32_t FTLPOL; /* FTM Fault Input Polarity */ + __IO uint32_t SYNCONF; /* Synchronization Configuration */ + __IO uint32_t INVCTRL; /* FTM Inverting Control */ + __IO uint32_t SWOCTRL; /* FTM Software Output Control */ + __IO uint32_t PWMLOAD; /* FTM PWM Load */ +} FTM_TypeDef; + +typedef struct +{ + __IO uint32_t SC1A; // offset: 0x00 + __IO uint32_t SC1B; // offset: 0x04 + __IO uint32_t CFG1; // offset: 0x08 + __IO uint32_t CFG2; // offset: 0x0C + __I uint32_t RA; // offset: 0x10 + __I uint32_t RB; // offset: 0x14 + __IO uint32_t CV1; // offset: 0x18 + __IO uint32_t CV2; // offset: 0x1C + __IO uint32_t SC2; // offset: 0x20 + __IO uint32_t SC3; // offset: 0x24 + __IO uint32_t OFS; // offset: 0x28 + __IO uint32_t PG; // offset: 0x2C + __IO uint32_t MG; // offset: 0x30 + __IO uint32_t CLPD; // offset: 0x34 + __IO uint32_t CLPS; // offset: 0x38 + __IO uint32_t CLP4; // offset: 0x3C + __IO uint32_t CLP3; // offset: 0x40 + __IO uint32_t CLP2; // offset: 0x44 + __IO uint32_t CLP1; // offset: 0x48 + __IO uint32_t CLP0; // offset: 0x4C + uint32_t RESERVED0[1]; // offset: 0x50 + __IO uint32_t CLMD; // offset: 0x54 + __IO uint32_t CLMS; // offset: 0x58 + __IO uint32_t CLM4; // offset: 0x5C + __IO uint32_t CLM3; // offset: 0x60 + __IO uint32_t CLM2; // offset: 0x64 + __IO uint32_t CLM1; // offset: 0x68 + __IO uint32_t CLM0; // offset: 0x6C +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t PSR; + __IO uint32_t CMR; + __I uint32_t CNR; +} LPTMR_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint32_t PDOR; + __IO uint32_t PSOR; + __IO uint32_t PCOR; + __IO uint32_t PTOR; + __IO uint32_t PDIR; + __IO uint32_t PDDR; +} GPIO_TypeDef; + +/** SPI - Peripheral register structure */ +typedef struct { + __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ + uint32_t RESERVED0[1]; + __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint32_t RESERVED1[6]; + __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR[4]; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ + uint32_t RESERVED2[12]; + __I uint32_t RXFR[4]; /**< DSPI Receive FIFO Registers, offset: 0x7C */ +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __I uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; + __I uint8_t ED; + __IO uint8_t MODEM; + __IO uint8_t IR; + uint8_t RESERVED0[1]; + __IO uint8_t PFIFO; + __IO uint8_t CFIFO; + __IO uint8_t SFIFO; + __IO uint8_t TWFIFO; + __I uint8_t TCFIFO; + __IO uint8_t RWFIFO; + __I uint8_t RCFIFO; + uint8_t RESERVED1[1]; + __IO uint8_t C7816; + __IO uint8_t IE7816; + __IO uint8_t IS7816; + union { + __IO uint8_t WP7816T0; + __IO uint8_t WP7816T1; + }; + __IO uint8_t WN7816; + __IO uint8_t WF7816; + __IO uint8_t ET7816; + __IO uint8_t TL7816; + uint8_t RESERVED2[2]; + __IO uint8_t C6; + __IO uint8_t PCTH; + __IO uint8_t PCTL; + __IO uint8_t B1T; + __IO uint8_t SDTH; + __IO uint8_t SDTL; + __IO uint8_t PRE; + __IO uint8_t TPL; + __IO uint8_t IE; + __IO uint8_t WB; + __IO uint8_t S3; + __IO uint8_t S4; + __I uint8_t RPL; + __I uint8_t RPREL; + __IO uint8_t CPW; + __IO uint8_t RIDT; + __IO uint8_t TIDT; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t LVDSC1; + __IO uint8_t LVDSC2; + __IO uint8_t REGSC; +} PMC_TypeDef; + +typedef struct +{ + __IO uint16_t STCTRLH; + __IO uint16_t STCTRLL; + __IO uint16_t TOVALH; + __IO uint16_t TOVALL; + __IO uint16_t WINH; + __IO uint16_t WINL; + __IO uint16_t REFRESH; + __IO uint16_t UNLOCK; + __IO uint16_t TMROUTH; + __IO uint16_t TMROUTL; + __IO uint16_t RSTCNT; + __IO uint16_t PRESC; +} WDOG_TypeDef; + +typedef struct { + __I uint8_t PERID; // 0x00 + uint8_t RESERVED0[3]; + __I uint8_t IDCOMP; // 0x04 + uint8_t RESERVED1[3]; + __I uint8_t REV; // 0x08 + uint8_t RESERVED2[3]; + __I uint8_t ADDINFO; // 0x0C + uint8_t RESERVED3[3]; + __IO uint8_t OTGISTAT; // 0x10 + uint8_t RESERVED4[3]; + __IO uint8_t OTGICR; // 0x14 + uint8_t RESERVED5[3]; + __IO uint8_t OTGSTAT; // 0x18 + uint8_t RESERVED6[3]; + __IO uint8_t OTGCTL; // 0x1C + uint8_t RESERVED7[99]; + __IO uint8_t ISTAT; // 0x80 + uint8_t RESERVED8[3]; + __IO uint8_t INTEN; // 0x84 + uint8_t RESERVED9[3]; + __IO uint8_t ERRSTAT; // 0x88 + uint8_t RESERVED10[3]; + __IO uint8_t ERREN; // 0x8C + uint8_t RESERVED11[3]; + __I uint8_t STAT; // 0x90 + uint8_t RESERVED12[3]; + __IO uint8_t CTL; // 0x94 + uint8_t RESERVED13[3]; + __IO uint8_t ADDR; // 0x98 + uint8_t RESERVED14[3]; + __IO uint8_t BDTPAGE1; // 0x9C + uint8_t RESERVED15[3]; + __IO uint8_t FRMNUML; // 0xA0 + uint8_t RESERVED16[3]; + __IO uint8_t FRMNUMH; // 0xA4 + uint8_t RESERVED17[3]; + __IO uint8_t TOKEN; // 0xA8 + uint8_t RESERVED18[3]; + __IO uint8_t SOFTHLD; // 0xAC + uint8_t RESERVED19[3]; + __IO uint8_t BDTPAGE2; // 0xB0 + uint8_t RESERVED20[3]; + __IO uint8_t BDTPAGE3; // 0xB4 + uint8_t RESERVED21[11]; + struct { + __IO uint8_t V; // 0xC0 + uint8_t RESERVED[3]; + } ENDPT[16]; + __IO uint8_t USBCTRL; // 0x100 + uint8_t RESERVED22[3]; + __I uint8_t OBSERVE; // 0x104 + uint8_t RESERVED23[3]; + __IO uint8_t CONTROL; // 0x108 + uint8_t RESERVED24[3]; + __IO uint8_t USBTRC0; // 0x10C + uint8_t RESERVED25[7]; + __IO uint8_t USBFRMADJUST; // 0x114 +} USBOTG_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008000) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define SPI0_BASE ((uint32_t)0x4002C000) +#define PIT_BASE ((uint32_t)0x40037000) +#define FTM0_BASE ((uint32_t)0x40038000) +#define FTM1_BASE ((uint32_t)0x40039000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define WDOG_BASE ((uint32_t)0x40052000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define USBOTG_BASE ((uint32_t)0x40072000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define PIT ((PIT_TypeDef *) PIT_BASE) +#define FTM0 ((FTM_TypeDef *) FTM0_BASE) +#define FTM1 ((FTM_TypeDef *) FTM1_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define WDOG ((WDOG_TypeDef *) WDOG_BASE) +#define USBOTG ((USBOTG_TypeDef *) USBOTG_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ +#define SIM_SOPT1_RAMSIZE_SHIFT 12 +#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT)) +#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK)) + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) +#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT)) +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ +#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */ +#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */ +#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */ +#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */ +#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */ +#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */ +#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT)) +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) +#define SIM_CLKDIV1_OUTDIV2_SHIFT 24 +#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT)) +#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK)) +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT)) +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) + +/****** Bits definition for SIM_CLKDIV2 register ***********/ +#define SIM_CLKDIV2_USBDIV_SHIFT 1 +#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT)) +#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK)) +#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001) + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ +/********** Bits definition for LLWU_PE1 register *************/ +#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ +#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ +#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ +#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ +#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ +#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ +#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ +#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ +#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ +#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ +#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ +#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ + +/********** Bits definition for LLWU_PE2 register *************/ +#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ +#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ +#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ +#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ +#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ +#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ +#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ +#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ +#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ +#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ +#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ +#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ + +/********** Bits definition for LLWU_PE3 register *************/ +#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ +#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ +#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ +#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ +#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ +#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ +#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ +#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ +#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ +#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ +#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ +#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ + +/********** Bits definition for LLWU_PE4 register *************/ +#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ +#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ +#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ +#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ +#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ +#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ +#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ +#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ +#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ +#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ +#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ +#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ + +/********** Bits definition for LLWU_ME register *************/ +#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ +#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ +#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ +#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ +#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ +#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ +#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ +#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ + +/********** Bits definition for LLWU_F1 register *************/ +#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ +#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ +#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ +#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ +#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ +#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ +#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ +#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ + +/********** Bits definition for LLWU_F2 register *************/ +#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ +#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ +#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ +#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ +#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ +#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ +#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ +#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ + +/********** Bits definition for LLWU_F3 register *************/ +#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ +#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ +#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ +#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ +#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ +#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ +#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ +#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ + +/********** Bits definition for LLWU_FILT1 register *************/ +#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/********** Bits definition for LLWU_FILT2 register *************/ +#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ +/******** Bits definition for PORTx_PCRn register *************/ +#define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ +#define PORTx_PCRn_IRQC_SHIFT 16 +#define PORTx_PCRn_IRQC_MASK ((uint32_t)((uint32_t)0xF << PORTx_PCRn_IRQC_SHIFT)) +#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) +#define PORTx_PCRn_LK ((uint32_t)0x00008000) /*!< Lock Register */ +#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ +#define PORTx_PCRn_MUX_MASK ((uint32_t)((uint32_t)0x7 << PORTx_PCRn_MUX_SHIFT)) /*!< Pin Mux Control (mask) */ +#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ +#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ +#define PORTx_PCRn_ODE ((uint32_t)0x00000020) /*!< Open Drain Enable */ +#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ +#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ +#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ +#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for OSC_CR register **************/ +#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ +#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ +#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ +#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ +#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ +#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ +/* ---------------------------------------------------------------------------- + -- DMA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros + * @{ + */ + + +/* DMA - Register accessors */ +#define DMA_CR_REG(base) ((base)->CR) +#define DMA_ES_REG(base) ((base)->ES) +#define DMA_ERQ_REG(base) ((base)->ERQ) +#define DMA_EEI_REG(base) ((base)->EEI) +#define DMA_CEEI_REG(base) ((base)->CEEI) +#define DMA_SEEI_REG(base) ((base)->SEEI) +#define DMA_CERQ_REG(base) ((base)->CERQ) +#define DMA_SERQ_REG(base) ((base)->SERQ) +#define DMA_CDNE_REG(base) ((base)->CDNE) +#define DMA_SSRT_REG(base) ((base)->SSRT) +#define DMA_CERR_REG(base) ((base)->CERR) +#define DMA_CINT_REG(base) ((base)->CINT) +#define DMA_INT_REG(base) ((base)->INT) +#define DMA_ERR_REG(base) ((base)->ERR) +#define DMA_HRS_REG(base) ((base)->HRS) +#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) +#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) +#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) +#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) +#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) +#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) +#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) +#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) +#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) +#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) +#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) +#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) +#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) +#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) +#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) +#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) +#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) +#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) +#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) + +/*! + * @} + */ /* end of group DMA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define DMA_CR_EDBG_MASK 0x2u +#define DMA_CR_EDBG_SHIFT 1 +#define DMA_CR_ERCA_MASK 0x4u +#define DMA_CR_ERCA_SHIFT 2 +#define DMA_CR_HOE_MASK 0x10u +#define DMA_CR_HOE_SHIFT 4 +#define DMA_CR_HALT_MASK 0x20u +#define DMA_CR_HALT_SHIFT 5 +#define DMA_CR_CLM_MASK 0x40u +#define DMA_CR_CLM_SHIFT 6 +#define DMA_CR_EMLM_MASK 0x80u +#define DMA_CR_EMLM_SHIFT 7 +#define DMA_CR_ECX_MASK 0x10000u +#define DMA_CR_ECX_SHIFT 16 +#define DMA_CR_CX_MASK 0x20000u +#define DMA_CR_CX_SHIFT 17 +/* ES Bit Fields */ +#define DMA_ES_DBE_MASK 0x1u +#define DMA_ES_DBE_SHIFT 0 +#define DMA_ES_SBE_MASK 0x2u +#define DMA_ES_SBE_SHIFT 1 +#define DMA_ES_SGE_MASK 0x4u +#define DMA_ES_SGE_SHIFT 2 +#define DMA_ES_NCE_MASK 0x8u +#define DMA_ES_NCE_SHIFT 3 +#define DMA_ES_DOE_MASK 0x10u +#define DMA_ES_DOE_SHIFT 4 +#define DMA_ES_DAE_MASK 0x20u +#define DMA_ES_DAE_SHIFT 5 +#define DMA_ES_SOE_MASK 0x40u +#define DMA_ES_SOE_SHIFT 6 +#define DMA_ES_SAE_MASK 0x80u +#define DMA_ES_SAE_SHIFT 7 +#define DMA_ES_ERRCHN_MASK 0xF00u +#define DMA_ES_ERRCHN_SHIFT 8 +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK 0x4000u +#define DMA_ES_CPE_SHIFT 14 +#define DMA_ES_ECX_MASK 0x10000u +#define DMA_ES_ECX_SHIFT 16 +#define DMA_ES_VLD_MASK 0x80000000u +#define DMA_ES_VLD_SHIFT 31 +/* ERQ Bit Fields */ +#define DMA_ERQ_ERQ0_MASK 0x1u +#define DMA_ERQ_ERQ0_SHIFT 0 +#define DMA_ERQ_ERQ1_MASK 0x2u +#define DMA_ERQ_ERQ1_SHIFT 1 +#define DMA_ERQ_ERQ2_MASK 0x4u +#define DMA_ERQ_ERQ2_SHIFT 2 +#define DMA_ERQ_ERQ3_MASK 0x8u +#define DMA_ERQ_ERQ3_SHIFT 3 +/* EEI Bit Fields */ +#define DMA_EEI_EEI0_MASK 0x1u +#define DMA_EEI_EEI0_SHIFT 0 +#define DMA_EEI_EEI1_MASK 0x2u +#define DMA_EEI_EEI1_SHIFT 1 +#define DMA_EEI_EEI2_MASK 0x4u +#define DMA_EEI_EEI2_SHIFT 2 +#define DMA_EEI_EEI3_MASK 0x8u +#define DMA_EEI_EEI3_SHIFT 3 +/* CEEI Bit Fields */ +#define DMA_CEEI_CEEI_MASK 0xFu +#define DMA_CEEI_CEEI_SHIFT 0 +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK 0x40u +#define DMA_CEEI_CAEE_SHIFT 6 +#define DMA_CEEI_NOP_MASK 0x80u +#define DMA_CEEI_NOP_SHIFT 7 +/* SEEI Bit Fields */ +#define DMA_SEEI_SEEI_MASK 0xFu +#define DMA_SEEI_SEEI_SHIFT 0 +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK 0x40u +#define DMA_SEEI_SAEE_SHIFT 6 +#define DMA_SEEI_NOP_MASK 0x80u +#define DMA_SEEI_NOP_SHIFT 7 +/* CERQ Bit Fields */ +#define DMA_CERQ_CERQ_MASK 0xFu +#define DMA_CERQ_CERQ_SHIFT 0 +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK 0x40u +#define DMA_CERQ_CAER_SHIFT 6 +#define DMA_CERQ_NOP_MASK 0x80u +#define DMA_CERQ_NOP_SHIFT 7 +/* SERQ Bit Fields */ +#define DMA_SERQ_SERQ_MASK 0xFu +#define DMA_SERQ_SERQ_SHIFT 0 +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK 0x40u +#define DMA_SERQ_SAER_SHIFT 6 +#define DMA_SERQ_NOP_MASK 0x80u +#define DMA_SERQ_NOP_SHIFT 7 +/* CDNE Bit Fields */ +#define DMA_CDNE_CDNE_MASK 0xFu +#define DMA_CDNE_CDNE_SHIFT 0 +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK 0x40u +#define DMA_CDNE_CADN_SHIFT 6 +#define DMA_CDNE_NOP_MASK 0x80u +#define DMA_CDNE_NOP_SHIFT 7 +/* SSRT Bit Fields */ +#define DMA_SSRT_SSRT_MASK 0xFu +#define DMA_SSRT_SSRT_SHIFT 0 +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK 0x40u +#define DMA_SSRT_SAST_SHIFT 6 +#define DMA_SSRT_NOP_MASK 0x80u +#define DMA_SSRT_NOP_SHIFT 7 +/* CERR Bit Fields */ +#define DMA_CERR_CERR_MASK 0xFu +#define DMA_CERR_CERR_SHIFT 0 +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK 0x40u +#define DMA_CERR_CAEI_SHIFT 6 +#define DMA_CERR_NOP_MASK 0x80u +#define DMA_CERR_NOP_SHIFT 7 +/* CINT Bit Fields */ +#define DMA_CINT_CINT_MASK 0xFu +#define DMA_CINT_CINT_SHIFT 0 +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK 0x40u +#define DMA_CINT_CAIR_SHIFT 6 +#define DMA_CINT_NOP_MASK 0x80u +#define DMA_CINT_NOP_SHIFT 7 +/* INT Bit Fields */ +#define DMA_INT_INT0_MASK 0x1u +#define DMA_INT_INT0_SHIFT 0 +#define DMA_INT_INT1_MASK 0x2u +#define DMA_INT_INT1_SHIFT 1 +#define DMA_INT_INT2_MASK 0x4u +#define DMA_INT_INT2_SHIFT 2 +#define DMA_INT_INT3_MASK 0x8u +#define DMA_INT_INT3_SHIFT 3 +/* ERR Bit Fields */ +#define DMA_ERR_ERR0_MASK 0x1u +#define DMA_ERR_ERR0_SHIFT 0 +#define DMA_ERR_ERR1_MASK 0x2u +#define DMA_ERR_ERR1_SHIFT 1 +#define DMA_ERR_ERR2_MASK 0x4u +#define DMA_ERR_ERR2_SHIFT 2 +#define DMA_ERR_ERR3_MASK 0x8u +#define DMA_ERR_ERR3_SHIFT 3 +/* HRS Bit Fields */ +#define DMA_HRS_HRS0_MASK 0x1u +#define DMA_HRS_HRS0_SHIFT 0 +#define DMA_HRS_HRS1_MASK 0x2u +#define DMA_HRS_HRS1_SHIFT 1 +#define DMA_HRS_HRS2_MASK 0x4u +#define DMA_HRS_HRS2_SHIFT 2 +#define DMA_HRS_HRS3_MASK 0x8u +#define DMA_HRS_HRS3_SHIFT 3 +/* DCHPRI3 Bit Fields */ +#define DMA_DCHPRI3_CHPRI_MASK 0xFu +#define DMA_DCHPRI3_CHPRI_SHIFT 0 +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK 0x40u +#define DMA_DCHPRI3_DPA_SHIFT 6 +#define DMA_DCHPRI3_ECP_MASK 0x80u +#define DMA_DCHPRI3_ECP_SHIFT 7 +/* DCHPRI2 Bit Fields */ +#define DMA_DCHPRI2_CHPRI_MASK 0xFu +#define DMA_DCHPRI2_CHPRI_SHIFT 0 +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK 0x40u +#define DMA_DCHPRI2_DPA_SHIFT 6 +#define DMA_DCHPRI2_ECP_MASK 0x80u +#define DMA_DCHPRI2_ECP_SHIFT 7 +/* DCHPRI1 Bit Fields */ +#define DMA_DCHPRI1_CHPRI_MASK 0xFu +#define DMA_DCHPRI1_CHPRI_SHIFT 0 +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK 0x40u +#define DMA_DCHPRI1_DPA_SHIFT 6 +#define DMA_DCHPRI1_ECP_MASK 0x80u +#define DMA_DCHPRI1_ECP_SHIFT 7 +/* DCHPRI0 Bit Fields */ +#define DMA_DCHPRI0_CHPRI_MASK 0xFu +#define DMA_DCHPRI0_CHPRI_SHIFT 0 +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK 0x40u +#define DMA_DCHPRI0_DPA_SHIFT 6 +#define DMA_DCHPRI0_ECP_MASK 0x80u +#define DMA_DCHPRI0_ECP_SHIFT 7 +/* SADDR Bit Fields */ +#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu +#define DMA_SADDR_SADDR_SHIFT 0 +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) +/* SOFF Bit Fields */ +#define DMA_SOFF_SOFF_MASK 0xFFFFu +#define DMA_SOFF_SOFF_SHIFT 0 +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) +/* ATTR Bit Fields */ +#define DMA_ATTR_DSIZE_MASK 0x7u +#define DMA_ATTR_DSIZE_SHIFT 0 +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK 0xF8u +#define DMA_ATTR_DMOD_SHIFT 3 +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK 0x700u +#define DMA_ATTR_SSIZE_SHIFT 8 +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK 0xF800u +#define DMA_ATTR_SMOD_SHIFT 11 +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) +/* NBYTES_MLNO Bit Fields */ +#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu +#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) +/* NBYTES_MLOFFNO Bit Fields */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 +/* NBYTES_MLOFFYES Bit Fields */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 +/* SLAST Bit Fields */ +#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu +#define DMA_SLAST_SLAST_SHIFT 0 +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) +/* DADDR Bit Fields */ +#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu +#define DMA_DADDR_DADDR_SHIFT 0 +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) +/* DOFF Bit Fields */ +#define DMA_DOFF_DOFF_MASK 0xFFFFu +#define DMA_DOFF_DOFF_SHIFT 0 +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) +/* CITER_ELINKNO Bit Fields */ +#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu +#define DMA_CITER_ELINKNO_CITER_SHIFT 0 +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKNO_ELINK_SHIFT 15 +/* CITER_ELINKYES Bit Fields */ +#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu +#define DMA_CITER_ELINKYES_CITER_SHIFT 0 +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_CITER_ELINKYES_ELINK_SHIFT 15 +/* DLAST_SGA Bit Fields */ +#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu +#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) +/* CSR Bit Fields */ +#define DMA_CSR_START_MASK 0x1u +#define DMA_CSR_START_SHIFT 0 +#define DMA_CSR_INTMAJOR_MASK 0x2u +#define DMA_CSR_INTMAJOR_SHIFT 1 +#define DMA_CSR_INTHALF_MASK 0x4u +#define DMA_CSR_INTHALF_SHIFT 2 +#define DMA_CSR_DREQ_MASK 0x8u +#define DMA_CSR_DREQ_SHIFT 3 +#define DMA_CSR_ESG_MASK 0x10u +#define DMA_CSR_ESG_SHIFT 4 +#define DMA_CSR_MAJORELINK_MASK 0x20u +#define DMA_CSR_MAJORELINK_SHIFT 5 +#define DMA_CSR_ACTIVE_MASK 0x40u +#define DMA_CSR_ACTIVE_SHIFT 6 +#define DMA_CSR_DONE_MASK 0x80u +#define DMA_CSR_DONE_SHIFT 7 +#define DMA_CSR_MAJORLINKCH_MASK 0xF00u +#define DMA_CSR_MAJORLINKCH_SHIFT 8 +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK 0xC000u +#define DMA_CSR_BWC_SHIFT 14 +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) +/* BITER_ELINKNO Bit Fields */ +#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu +#define DMA_BITER_ELINKNO_BITER_SHIFT 0 +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKNO_ELINK_SHIFT 15 +/* BITER_ELINKYES Bit Fields */ +#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu +#define DMA_BITER_ELINKYES_BITER_SHIFT 0 +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u +#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u +#define DMA_BITER_ELINKYES_ELINK_SHIFT 15 + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base pointer */ +#define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u) +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA_BASE_PTR } + +/* ---------------------------------------------------------------------------- + -- DMA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros + * @{ + */ + + +/* DMA - Register instance definitions */ +/* DMA */ +#define DMA_CR DMA_CR_REG(DMA_BASE_PTR) +#define DMA_ES DMA_ES_REG(DMA_BASE_PTR) +#define DMA_ERQ DMA_ERQ_REG(DMA_BASE_PTR) +#define DMA_EEI DMA_EEI_REG(DMA_BASE_PTR) +#define DMA_CEEI DMA_CEEI_REG(DMA_BASE_PTR) +#define DMA_SEEI DMA_SEEI_REG(DMA_BASE_PTR) +#define DMA_CERQ DMA_CERQ_REG(DMA_BASE_PTR) +#define DMA_SERQ DMA_SERQ_REG(DMA_BASE_PTR) +#define DMA_CDNE DMA_CDNE_REG(DMA_BASE_PTR) +#define DMA_SSRT DMA_SSRT_REG(DMA_BASE_PTR) +#define DMA_CERR DMA_CERR_REG(DMA_BASE_PTR) +#define DMA_CINT DMA_CINT_REG(DMA_BASE_PTR) +#define DMA_INT DMA_INT_REG(DMA_BASE_PTR) +#define DMA_ERR DMA_ERR_REG(DMA_BASE_PTR) +#define DMA_HRS DMA_HRS_REG(DMA_BASE_PTR) +#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA_BASE_PTR) +#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA_BASE_PTR) +#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA_BASE_PTR) +#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA_BASE_PTR) +#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_CSR DMA_CSR_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,0) +#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,0) +#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_CSR DMA_CSR_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,1) +#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,1) +#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_CSR DMA_CSR_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,2) +#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,2) +#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_CSR DMA_CSR_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,3) +#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,3) + +/* DMA - Register array accessors */ +#define DMA_SADDR(index) DMA_SADDR_REG(DMA_BASE_PTR,index) +#define DMA_SOFF(index) DMA_SOFF_REG(DMA_BASE_PTR,index) +#define DMA_ATTR(index) DMA_ATTR_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA_BASE_PTR,index) +#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA_BASE_PTR,index) +#define DMA_SLAST(index) DMA_SLAST_REG(DMA_BASE_PTR,index) +#define DMA_DADDR(index) DMA_DADDR_REG(DMA_BASE_PTR,index) +#define DMA_DOFF(index) DMA_DOFF_REG(DMA_BASE_PTR,index) +#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA_BASE_PTR,index) +#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA_BASE_PTR,index) +#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA_BASE_PTR,index) +#define DMA_CSR(index) DMA_CSR_REG(DMA_BASE_PTR,index) +#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA_BASE_PTR,index) +#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA_BASE_PTR,index) + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ +/******** Bits definition for DMAMUX_CHCFGn register **********/ +#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ +#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ +#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ +#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ +#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/****************************************************************/ +/* */ +/* FlexTimer Module (FTM) */ +/* */ +/****************************************************************/ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK 0x18u +#define FTM_SC_CLKS_SHIFT 3 +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS 0x20u +#define FTM_SC_TOIE 0x40u +#define FTM_SC_TOF 0x80u +/* CNT Bit Fields */ +#define FTM_CNT_COUNT_MASK 0xFFFFu +#define FTM_CNT_COUNT_SHIFT 0 +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) +/* MOD Bit Fields */ +#define FTM_MOD_MOD_MASK 0xFFFFu +#define FTM_MOD_MOD_SHIFT 0 +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) +/* CnSC Bit Fields */ +#define FTM_CnSC_DMA 0x1u +#define FTM_CnSC_ELSA 0x4u +#define FTM_CnSC_ELSB 0x8u +#define FTM_CnSC_MSA 0x10u +#define FTM_CnSC_MSB 0x20u +#define FTM_CnSC_CHIE 0x40u +#define FTM_CnSC_CHF 0x80u +/* CnV Bit Fields */ +#define FTM_CnV_VAL_MASK 0xFFFFu +#define FTM_CnV_VAL_SHIFT 0 +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) +/* CNTIN Bit Fields */ +#define FTM_CNTIN_INIT_MASK 0xFFFFu +#define FTM_CNTIN_INIT_SHIFT 0 +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) +/* STATUS Bit Fields */ +#define FTM_STATUS_CH0F_MASK 0x1u +#define FTM_STATUS_CH0F_SHIFT 0 +#define FTM_STATUS_CH1F_MASK 0x2u +#define FTM_STATUS_CH1F_SHIFT 1 +#define FTM_STATUS_CH2F_MASK 0x4u +#define FTM_STATUS_CH2F_SHIFT 2 +#define FTM_STATUS_CH3F_MASK 0x8u +#define FTM_STATUS_CH3F_SHIFT 3 +#define FTM_STATUS_CH4F_MASK 0x10u +#define FTM_STATUS_CH4F_SHIFT 4 +#define FTM_STATUS_CH5F_MASK 0x20u +#define FTM_STATUS_CH5F_SHIFT 5 +#define FTM_STATUS_CH6F_MASK 0x40u +#define FTM_STATUS_CH6F_SHIFT 6 +#define FTM_STATUS_CH7F_MASK 0x80u +#define FTM_STATUS_CH7F_SHIFT 7 +/* MODE Bit Fields */ +#define FTM_MODE_FTMEN_MASK 0x1u +#define FTM_MODE_FTMEN_SHIFT 0 +#define FTM_MODE_INIT_MASK 0x2u +#define FTM_MODE_INIT_SHIFT 1 +#define FTM_MODE_WPDIS_MASK 0x4u +#define FTM_MODE_WPDIS_SHIFT 2 +#define FTM_MODE_PWMSYNC_MASK 0x8u +#define FTM_MODE_PWMSYNC_SHIFT 3 +#define FTM_MODE_CAPTEST_MASK 0x10u +#define FTM_MODE_CAPTEST_SHIFT 4 +#define FTM_MODE_FAULTM_MASK 0x60u +#define FTM_MODE_FAULTM_SHIFT 5 +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK 0x80u +#define FTM_MODE_FAULTIE_SHIFT 7 +/* SYNC Bit Fields */ +#define FTM_SYNC_CNTMIN_MASK 0x1u +#define FTM_SYNC_CNTMIN_SHIFT 0 +#define FTM_SYNC_CNTMAX_MASK 0x2u +#define FTM_SYNC_CNTMAX_SHIFT 1 +#define FTM_SYNC_REINIT_MASK 0x4u +#define FTM_SYNC_REINIT_SHIFT 2 +#define FTM_SYNC_SYNCHOM_MASK 0x8u +#define FTM_SYNC_SYNCHOM_SHIFT 3 +#define FTM_SYNC_TRIG0_MASK 0x10u +#define FTM_SYNC_TRIG0_SHIFT 4 +#define FTM_SYNC_TRIG1_MASK 0x20u +#define FTM_SYNC_TRIG1_SHIFT 5 +#define FTM_SYNC_TRIG2_MASK 0x40u +#define FTM_SYNC_TRIG2_SHIFT 6 +#define FTM_SYNC_SWSYNC_MASK 0x80u +#define FTM_SYNC_SWSYNC_SHIFT 7 +/* OUTINIT Bit Fields */ +#define FTM_OUTINIT_CH0OI_MASK 0x1u +#define FTM_OUTINIT_CH0OI_SHIFT 0 +#define FTM_OUTINIT_CH1OI_MASK 0x2u +#define FTM_OUTINIT_CH1OI_SHIFT 1 +#define FTM_OUTINIT_CH2OI_MASK 0x4u +#define FTM_OUTINIT_CH2OI_SHIFT 2 +#define FTM_OUTINIT_CH3OI_MASK 0x8u +#define FTM_OUTINIT_CH3OI_SHIFT 3 +#define FTM_OUTINIT_CH4OI_MASK 0x10u +#define FTM_OUTINIT_CH4OI_SHIFT 4 +#define FTM_OUTINIT_CH5OI_MASK 0x20u +#define FTM_OUTINIT_CH5OI_SHIFT 5 +#define FTM_OUTINIT_CH6OI_MASK 0x40u +#define FTM_OUTINIT_CH6OI_SHIFT 6 +#define FTM_OUTINIT_CH7OI_MASK 0x80u +#define FTM_OUTINIT_CH7OI_SHIFT 7 +/* OUTMASK Bit Fields */ +#define FTM_OUTMASK_CH0OM_MASK 0x1u +#define FTM_OUTMASK_CH0OM_SHIFT 0 +#define FTM_OUTMASK_CH1OM_MASK 0x2u +#define FTM_OUTMASK_CH1OM_SHIFT 1 +#define FTM_OUTMASK_CH2OM_MASK 0x4u +#define FTM_OUTMASK_CH2OM_SHIFT 2 +#define FTM_OUTMASK_CH3OM_MASK 0x8u +#define FTM_OUTMASK_CH3OM_SHIFT 3 +#define FTM_OUTMASK_CH4OM_MASK 0x10u +#define FTM_OUTMASK_CH4OM_SHIFT 4 +#define FTM_OUTMASK_CH5OM_MASK 0x20u +#define FTM_OUTMASK_CH5OM_SHIFT 5 +#define FTM_OUTMASK_CH6OM_MASK 0x40u +#define FTM_OUTMASK_CH6OM_SHIFT 6 +#define FTM_OUTMASK_CH7OM_MASK 0x80u +#define FTM_OUTMASK_CH7OM_SHIFT 7 +/* COMBINE Bit Fields */ +#define FTM_COMBINE_COMBINE0_MASK 0x1u +#define FTM_COMBINE_COMBINE0_SHIFT 0 +#define FTM_COMBINE_COMP0_MASK 0x2u +#define FTM_COMBINE_COMP0_SHIFT 1 +#define FTM_COMBINE_DECAPEN0_MASK 0x4u +#define FTM_COMBINE_DECAPEN0_SHIFT 2 +#define FTM_COMBINE_DECAP0_MASK 0x8u +#define FTM_COMBINE_DECAP0_SHIFT 3 +#define FTM_COMBINE_DTEN0_MASK 0x10u +#define FTM_COMBINE_DTEN0_SHIFT 4 +#define FTM_COMBINE_SYNCEN0_MASK 0x20u +#define FTM_COMBINE_SYNCEN0_SHIFT 5 +#define FTM_COMBINE_FAULTEN0_MASK 0x40u +#define FTM_COMBINE_FAULTEN0_SHIFT 6 +#define FTM_COMBINE_COMBINE1_MASK 0x100u +#define FTM_COMBINE_COMBINE1_SHIFT 8 +#define FTM_COMBINE_COMP1_MASK 0x200u +#define FTM_COMBINE_COMP1_SHIFT 9 +#define FTM_COMBINE_DECAPEN1_MASK 0x400u +#define FTM_COMBINE_DECAPEN1_SHIFT 10 +#define FTM_COMBINE_DECAP1_MASK 0x800u +#define FTM_COMBINE_DECAP1_SHIFT 11 +#define FTM_COMBINE_DTEN1_MASK 0x1000u +#define FTM_COMBINE_DTEN1_SHIFT 12 +#define FTM_COMBINE_SYNCEN1_MASK 0x2000u +#define FTM_COMBINE_SYNCEN1_SHIFT 13 +#define FTM_COMBINE_FAULTEN1_MASK 0x4000u +#define FTM_COMBINE_FAULTEN1_SHIFT 14 +#define FTM_COMBINE_COMBINE2_MASK 0x10000u +#define FTM_COMBINE_COMBINE2_SHIFT 16 +#define FTM_COMBINE_COMP2_MASK 0x20000u +#define FTM_COMBINE_COMP2_SHIFT 17 +#define FTM_COMBINE_DECAPEN2_MASK 0x40000u +#define FTM_COMBINE_DECAPEN2_SHIFT 18 +#define FTM_COMBINE_DECAP2_MASK 0x80000u +#define FTM_COMBINE_DECAP2_SHIFT 19 +#define FTM_COMBINE_DTEN2_MASK 0x100000u +#define FTM_COMBINE_DTEN2_SHIFT 20 +#define FTM_COMBINE_SYNCEN2_MASK 0x200000u +#define FTM_COMBINE_SYNCEN2_SHIFT 21 +#define FTM_COMBINE_FAULTEN2_MASK 0x400000u +#define FTM_COMBINE_FAULTEN2_SHIFT 22 +#define FTM_COMBINE_COMBINE3_MASK 0x1000000u +#define FTM_COMBINE_COMBINE3_SHIFT 24 +#define FTM_COMBINE_COMP3_MASK 0x2000000u +#define FTM_COMBINE_COMP3_SHIFT 25 +#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u +#define FTM_COMBINE_DECAPEN3_SHIFT 26 +#define FTM_COMBINE_DECAP3_MASK 0x8000000u +#define FTM_COMBINE_DECAP3_SHIFT 27 +#define FTM_COMBINE_DTEN3_MASK 0x10000000u +#define FTM_COMBINE_DTEN3_SHIFT 28 +#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u +#define FTM_COMBINE_SYNCEN3_SHIFT 29 +#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u +#define FTM_COMBINE_FAULTEN3_SHIFT 30 +/* DEADTIME Bit Fields */ +#define FTM_DEADTIME_DTVAL_MASK 0x3Fu +#define FTM_DEADTIME_DTVAL_SHIFT 0 +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK 0xC0u +#define FTM_DEADTIME_DTPS_SHIFT 6 +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) +/* EXTTRIG Bit Fields */ +#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u +#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 +#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u +#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 +#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u +#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 +#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u +#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 +#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u +#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 +#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u +#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 +#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u +#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 +#define FTM_EXTTRIG_TRIGF_MASK 0x80u +#define FTM_EXTTRIG_TRIGF_SHIFT 7 +/* POL Bit Fields */ +#define FTM_POL_POL0_MASK 0x1u +#define FTM_POL_POL0_SHIFT 0 +#define FTM_POL_POL1_MASK 0x2u +#define FTM_POL_POL1_SHIFT 1 +#define FTM_POL_POL2_MASK 0x4u +#define FTM_POL_POL2_SHIFT 2 +#define FTM_POL_POL3_MASK 0x8u +#define FTM_POL_POL3_SHIFT 3 +#define FTM_POL_POL4_MASK 0x10u +#define FTM_POL_POL4_SHIFT 4 +#define FTM_POL_POL5_MASK 0x20u +#define FTM_POL_POL5_SHIFT 5 +#define FTM_POL_POL6_MASK 0x40u +#define FTM_POL_POL6_SHIFT 6 +#define FTM_POL_POL7_MASK 0x80u +#define FTM_POL_POL7_SHIFT 7 +/* FMS Bit Fields */ +#define FTM_FMS_FAULTF0_MASK 0x1u +#define FTM_FMS_FAULTF0_SHIFT 0 +#define FTM_FMS_FAULTF1_MASK 0x2u +#define FTM_FMS_FAULTF1_SHIFT 1 +#define FTM_FMS_FAULTF2_MASK 0x4u +#define FTM_FMS_FAULTF2_SHIFT 2 +#define FTM_FMS_FAULTF3_MASK 0x8u +#define FTM_FMS_FAULTF3_SHIFT 3 +#define FTM_FMS_FAULTIN_MASK 0x20u +#define FTM_FMS_FAULTIN_SHIFT 5 +#define FTM_FMS_WPEN_MASK 0x40u +#define FTM_FMS_WPEN_SHIFT 6 +#define FTM_FMS_FAULTF_MASK 0x80u +#define FTM_FMS_FAULTF_SHIFT 7 +/* FILTER Bit Fields */ +#define FTM_FILTER_CH0FVAL_MASK 0xFu +#define FTM_FILTER_CH0FVAL_SHIFT 0 +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK 0xF0u +#define FTM_FILTER_CH1FVAL_SHIFT 4 +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK 0xF00u +#define FTM_FILTER_CH2FVAL_SHIFT 8 +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK 0xF000u +#define FTM_FILTER_CH3FVAL_SHIFT 12 +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) +/* FLTCTRL Bit Fields */ +#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u +#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 +#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u +#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 +#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u +#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 +#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u +#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 +#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u +#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 +#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u +#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 +#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u +#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 +#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u +#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 +#define FTM_FLTCTRL_FFVAL_MASK 0xF00u +#define FTM_FLTCTRL_FFVAL_SHIFT 8 +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) +/* QDCTRL Bit Fields */ +#define FTM_QDCTRL_QUADEN_MASK 0x1u +#define FTM_QDCTRL_QUADEN_SHIFT 0 +#define FTM_QDCTRL_TOFDIR_MASK 0x2u +#define FTM_QDCTRL_TOFDIR_SHIFT 1 +#define FTM_QDCTRL_QUADIR_MASK 0x4u +#define FTM_QDCTRL_QUADIR_SHIFT 2 +#define FTM_QDCTRL_QUADMODE_MASK 0x8u +#define FTM_QDCTRL_QUADMODE_SHIFT 3 +#define FTM_QDCTRL_PHBPOL_MASK 0x10u +#define FTM_QDCTRL_PHBPOL_SHIFT 4 +#define FTM_QDCTRL_PHAPOL_MASK 0x20u +#define FTM_QDCTRL_PHAPOL_SHIFT 5 +#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u +#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 +#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u +#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 +/* CONF Bit Fields */ +#define FTM_CONF_NUMTOF_MASK 0x1Fu +#define FTM_CONF_NUMTOF_SHIFT 0 +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK 0xC0u +#define FTM_CONF_BDMMODE_SHIFT 6 +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK 0x200u +#define FTM_CONF_GTBEEN_SHIFT 9 +#define FTM_CONF_GTBEOUT_MASK 0x400u +#define FTM_CONF_GTBEOUT_SHIFT 10 +/* FLTPOL Bit Fields */ +#define FTM_FLTPOL_FLT0POL_MASK 0x1u +#define FTM_FLTPOL_FLT0POL_SHIFT 0 +#define FTM_FLTPOL_FLT1POL_MASK 0x2u +#define FTM_FLTPOL_FLT1POL_SHIFT 1 +#define FTM_FLTPOL_FLT2POL_MASK 0x4u +#define FTM_FLTPOL_FLT2POL_SHIFT 2 +#define FTM_FLTPOL_FLT3POL_MASK 0x8u +#define FTM_FLTPOL_FLT3POL_SHIFT 3 +/* SYNCONF Bit Fields */ +#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u +#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 +#define FTM_SYNCONF_CNTINC_MASK 0x4u +#define FTM_SYNCONF_CNTINC_SHIFT 2 +#define FTM_SYNCONF_INVC_MASK 0x10u +#define FTM_SYNCONF_INVC_SHIFT 4 +#define FTM_SYNCONF_SWOC_MASK 0x20u +#define FTM_SYNCONF_SWOC_SHIFT 5 +#define FTM_SYNCONF_SYNCMODE_MASK 0x80u +#define FTM_SYNCONF_SYNCMODE_SHIFT 7 +#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u +#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 +#define FTM_SYNCONF_SWWRBUF_MASK 0x200u +#define FTM_SYNCONF_SWWRBUF_SHIFT 9 +#define FTM_SYNCONF_SWOM_MASK 0x400u +#define FTM_SYNCONF_SWOM_SHIFT 10 +#define FTM_SYNCONF_SWINVC_MASK 0x800u +#define FTM_SYNCONF_SWINVC_SHIFT 11 +#define FTM_SYNCONF_SWSOC_MASK 0x1000u +#define FTM_SYNCONF_SWSOC_SHIFT 12 +#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u +#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 +#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u +#define FTM_SYNCONF_HWWRBUF_SHIFT 17 +#define FTM_SYNCONF_HWOM_MASK 0x40000u +#define FTM_SYNCONF_HWOM_SHIFT 18 +#define FTM_SYNCONF_HWINVC_MASK 0x80000u +#define FTM_SYNCONF_HWINVC_SHIFT 19 +#define FTM_SYNCONF_HWSOC_MASK 0x100000u +#define FTM_SYNCONF_HWSOC_SHIFT 20 +/* INVCTRL Bit Fields */ +#define FTM_INVCTRL_INV0EN_MASK 0x1u +#define FTM_INVCTRL_INV0EN_SHIFT 0 +#define FTM_INVCTRL_INV1EN_MASK 0x2u +#define FTM_INVCTRL_INV1EN_SHIFT 1 +#define FTM_INVCTRL_INV2EN_MASK 0x4u +#define FTM_INVCTRL_INV2EN_SHIFT 2 +#define FTM_INVCTRL_INV3EN_MASK 0x8u +#define FTM_INVCTRL_INV3EN_SHIFT 3 +/* SWOCTRL Bit Fields */ +#define FTM_SWOCTRL_CH0OC_MASK 0x1u +#define FTM_SWOCTRL_CH0OC_SHIFT 0 +#define FTM_SWOCTRL_CH1OC_MASK 0x2u +#define FTM_SWOCTRL_CH1OC_SHIFT 1 +#define FTM_SWOCTRL_CH2OC_MASK 0x4u +#define FTM_SWOCTRL_CH2OC_SHIFT 2 +#define FTM_SWOCTRL_CH3OC_MASK 0x8u +#define FTM_SWOCTRL_CH3OC_SHIFT 3 +#define FTM_SWOCTRL_CH4OC_MASK 0x10u +#define FTM_SWOCTRL_CH4OC_SHIFT 4 +#define FTM_SWOCTRL_CH5OC_MASK 0x20u +#define FTM_SWOCTRL_CH5OC_SHIFT 5 +#define FTM_SWOCTRL_CH6OC_MASK 0x40u +#define FTM_SWOCTRL_CH6OC_SHIFT 6 +#define FTM_SWOCTRL_CH7OC_MASK 0x80u +#define FTM_SWOCTRL_CH7OC_SHIFT 7 +#define FTM_SWOCTRL_CH0OCV_MASK 0x100u +#define FTM_SWOCTRL_CH0OCV_SHIFT 8 +#define FTM_SWOCTRL_CH1OCV_MASK 0x200u +#define FTM_SWOCTRL_CH1OCV_SHIFT 9 +#define FTM_SWOCTRL_CH2OCV_MASK 0x400u +#define FTM_SWOCTRL_CH2OCV_SHIFT 10 +#define FTM_SWOCTRL_CH3OCV_MASK 0x800u +#define FTM_SWOCTRL_CH3OCV_SHIFT 11 +#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u +#define FTM_SWOCTRL_CH4OCV_SHIFT 12 +#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u +#define FTM_SWOCTRL_CH5OCV_SHIFT 13 +#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u +#define FTM_SWOCTRL_CH6OCV_SHIFT 14 +#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u +#define FTM_SWOCTRL_CH7OCV_SHIFT 15 +/* PWMLOAD Bit Fields */ +#define FTM_PWMLOAD_CH0SEL_MASK 0x1u +#define FTM_PWMLOAD_CH0SEL_SHIFT 0 +#define FTM_PWMLOAD_CH1SEL_MASK 0x2u +#define FTM_PWMLOAD_CH1SEL_SHIFT 1 +#define FTM_PWMLOAD_CH2SEL_MASK 0x4u +#define FTM_PWMLOAD_CH2SEL_SHIFT 2 +#define FTM_PWMLOAD_CH3SEL_MASK 0x8u +#define FTM_PWMLOAD_CH3SEL_SHIFT 3 +#define FTM_PWMLOAD_CH4SEL_MASK 0x10u +#define FTM_PWMLOAD_CH4SEL_SHIFT 4 +#define FTM_PWMLOAD_CH5SEL_MASK 0x20u +#define FTM_PWMLOAD_CH5SEL_SHIFT 5 +#define FTM_PWMLOAD_CH6SEL_MASK 0x40u +#define FTM_PWMLOAD_CH6SEL_SHIFT 6 +#define FTM_PWMLOAD_CH7SEL_MASK 0x80u +#define FTM_PWMLOAD_CH7SEL_SHIFT 7 +#define FTM_PWMLOAD_LDOK_MASK 0x200u +#define FTM_PWMLOAD_LDOK_SHIFT 9 + +/****************************************************************/ +/* */ +/* Periodic Interrupt Timer (PIT) */ +/* */ +/****************************************************************/ +/* MCR Bit Fields */ +#define PIT_MCR_FRZ 0x1u +#define PIT_MCR_MDIS 0x2u +/* LDVAL Bit Fields */ +#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu +#define PIT_LDVAL_TSV_SHIFT 0 +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) +/* CVAL Bit Fields */ +#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu +#define PIT_CVAL_TVL_SHIFT 0 +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) +/* TCTRL Bit Fields */ +#define PIT_TCTRL_TEN 0x1u +#define PIT_TCTRL_TIE 0x2u +/* TFLG Bit Fields */ +#define PIT_TFLG_TIF 0x1u + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for ADCx_SC1n register ***********/ +#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ +#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ +#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ +#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ +#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ +#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ + +/*********** Bits definition for ADCx_CFG1 register ***********/ +#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ +#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ +#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ +#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ +#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ +#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ +#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ +#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ +#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ +#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ +#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ + +/*********** Bits definition for ADCx_CFG2 register ***********/ +#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ +#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ +#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ +#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ +#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ +#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ + +/*********** Bits definition for ADCx_SC2 register ***********/ +#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ +#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ +#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ +#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ +#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ +#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ +#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ +#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ +#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ + +/*********** Bits definition for ADCx_SC3 register ***********/ +#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ +#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ +#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ +#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ +#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ +#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ +#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ +/********** Bits definition for LPTMRx_CSR register ***********/ +#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ +#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ +#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ +#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ +#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ +#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ +#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ +#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ +#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ + +/********** Bits definition for LPTMRx_PSR register ***********/ +#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ +#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ +#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ +#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ +#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ +#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ +#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ + +/********** Bits definition for LPTMRx_CMR register ***********/ +#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ +#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ +#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ + +/********** Bits definition for LPTMRx_CNR register ***********/ +#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ +#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ +#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)0x04) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)0x02) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)0x01) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)0x80) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x3 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)0x08) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)0x04) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)0x02) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)0x01) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)0x80) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x3 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0xF << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)0x01) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)0x40) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)0x20) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)0x1F) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)0x80) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)0x40) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)0x20) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_MASK ((uint8_t)0x1F) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)((uint8_t)(x) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)0x80) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)0x40) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)0x20) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)0x10) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x3 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)0x02) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)0x01) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)0x80) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)0x40) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)0x20) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)0x10) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x7 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)0x01) /*!< OSC0 Loss of Clock Status */ + +/************ Bits definition for MCG_C7 register **************/ +#define MCG_C7_OSCSEL ((uint8_t)0x01) /*!< MCG OSC Clock Select */ + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOCRE1 ((uint8_t)0x80) /*!< PLL Loss of Clock Reset Enable */ +#define MCG_C8_LOLRE ((uint8_t)0x40) /*!< PLL Loss of Lock Reset Enable */ +#define MCG_C8_CME1 ((uint8_t)0x20) /*!< PLL Clock Monitor Enable */ +#define MCG_C8_LOCS1 ((uint8_t)0x01) /*!< RTC Loss of Clock Status */ + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ + +/*********** Bits definition for SPIx_MCR register *************/ +#define SPIx_MCR_MSTR ((uint32_t)0x80000000) // Master/Slave Mode Select +#define SPIx_MCR_CONT_SCKE ((uint32_t)0x40000000) // Continuous SCK Enable +#define SPIx_MCR_DCONF(n) (((n) & 3) << 28) // DSPI Configuration +#define SPIx_MCR_FRZ ((uint32_t)0x08000000) // Freeze +#define SPIx_MCR_MTFE ((uint32_t)0x04000000) // Modified Timing Format Enable +#define SPIx_MCR_ROOE ((uint32_t)0x01000000) // Receive FIFO Overflow Overwrite Enable +#define SPIx_MCR_PCSIS(n) (((n) & 0x1F) << 16) // Peripheral Chip Select x Inactive State +#define SPIx_MCR_DOZE ((uint32_t)0x00008000) // Doze Enable +#define SPIx_MCR_MDIS ((uint32_t)0x00004000) // Module Disable +#define SPIx_MCR_DIS_TXF ((uint32_t)0x00002000) // Disable Transmit FIFO +#define SPIx_MCR_DIS_RXF ((uint32_t)0x00001000) // Disable Receive FIFO +#define SPIx_MCR_CLR_TXF ((uint32_t)0x00000800) // Clear the TX FIFO and counter +#define SPIx_MCR_CLR_RXF ((uint32_t)0x00000400) // Clear the RX FIFO and counter +#define SPIx_MCR_SMPL_PT(n) (((n) & 3) << 8) // Sample Point +#define SPIx_MCR_HALT ((uint32_t)0x00000001) // Halt + +/*********** Bits definition for SPIx_TCR register *************/ +#define SPIx_TCR_TCNT(n) (((n) & 0xffff) << 16) // DSPI Transfer Count Register + +/*********** Bits definition for SPIx_CTARn register *************/ +#define SPIx_CTARn_DBR ((uint32_t)0x80000000) // Double Baud Rate +#define SPIx_CTARn_FMSZ_SHIFT 27 // Frame Size Shift +#define SPIx_CTARn_FMSZ_MASK 0xF // Frame Size Mask +#define SPIx_CTARn_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) +#define SPIx_CTARn_CPOL ((uint32_t)0x04000000) // Clock Polarity +#define SPIx_CTARn_CPHA ((uint32_t)0x02000000) // Clock Phase +#define SPIx_CTARn_LSBFE ((uint32_t)0x01000000) // LSB First +#define SPIx_CTARn_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler +#define SPIx_CTARn_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler +#define SPIx_CTARn_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler +#define SPIx_CTARn_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler +#define SPIx_CTARn_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler +#define SPIx_CTARn_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler +#define SPIx_CTARn_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler +#define SPIx_CTARn_BR(n) (((n) & 15) << 0) // Baud Rate Scaler + + +/*********** Bits definition for SPIx_CTARn_SLAVE register *************/ +#define SPIx_CTARn_SLAVE_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1) +#define SPIx_CTARn_SLAVE_CPOL ((uint32_t)0x04000000) // Clock Polarity +#define SPIx_CTARn_SLAVE_CPHA ((uint32_t)0x02000000) // Clock Phase + +/*********** Bits definition for SPIx_SR register *************/ +#define SPIx_SR_TCF ((uint32_t)0x80000000) // Transfer Complete Flag +#define SPIx_SR_TXRXS ((uint32_t)0x40000000) // TX and RX Status +#define SPIx_SR_EOQF ((uint32_t)0x10000000) // End of Queue Flag +#define SPIx_SR_TFUF ((uint32_t)0x08000000) // Transmit FIFO Underflow Flag +#define SPIx_SR_TFFF ((uint32_t)0x02000000) // Transmit FIFO Fill Flag +#define SPIx_SR_RFOF ((uint32_t)0x00080000) // Receive FIFO Overflow Flag +#define SPIx_SR_RFDF ((uint32_t)0x00020000) // Receive FIFO Drain Flag +#define SPIx_SR_TXCTR (((n) & 15) << 12) // TX FIFO Counter +#define SPIx_SR_TXNXPTR (((n) & 15) << 8) // Transmit Next Pointer +#define SPIx_SR_RXCTR (((n) & 15) << 4) // RX FIFO Counter +#define SPIx_SR_POPNXTPTR ((n) & 15) // POP Next Pointer + +/*********** Bits definition for SPIx_SR register *************/ +#define SPIx_RSER_TCF_RE ((uint32_t)0x80000000) // Transmission Complete Request Enable +#define SPIx_RSER_EOQF_RE ((uint32_t)0x10000000) // DSPI Finished Request Request Enable +#define SPIx_RSER_TFUF_RE ((uint32_t)0x08000000) // Transmit FIFO Underflow Request Enable +#define SPIx_RSER_TFFF_RE ((uint32_t)0x02000000) // Transmit FIFO Fill Request Enable +#define SPIx_RSER_TFFF_DIRS ((uint32_t)0x01000000) // Transmit FIFO FIll Dma or Interrupt Request Select +#define SPIx_RSER_RFOF_RE ((uint32_t)0x00080000) // Receive FIFO Overflow Request Enable +#define SPIx_RSER_RFDF_RE ((uint32_t)0x00020000) // Receive FIFO Drain Request Enable +#define SPIx_RSER_RFDF_DIRS ((uint32_t)0x00010000) // Receive FIFO Drain DMA or Interrupt Request Select + +/*********** Bits definition for SPIx_PUSHR register *************/ +#define SPIx_PUSHR_CONT ((uint32_t)0x80000000) // Continuous Peripheral Chip Select Enable +#define SPIx_PUSHR_CTAS(n) (((n) & 7) << 28) // Clock and Transfer Attributes Select +#define SPIx_PUSHR_EOQ ((uint32_t)0x08000000) // End Of Queue +#define SPIx_PUSHR_CTCNT ((uint32_t)0x04000000) // Clear Transfer Counter +#define SPIx_PUSHR_PCS(n) (((n) & 31) << 16) // Peripheral Chip Select +#define SPIx_PUSHR_TXDATA(n) ((n) & 0xffff) // Transmit Data + +/*********** Bits definition for SPIx_PUSHR_SLAVE register *************/ +#define SPIx_PUSHR_SLAVE_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data in slave mode + +/*********** Bits definition for SPIx_POPR register *************/ +#define SPIx_POPR_RXDATA(n) (((n) & 0xffff) << 16) // Received Data + +/*********** Bits definition for SPIx_TXFRn register *************/ +#define SPIx_TXFRn_TXCMD_TXDATA (((n) & 0xffff) << 16) // Transmit Command (in master mode) +#define SPIx_TXFRn_TXDATA(n) (((n) & 0xffff) << 0) // Transmit Data + +/*********** Bits definition for SPIx_RXFRn register *************/ +#define SPIx_RXFRn_RXDATA(n) (((n) & 0xffff) << 0) // Receive Data + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ + +#define I2Cx_A1_AD_SHIT 1 + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ + +#define I2Cx_F_MULT_SHIFT 5 + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ + +#define I2Cx_RA_RAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ + +#define I2Cx_A2_SAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RxD Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBR_MASK ((uint8_t)0x1F) +#define UARTx_BDH_SBR(x) ((uint8_t)((uint8_t)(x) & UARTx_BDH_SBR_MASK)) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR_MASK ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_BRFA_MASK ((uint8_t)0x1F) +#define UARTx_C4_BRFA(x) ((uint8_t)((uint8_t)(x) & UARTx_C4_BRFA_MASK)) /*!< Baud Rate Fine Adjust */ + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ + +/******* Bits definition for UARTx_CFIFO register ************/ +#define UARTx_CFIFO_TXFLUSH ((uint8_t)0x80) /*!< Transmit FIFO/Buffer Flush */ +#define UARTx_CFIFO_RXFLUSH ((uint8_t)0x40) /*!< Receive FIFO/Buffer Flush */ +#define UARTx_CFIFO_RXOFE ((uint8_t)0x04) /*!< Receive FIFO Overflow Interrupt Enable */ +#define UARTx_CFIFO_TXOFE ((uint8_t)0x02) /*!< Transmit FIFO Overflow Interrupt Enable */ +#define UARTx_CFIFO_RXUFE ((uint8_t)0x01) /*!< Receive FIFO Underflow Interrupt Enable */ + +/******* Bits definition for UARTx_PFIFO register ************/ +#define UARTx_PFIFO_TXFE ((uint8_t)0x80) /*!< Transmit FIFO Enable */ +#define UARTx_PFIFO_TXFIFOSIZE_SHIFT 4 +#define UARTx_PFIFO_TXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_TXFIFOSIZE_SHIFT)) +#define UARTx_PFIFO_TXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_TXFIFOSIZE_SHIFT) & UARTx_PFIFO_TXFIFOSIZE_MASK)) /*!< Transmit FIFO Buffer depth */ +#define UARTx_PFIFO_RXFE ((uint8_t)0x08) /*!< Receive FIFOh */ +#define UARTx_PFIFO_RXFIFOSIZE_SHIFT 0 +#define UARTx_PFIFO_RXFIFOSIZE_MASK ((uint8_t)((uint8_t)0x7 << UARTx_PFIFO_RXFIFOSIZE_SHIFT)) +#define UARTx_PFIFO_RXFIFOSIZE(x) ((uint8_t)(((uint8_t)(x) << UARTx_PFIFO_RXFIFOSIZE_SHIFT) & UARTx_PFIFO_RXFIFOSIZE_MASK)) /*!< Receive FIFO Buffer depth */ + +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ +#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ +#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ +#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ +#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ +#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ +#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ +#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +/********* Bits definition for PMC_REGSC register *************/ +#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ +#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ +#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ +#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ + +/****************************************************************/ +/* */ +/* Watchdog */ +/* */ +/****************************************************************/ +/******** Bits definition for WDOG_STCTRLH register ***********/ +#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) +#define WDOG_STCTRLH_BYTESEL_1_0 ((uint16_t)0x3000) +#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800) +#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400) +#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080) +#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040) +#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020) +#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010) +#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008) +#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004) +#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002) +#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001) + +/******** Bits definition for WDOG_STCTRLL register ***********/ +#define WDOG_STCTRLL_INTFLG ((uint16_t)0x8000) + +/********* Bits definition for WDOG_PRESC register ************/ +#define WDOG_PRESC_PRESCVAL ((uint16_t)0x0700) + +/****************************************************************/ +/* */ +/* USB OTG */ +/* */ +/****************************************************************/ +/******** Bits definition for USBx_ISTAT register *************/ +#define USBx_ISTAT_STALL ((uint8_t)0x80) /*!< Stall interrupt */ +#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */ +#define USBx_ISTAT_RESUME ((uint8_t)0x20) /*!< Signal remote wakeup on the bus */ +#define USBx_ISTAT_SLEEP ((uint8_t)0x10) /*!< Detected bus idle for 3ms */ +#define USBx_ISTAT_TOKDNE ((uint8_t)0x08) /*!< Completed processing of current token */ +#define USBx_ISTAT_SOFTOK ((uint8_t)0x04) /*!< Received start of frame */ +#define USBx_ISTAT_ERROR ((uint8_t)0x02) /*!< Error (must check ERRSTAT!) */ +#define USBx_ISTAT_USBRST ((uint8_t)0x01) /*!< USB reset detected */ + +/******** Bits definition for USBx_ERRSTAT register ***********/ +#define USBx_ERRSTAT_BTSERR ((uint8_t)0x80) /*!< Bit stuff error detected */ +#define USBx_ERRSTAT_DMAERR ((uint8_t)0x20) /*!< DMA request was not given */ +#define USBx_ERRSTAT_BTOERR ((uint8_t)0x10) /*!< BUS turnaround timeout error */ +#define USBx_ERRSTAT_DFN8 ((uint8_t)0x08) /*!< Received data not 8-bit sized */ +#define USBx_ERRSTAT_CRC16 ((uint8_t)0x04) /*!< Packet with CRC16 error */ +#define USBx_ERRSTAT_CRC5EOF ((uint8_t)0x02) /*!< CRC5 (device) or EOF (host) error */ +#define USBx_ERRSTAT_PIDERR ((uint8_t)0x01) /*!< PID check field fail */ + +/******** Bits definition for USBx_CTL register *****************/ +#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ +#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ +#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */ +#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ +#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ +#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ +#define USBx_CTL_ODDRST ((uint8_t)0x02) /*!< Reset all BDT ODD ping/pong bits */ +#define USBx_CTL_USBENSOFEN ((uint8_t)0x01) /*!< USB Enable! */ + +/******** Bits definition for USBx_INTEN register ***************/ +#define USBx_INTEN_STALLEN ((uint8_t)0x80) /*!< STALL interrupt enable */ +#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */ +#define USBx_INTEN_RESUMEEN ((uint8_t)0x20) /*!< RESUME interrupt enable */ +#define USBx_INTEN_SLEEPEN ((uint8_t)0x10) /*!< SLEEP interrupt enable */ +#define USBx_INTEN_TOKDNEEN ((uint8_t)0x08) /*!< TOKDNE interrupt enable */ +#define USBx_INTEN_SOFTOKEN ((uint8_t)0x04) /*!< SOFTOK interrupt enable */ +#define USBx_INTEN_ERROREN ((uint8_t)0x02) /*!< ERROR interrupt enable */ +#define USBx_INTEN_USBRSTEN ((uint8_t)0x01) /*!< USBRST interrupt enable */ + +/******** Bits definition for USBx_ENDPTn register **************/ +#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80) +#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40) +#define USBx_ENDPTn_EPCTLDIS ((uint8_t)0x10) /*!< Disables control transfers */ +#define USBx_ENDPTn_EPRXEN ((uint8_t)0x08) /*!< Enable RX transfers */ +#define USBx_ENDPTn_EPTXEN ((uint8_t)0x04) /*!< Enable TX transfers */ +#define USBx_ENDPTn_EPSTALL ((uint8_t)0x02) /*!< Endpoint is called and in STALL */ +#define USBx_ENDPTn_EPHSHK ((uint8_t)0x01) /*!< Enable handshaking during transaction */ + +/******** Bits definition for USBx_CTRL register ****************/ +#define USBx_CTRL_SUSP ((uint8_t)0x80) /*!< USB transceiver in suspend state */ +#define USBx_CTRL_PDE ((uint8_t)0x40) /*!< Enable weak pull-downs */ + +/******** Bits definition for USBx_USBTRC0 register *************/ +#define USBx_USBTRC0_USBRESET ((uint8_t)0x80) /*!< USB reset */ +#define USBx_USBTRC0_USBRESMEN ((uint8_t)0x20) /*!< Asynchronous resume interrupt enable */ +#define USBx_USBTRC0_SYNC_DET ((uint8_t)0x02) /*!< Synchronous USB interrupt detect */ +#define USBx_USBTRC0_USB_RESUME_INT ((uint8_t)0x01) /*!< USB asynchronous interrupt */ + +/******** Bits definition for USBx_CONTROL register *************/ +#define USBx_CONTROL_DPPULLUPNONOTG ((uint8_t)0x10) /*!< Control pull-ups in device mode */ + +#endif diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.c b/os/hal/ports/KINETIS/K20x/pal_lld.c new file mode 100644 index 0000000..101d574 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pal_lld.c @@ -0,0 +1,241 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK20D5/pal_lld.c
+ * @brief PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+uint8_t _pal_lld_readpad(ioportid_t port,
+ uint8_t pad) {
+
+ return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
+}
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+void _pal_lld_writepad(ioportid_t port,
+ uint8_t pad,
+ uint8_t bit) {
+
+ if (bit == PAL_HIGH)
+ port->PDOR |= ((uint32_t) 1 << pad);
+ else
+ port->PDOR &= ~((uint32_t) 1 << pad);
+}
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+void _pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode) {
+
+ PORT_TypeDef *portcfg = NULL;
+
+ chDbgAssert(pad <= 31, "pal_lld_setpadmode() #1, invalid pad");
+
+ if (mode == PAL_MODE_OUTPUT_PUSHPULL)
+ port->PDDR |= ((uint32_t) 1 << pad);
+ else
+ port->PDDR &= ~((uint32_t) 1 << pad);
+
+ if (port == IOPORT1)
+ portcfg = PORTA;
+ else if (port == IOPORT2)
+ portcfg = PORTB;
+ else if (port == IOPORT3)
+ portcfg = PORTC;
+ else if (port == IOPORT4)
+ portcfg = PORTD;
+ else if (port == IOPORT5)
+ portcfg = PORTE;
+
+ chDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");
+
+ switch (mode) {
+ case PAL_MODE_RESET:
+ case PAL_MODE_INPUT:
+ case PAL_MODE_OUTPUT_PUSHPULL:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
+ break;
+ case PAL_MODE_OUTPUT_OPENDRAIN:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_ODE;
+ break;
+ case PAL_MODE_INPUT_PULLUP:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_PE |
+ PORTx_PCRn_PS;
+ break;
+ case PAL_MODE_INPUT_PULLDOWN:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_PE;
+ break;
+ case PAL_MODE_UNCONNECTED:
+ case PAL_MODE_INPUT_ANALOG:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(0);
+ break;
+ case PAL_MODE_ALTERNATIVE_1:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
+ break;
+ case PAL_MODE_ALTERNATIVE_2:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(2);
+ break;
+ case PAL_MODE_ALTERNATIVE_3:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(3);
+ break;
+ case PAL_MODE_ALTERNATIVE_4:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(4);
+ break;
+ case PAL_MODE_ALTERNATIVE_5:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(5);
+ break;
+ case PAL_MODE_ALTERNATIVE_6:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(6);
+ break;
+ case PAL_MODE_ALTERNATIVE_7:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(7);
+ break;
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Kinetis I/O ports configuration.
+ * @details Ports A-E clocks enabled.
+ *
+ * @param[in] config the Kinetis ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ int i, j;
+
+ /* Enable clocking on all Ports */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+ /* Initial PORT and GPIO setup */
+ for (i = 0; i < TOTAL_PORTS; i++) {
+ for (j = 0; j < PADS_PER_PORT; j++) {
+ pal_lld_setpadmode(config->ports[i].port,
+ j,
+ config->ports[i].pads[j]);
+ }
+ }
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+
+ int i;
+
+ (void)mask;
+
+ for (i = 0; i < PADS_PER_PORT; i++) {
+ pal_lld_setpadmode(port, i, mode);
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/pal_lld.h b/os/hal/ports/KINETIS/K20x/pal_lld.h new file mode 100644 index 0000000..242583a --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/pal_lld.h @@ -0,0 +1,375 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK20D5/pal_lld.h
+ * @brief PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#define PAL_MODE_ALTERNATIVE_1 10
+#define PAL_MODE_ALTERNATIVE_2 11
+#define PAL_MODE_ALTERNATIVE_3 12
+#define PAL_MODE_ALTERNATIVE_4 13
+#define PAL_MODE_ALTERNATIVE_5 14
+#define PAL_MODE_ALTERNATIVE_6 15
+#define PAL_MODE_ALTERNATIVE_7 16
+
+#define PIN_MUX_ALTERNATIVE(x) PORTx_PCRn_MUX(x)
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+#define TOTAL_PORTS 5
+#define PADS_PER_PORT 32
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef GPIO_TypeDef *ioportid_t;
+
+/**
+ * @brief Port Configuration.
+ * @details This structure stores the configuration parameters of all pads
+ * belonging to a port.
+ */
+typedef struct {
+ ioportid_t port;
+ iomode_t pads[PADS_PER_PORT];
+} PortConfig;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ PortConfig ports[TOTAL_PORTS];
+} PALConfig;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO port A identifier.
+ */
+#define IOPORT1 GPIOA
+
+/**
+ * @brief GPIO port B identifier.
+ */
+#define IOPORT2 GPIOB
+
+/**
+ * @brief GPIO port C identifier.
+ */
+#define IOPORT3 GPIOC
+
+/**
+ * @brief GPIO port D identifier.
+ */
+#define IOPORT4 GPIOD
+
+/**
+ * @brief GPIO port E identifier.
+ */
+#define IOPORT5 GPIOE
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) (port)->PDIR
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) (port)->PDOR
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) (port)->PDOR = (bits)
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) (port)->PSOR = (bits)
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) (port)->PCOR = (bits)
+
+/**
+ * @brief Toggles a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be toggled on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_toggleport(port, bits) (port)->PTOR = (bits)
+
+/**
+ * @brief Reads a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) 0
+
+/**
+ * @brief Writes a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) _pal_lld_readpad(port, pad)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) _pal_lld_writepad(port, pad, bit)
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode) \
+ _pal_lld_setpadmode(port, pad, mode)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+ void _pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/platform.dox b/os/hal/ports/KINETIS/K20x/platform.dox new file mode 100644 index 0000000..3fb142d --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/platform.dox @@ -0,0 +1,365 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/* TODO Still need to edit this entire file */
+
+/**
+ * @defgroup MK20D5_DRIVERS MK20D5 Drivers
+ * @details This section describes all the supported drivers on the MK20D5
+ * platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup MK20D5_HAL MK20D5 Initialization Support
+ * @details The MK20D5 HAL support is responsible for system initialization.
+ *
+ * @section mk20d5_hal_1 Supported HW resources
+ * - PLL1.
+ * - PLL2.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section mk20d5_hal_2 MK20D5 HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ADC MK20D5 ADC Support
+ * @details The MK20D5 ADC driver supports the ADC peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_adc_1 Supported HW resources
+ * - ADC1.
+ * - ADC2.
+ * - ADC3.
+ * - DMA2.
+ * .
+ * @section mk20d5_adc_2 MK20D5 ADC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Streaming conversion using DMA for maximum performance.
+ * - Programmable ADC interrupt priority level.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - DMA and ADC errors detection.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_CAN MK20D5 CAN Support
+ * @details The MK20D5 CAN driver uses the CAN peripherals.
+ *
+ * @section mk20d5_can_1 Supported HW resources
+ * - bxCAN1.
+ * .
+ * @section mk20d5_can_2 MK20D5 CAN driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Support for bxCAN sleep mode.
+ * - Programmable bxCAN interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_EXT MK20D5 EXT Support
+ * @details The MK20D5 EXT driver uses the EXTI peripheral.
+ *
+ * @section mk20d5_ext_1 Supported HW resources
+ * - EXTI.
+ * .
+ * @section mk20d5_ext_2 MK20D5 EXT driver implementation features
+ * - Each EXTI channel can be independently enabled and programmed.
+ * - Programmable EXTI interrupts priority level.
+ * - Capability to work as event sources (WFE) rather than interrupt sources.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_GPT MK20D5 GPT Support
+ * @details The MK20D5 GPT driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_gpt_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_gpt_2 MK20D5 GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ICU MK20D5 ICU Support
+ * @details The MK20D5 ICU driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_icu_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_icu_2 MK20D5 ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_MAC MK20D5 MAC Support
+ * @details The MK20D5 MAC driver supports the ETH peripheral.
+ *
+ * @section mk20d5_mac_1 Supported HW resources
+ * - ETH.
+ * - PHY (external).
+ * .
+ * @section mk20d5_mac_2 MK20D5 MAC driver implementation features
+ * - Dedicated DMA operations.
+ * - Support for checksum off-loading.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PAL MK20D5 PAL Support
+ * @details The MK20D5 PAL driver uses the GPIO peripherals.
+ *
+ * @section mk20d5_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOF.
+ * - GPIOG.
+ * - GPIOH.
+ * - GPIOI.
+ * .
+ * @section mk20d5_pal_2 MK20D5 PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section mk20d5_pal_3 Supported PAL setup modes
+ * The MK20D5 PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_ALTERNATE (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section mk20d5_pal_4 Suboptimal behavior
+ * The MK20D5 GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PWM MK20D5 PWM Support
+ * @details The MK20D5 PWM driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_pwm_2 MK20D5 PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SDC MK20D5 SDC Support
+ * @details The MK20D5 SDC driver uses the SDIO peripheral.
+ *
+ * @section mk20d5_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section mk20d5_sdc_2 MK20D5 SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SERIAL MK20D5 Serial Support
+ * @details The MK20D5 Serial driver uses the USART/UART peripherals in a
+ * buffered, interrupt driven, implementation.
+ *
+ * @section mk20d5_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - UART4.
+ * - UART5.
+ * - USART6.
+ * .
+ * @section mk20d5_serial_2 MK20D5 Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SPI MK20D5 SPI Support
+ * @details The SPI driver supports the MK20D5 SPI peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - SPI3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_spi_2 MK20D5 SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_UART MK20D5 UART Support
+ * @details The UART driver supports the MK20D5 USART peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_uart_2 MK20D5 UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PLATFORM_DRIVERS MK20D5 Platform Drivers
+ * @details Platform support drivers. Platform drivers do not implement HAL
+ * standard driver templates, their role is to support platform
+ * specific functionalities.
+ *
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_DMA MK20D5 DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ * access the shared DMA resources in a consistent way.
+ *
+ * @section mk20d5_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_dma_2 MK20D5 DMA driver implementation features
+ * - Exports helper functions/macros to the other drivers that share the
+ * DMA resource.
+ * - Automatic DMA clock stop when not in use by any driver.
+ * - DMA streams and interrupt vectors sharing among multiple drivers.
+ * .
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ISR MK20D5 ISR Support
+ * @details This ISR helper driver is used by the other drivers in order to
+ * map ISR names to physical vector names.
+ *
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_RCC MK20D5 RCC Support
+ * @details This RCC helper driver is used by the other drivers in order to
+ * access the shared RCC resources in a consistent way.
+ *
+ * @section mk20d5_rcc_1 Supported HW resources
+ * - RCC.
+ * .
+ * @section mk20d5_rcc_2 MK20D5 RCC driver implementation features
+ * - Peripherals reset.
+ * - Peripherals clock enable.
+ * - Peripherals clock disable.
+ * .
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
diff --git a/os/hal/ports/KINETIS/K20x/platform.mk b/os/hal/ports/KINETIS/K20x/platform.mk new file mode 100644 index 0000000..c7ae92d --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/platform.mk @@ -0,0 +1,16 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/gpt_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x/st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS}/os/hal/ports/KINETIS/K20x \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.c b/os/hal/ports/KINETIS/K20x/serial_lld.c new file mode 100644 index 0000000..0092747 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/serial_lld.c @@ -0,0 +1,327 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/serial_lld.c
+ * @brief Kinetis K20x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+#include "mk20d5.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] u pointer to an UART I/O block
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UART_TypeDef *u = sdp->uart;
+ uint8_t s1 = u->S1;
+
+ if (s1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (s1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ u->C2 &= ~UARTx_C2_TIE;
+ } else {
+ u->D = b;
+ }
+ }
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UART_TypeDef *u = sdp->uart;
+
+ if (u->S1 & UARTx_S1_TDRE) {
+ msg_t b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ u->D = b;
+ u->C2 |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(UART_TypeDef *uart, const SerialConfig *config)
+{
+ uint32_t divisor = (KINETIS_SYSCLK_FREQUENCY * 2 + 1) / config->sc_speed;
+
+ /* Disable UART while configuring */
+ uart->C2 &= ~(UARTx_C2_RE | UARTx_C2_TE);
+ uart->C1 = 0;
+
+ uart->BDH = UARTx_BDH_SBR(divisor >> 13) | (uart->BDH & ~UARTx_BDH_SBR_MASK);
+ uart->BDL = divisor >> 5;
+ uart->C4 = UARTx_C4_BRFA(divisor) | (uart->C4 & ~UARTx_C4_BRFA_MASK);
+
+ uart->C2 |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+ uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/* TODO:
+ * UART0_Error is Vector84
+ * UART1_Error is Vector8C
+ * UART2_Error is Vector94
+ */
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector80) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector88) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector90) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.uart = UART0;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+ SD2.uart = UART1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart = UART2;
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ nvicDisableVector(UART0Status_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ nvicDisableVector(UART1Status_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ nvicDisableVector(UART2Status_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/serial_lld.h b/os/hal/ports/KINETIS/K20x/serial_lld.h new file mode 100644 index 0000000..736cfe3 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/serial_lld.h @@ -0,0 +1,163 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/serial_lld.h
+ * @brief Kinetis K20x Serial Driver subsystem low level driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SD1 driver enable switch.
+ * @details If set to @p TRUE the support for SD1 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART0 FALSE
+#endif
+/**
+ * @brief SD2 driver enable switch.
+ * @details If set to @p TRUE the support for SD2 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART1 FALSE
+#endif
+/**
+ * @brief SD3 driver enable switch.
+ * @details If set to @p TRUE the support for SD3 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART2 FALSE
+#endif
+
+/**
+ * @brief UART0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART0_PRIORITY 12
+#endif
+
+/**
+ * @brief UART1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART1_PRIORITY 12
+#endif
+
+/**
+ * @brief UART2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART2_PRIORITY 12
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /* End of the mandatory fields.*/
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the UART registers block.*/ \
+ UART_TypeDef *uart;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.c b/os/hal/ports/KINETIS/K20x/spi_lld.c new file mode 100644 index 0000000..132580f --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/spi_lld.c @@ -0,0 +1,418 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.c
+ * @brief KINETIS SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SPI_USE_SPI0)
+#define KINETIS_SPI_USE_SPI0 TRUE
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
+#define KINETIS_SPI0_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
+#define KINETIS_SPI0_TX_DMA_CHANNEL 1
+#endif
+
+#define DMAMUX_SPI_RX_SOURCE 16
+#define DMAMUX_SPI_TX_SOURCE 17
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief SPI0 driver identifier.*/
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/* Use a dummy byte as the source/destination when a buffer is not provided */
+/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
+static volatile uint16_t dmaRxDummy;
+static uint16_t dmaTxDummy = 0xFFFF;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void spi_start_xfer(SPIDriver *spip, bool polling)
+{
+ /*
+ * Enable the DSPI peripheral in master mode.
+ * Clear the TX and RX FIFOs.
+ * */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
+
+ /* If we are not polling then enable DMA */
+ if (!polling) {
+
+ /* Enable receive dma and transmit dma */
+ spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
+ SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
+
+ /* Configure RX DMA */
+ if (spip->rxbuf) {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ /* Configure TX DMA */
+ if (spip->txbuf) {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
+ }
+}
+
+static void spi_stop_xfer(SPIDriver *spip)
+{
+ /* Halt the DSPI peripheral */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
+
+ /* Clear all the flags which are currently set. */
+ spip->spi->SR |= spip->spi->SR;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+OSAL_IRQ_HANDLER(Vector40) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID1);
+
+ _spi_isr_code(&SPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+#if KINETIS_SPI_USE_SPI0
+ spiObjectInit(&SPID1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (spip->state == SPI_STOP) {
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI0;
+
+ SPID1.spi = SPI0;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
+ nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
+
+ SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
+ SIM->SCGC7 |= SIM_SCGC7_DMA;
+
+ /* Clear DMA error flags */
+ DMA->ERR = 0x0F;
+
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+ }
+}
+
+/**
+ * @brief Deactivates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (spip->state == SPI_READY) {
+
+ nvicDisableVector(DMA0_IRQn);
+
+ SIM->SCGC7 &= ~SIM_SCGC7_DMA;
+ SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+#endif
+
+ /* Disable the clock for SPI0 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+ }
+}
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+ palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+ palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ * idle words on the SPI bus and ignores the received data.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ * operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = (void *)txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ * synchronization method. This function is useful when exchanging
+ * small amount of data on high speed channels, usually in this
+ * situation is much more efficient just wait for completion using
+ * polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] frame the data frame to send over the SPI bus
+ * @return The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+ spi_start_xfer(spip, true);
+
+ spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
+
+ while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
+ ;
+
+ frame = spip->spi->POPR;
+
+ spi_stop_xfer(spip);
+
+ return frame;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/spi_lld.h b/os/hal/ports/KINETIS/K20x/spi_lld.h new file mode 100644 index 0000000..23c6812 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/spi_lld.h @@ -0,0 +1,230 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.h
+ * @brief KINETIS SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPI_LLD_H_
+#define _SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SPI0 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI0 FALSE
+#endif
+
+/**
+ * @brief SPI0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#define KINETIS_HAS_SPI0 TRUE
+
+#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
+#error "SPI0 not present in the selected device"
+#endif
+
+#if !KINETIS_SPI_USE_SPI0
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI0"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief SPI notification callback type.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object triggering the
+ * callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ spicallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief The chip select line port - when not using pcs.
+ */
+ ioportid_t ssport;
+ /**
+ * @brief The chip select line pad number - when not using pcs.
+ */
+ uint16_t sspad;
+ /**
+ * @brief SPI initialization data.
+ */
+ uint32_t tar0;
+} SPIConfig;
+
+/**
+ * @brief Structure representing a SPI driver.
+ */
+struct SPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ spistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const SPIConfig *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+ SPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Number of bytes/words of data to transfer.
+ */
+ size_t count;
+ /**
+ * @brief Word size in bytes.
+ */
+ size_t word_size;
+ /**
+ * @brief Pointer to the buffer with data to send.
+ */
+ const uint8_t *txbuf;
+ /**
+ * @brief Pointer to the buffer to put received data.
+ */
+ uint8_t *rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/* TAR settings for n bits at SYSCLK / 2 */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
+ SPIx_CTARn_FMSZ((n) - 1) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_DBR | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0) | \
+ SPIx_CTARn_CSSCK(0) | \
+ SPIx_CTARn_ASC(0) | \
+ SPIx_CTARn_DT(0)
+
+/* TAR settings for n bits at SYSCLK / 4096 for debugging */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
+ SPIx_CTARn_FMSZ(((n) - 1)) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0xB) | \
+ SPIx_CTARn_CSSCK(0xB) | \
+ SPIx_CTARn_ASC(0x7) | \
+ SPIx_CTARn_DT(0xB)
+
+#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
+
+#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void spi_lld_init(void);
+ void spi_lld_start(SPIDriver *spip);
+ void spi_lld_stop(SPIDriver *spip);
+ void spi_lld_select(SPIDriver *spip);
+ void spi_lld_unselect(SPIDriver *spip);
+ void spi_lld_ignore(SPIDriver *spip, size_t n);
+ void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf);
+ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* _SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.c b/os/hal/ports/KINETIS/K20x/st_lld.c new file mode 100644 index 0000000..1f8cb63 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/st_lld.c @@ -0,0 +1,98 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/KL2x/st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+ in this mode.*/
+ SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+
+ /* IRQ enabled.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K20x/st_lld.h b/os/hal/ports/KINETIS/K20x/st_lld.h new file mode 100644 index 0000000..24044e5 --- /dev/null +++ b/os/hal/ports/KINETIS/K20x/st_lld.h @@ -0,0 +1,156 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ST_IRQ_PRIORITY 8
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.c b/os/hal/ports/KINETIS/KL2x/hal_lld.c new file mode 100644 index 0000000..dce1588 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.c @@ -0,0 +1,307 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.c
+ * @brief Kinetis KL2x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used, section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+}
+
+/**
+ * @brief KL2x clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void kl2x_clock_init(void) {
+#if !KINETIS_NO_INIT
+ /* Disable COP watchdog */
+ SIM->COPC = 0;
+
+ /* Enable PORTA */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA;
+
+ /* --- MCG mode: FEI (default out of reset) ---
+ f_MCGOUTCLK = f_int * F
+ F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits.
+ Typical f_MCGOUTCLK = 21 MHz immediately after reset.
+ C4[DMX32]=0 and C4[DRST_DRS]=00 => FLL factor=640.
+ C3[SCTRIM] and C4[SCFTRIM] factory trim values apply to f_int. */
+
+ /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
+ SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 24 MHz */
+ SIM_CLKDIV1_OUTDIV4(0); /* OUTDIV4 = divide-by-1 => 24 MHz */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
+ /*
+ * FLL Enabled External (FEE) MCG Mode
+ * 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
+ * f_MCGOUTCLK = (f_ext / FLL_R) * F
+ * = (32.768 kHz ) *
+ * FLL_R is the reference divider selected by C1[FRDIV]
+ * F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32].
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 48 MHz / 1 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = MHz / 4 = 24 MHz
+ */
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1); /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ /* PLLFLLSEL=0 -> MCGFLLCLK */
+
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_MCG_FLL_OUTDIV1 - 1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_MCG_FLL_OUTDIV4 - 1);
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ OSC0->CR = 0;
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FEE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor, for 32.768 kHz crystal configuration. */
+ MCG->C2 =
+ MCG_C2_RANGE0(0) | /* low frequency range (<= 40 kHz) */
+ MCG_C2_EREFS0; /* external reference (using a crystal) */
+ /* (2) Write to C1 to select the clock mode. */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_FLLPLL | /* Use FLL for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(0); /* Don't divide 32kHz ERCLK FLL reference. */
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] indicates FLL feeds MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_FLL)
+ ; /* Wait until FLL has been selected. */
+
+ /* --- MCG mode: FEE --- */
+ /* Set frequency range for DCO output (MCGFLLCLK). */
+ MCG->C4 = (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0) |
+ MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS);
+
+ /* Wait for the FLL lock time; t[fll_acquire][max] = 1 ms */
+ /* TODO - not implemented - is it required? Freescale example code
+ seems to omit it. */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ /*
+ * PLL Enabled External (PEE) MCG Mode
+ * 48 MHz core, 24 MHz bus - using 8 MHz crystal with PLL.
+ * f_MCGOUTCLK = (OSCCLK / PLL_R) * M
+ * = 8 MHz / 2 * 24 = 96 MHz
+ * PLL_R is the reference divider selected by C5[PRDIV0]
+ * M is the multiplier selected by C6[VDIV0]
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
+ */
+
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(1) | /* OUTDIV1 = divide-by-2 => 48 MHz */
+ SIM_CLKDIV1_OUTDIV4(1); /* OUTDIV4 = divide-by-2 => 24 MHz */
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ OSC0->CR = 0;
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FBE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
+ Use high-gain mode by setting C2[HGO0] instead if external
+ feedback resistor Rf is installed. */
+ MCG->C2 =
+ MCG_C2_RANGE0(2) | /* very high frequency range */
+ MCG_C2_EREFS0; /* external reference (using a crystal) */
+ /* (2) Write to C1 to select the clock mode. */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_ERCLK | /* Use ERCLK for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(3); /* Divide ERCLK / 256 for FLL reference. */
+ /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz.
+ 8 MHz / 256 = 31.25 kHz. */
+ MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* (3) Once configuration is set, wait for MCG mode change. */
+
+ /* From KL25P80M48SF0RM section 24.5.31: */
+ /* (1)(c) Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* (1)(d) Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] is 2'b10, indicating
+ the external reference clock is selected to feed MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_ERCLK)
+ ; /* Wait until external reference clock has been selected. */
+
+ /* --- MCG mode: FBE (FLL bypassed, external crystal) ---
+ Now the MCG is in FBE mode.
+ Although the FLL is bypassed, it is still on. */
+
+ /* (2) Then configure C5[PRDIV0] to generate the
+ correct PLL reference frequency. */
+ MCG->C5 = MCG_C5_PRDIV0(1); /* PLL External Reference Divide by 2 */
+ /* (3) Then from FBE transition to PBE mode. */
+ /* (3)(b) C6[PLLS]=1 to select PLL. */
+ /* (3)(b) C6[VDIV0]=5'b0000 (x24) 2 MHz * 24 = 48 MHz. */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+ /* (3)(d) Loop until S[PLLST], indicating PLL
+ is the PLLS clock source. */
+ while ((MCG->S & MCG_S_PLLST) == 0)
+ ; /* wait until PLL is the PLLS clock source. */
+ /* (3)(e) Loop until S[LOCK0] is set, indicating the PLL has acquired lock. */
+ /* PLL selected as MCG source. VDIV0=00000 (Multiply=24). */
+ while ((MCG->S & MCG_S_LOCK0) == 0)
+ ; /* wait until PLL locked */
+
+ /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
+
+ /* (4) Transition from PBE mode to PEE mode. */
+ /* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
+ // Switch to PEE mode
+ // Select PLL output (CLKS=0)
+ // FLL external reference divider (FRDIV=3)
+ // External reference clock for FLL (IREFS=0)
+ MCG->C1 = MCG_C1_CLKS(0) |
+ MCG_C1_FRDIV(3);
+ /* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
+ ; /* wait until clock switched to PLL output */
+
+ /* --- MCG mode: PEE (PLL enabled, external crystal) --- */
+
+#else /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/**
+ * @brief Platform early initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ *
+ * @special
+ */
+void platform_early_init(void) {
+
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/hal_lld.h b/os/hal/ports/KINETIS/KL2x/hal_lld.h new file mode 100644 index 0000000..f93d920 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/hal_lld.h @@ -0,0 +1,269 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.h
+ * @brief Kinetis KL2x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "kl25z.h"
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
+ * @note The allowed range is 1...16.
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV1 2
+#endif
+
+/**
+ * @brief Additional clock divider bus/flash clocks (OUTDIV4).
+ * @note The allowed range is 1...8.
+ * @note This divider is on top of the OUTDIV1 divider.
+ * @note The default value is calculated for 24 MHz bus/flash clocks
+ * from a 96 MHz PLL output and 48 MHz core/system clock.
+ */
+#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_OUTDIV4 2
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/**
+ * @brief MCU bus/flash clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#endif
+
+/**
+ * @brief UART0 clock frequency.
+ * @note The default value is based on 96 MHz PLL/2 source.
+ * If you use a different source, such as the FLL,
+ * you must set this properly.
+ */
+#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+/**
+ * @brief UART0 clock source.
+ * @note The default value is to use PLL/2 or FLL source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+#error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+#error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+#error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+#error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
+ KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
+#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
+ KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
+#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void kl2x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_registry.h b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h new file mode 100644 index 0000000..dcf3576 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/kinetis_registry.h @@ -0,0 +1,52 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/kinetis_registry.h
+ * @brief KL2x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _KINETIS_REGISTRY_H_
+#define _KINETIS_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name KL2x capabilities
+ * @{
+ */
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector7C
+
+/* I2C attributes.*/
+#define KINETIS_I2C0_IRQ_VECTOR Vector60
+
+/** @} */
+
+#endif /* _KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h b/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h new file mode 100644 index 0000000..99ffc9c --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/kinetis_tpm.h @@ -0,0 +1,120 @@ +/*
+ ChibiOS - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/kinetis_tpm.h
+ * @brief Kinetis TPM registers layout header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _KINETIS_TPM_H_
+#define _KINETIS_TPM_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name TPM_SC register
+ * @{
+ */
+#define TPM_SC_CMOD_DISABLE (0 << 3)
+#define TPM_SC_CMOD_LPTPM_CLK (1 << 3)
+#define TPM_SC_CMOD_LPTPM_EXTCLK (2 << 3)
+#define TPM_SC_CPWMS (1 << 5)
+#define TPM_SC_TOIE (1 << 6)
+#define TPM_SC_TOF (1 << 7)
+#define TPM_SC_DMA (1 << 8)
+/** @} */
+
+/**
+ * @name TPM_MOD register
+ * @{
+ */
+#define TPM_MOD_MASK (0xFFFF)
+/** @} */
+
+/**
+ * @name TPM_CnSC register
+ * @{
+ */
+#define TPM_CnSC_DMA (1 << 0)
+#define TPM_CnSC_ELSA (1 << 2)
+#define TPM_CnSC_ELSB (1 << 3)
+#define TPM_CnSC_MSA (1 << 4)
+#define TPM_CnSC_MSB (1 << 5)
+#define TPM_CnSC_CHIE (1 << 6)
+#define TPM_CnSC_CHF (1 << 7)
+/** @} */
+
+/**
+ * @name TPM_CnV register
+ * @{
+ */
+#define TPM_CnV_VAL_MASK (0xFFFF)
+/** @} */
+
+/**
+ * @name TPM_STATUS register
+ * @{
+ */
+#define TPM_STATUS_CH0F (1 << 0)
+#define TPM_STATUS_CH1F (1 << 1)
+#define TPM_STATUS_CH2F (1 << 2)
+#define TPM_STATUS_CH3F (1 << 3)
+#define TPM_STATUS_CH4F (1 << 4)
+#define TPM_STATUS_CH5F (1 << 5)
+#define TPM_STATUS_TOF (1 << 8)
+/** @} */
+
+/**
+ * @name TPM_CONF register
+ * @{
+ */
+#define TPM_CONF_DOZEEN (1 << 5)
+#define TPM_CONF_DBGMODE_CONT (3 << 6)
+#define TPM_CONF_DBGMODE_PAUSE (0 << 6)
+#define TPM_CONF_GTBEEN (1 << 9)
+#define TPM_CONF_CSOT (1 << 16)
+#define TPM_CONF_CSOO (1 << 17)
+#define TPM_CONF_CROT (1 << 18)
+#define TPM_CONF_TRGSEL(n) ((n) << 24)
+/** @{ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+#endif /* _KINETIS_TPM_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/kl25z.h b/os/hal/ports/KINETIS/KL2x/kl25z.h new file mode 100644 index 0000000..4e9547f --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/kl25z.h @@ -0,0 +1,1190 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _KL25Z_H_ +#define _KL25Z_H_ + +/* + * ============================================================== + * ---------- Interrupt Number Definition ----------------------- + * ============================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ****************/ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + +/****** KL2x Specific Interrupt Numbers ***********************/ + DMA0_IRQn = 0, + DMA1_IRQn = 1, + DMA2_IRQn = 2, + DMA3_IRQn = 3, + Reserved0_IRQn = 4, + FTFA_IRQn = 5, + PMC_IRQn = 6, + LLWU_IRQn = 7, + I2C0_IRQn = 8, + I2C1_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + UART2_IRQn = 14, + ADC0_IRQn = 15, + CMP0_IRQn = 16, + TPM0_IRQn = 17, + TPM1_IRQn = 18, + TPM2_IRQn = 19, + RTC0_IRQn = 20, + RTC1_IRQn = 21, + PIT_IRQn = 22, + Reserved1_IRQn = 23, + USB_OTG_IRQn = 24, + DAC0_IRQn = 25, + TSI0_IRQn = 26, + MCG_IRQn = 27, + LPTMR0_IRQn = 28, + Reserved2_IRQn = 29, + PINA_IRQn = 30, + PIND_IRQn = 31, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/** + * @brief KL2x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __MPU_PRESENT 0 +#define __VTOR_PRESENT 1 +#define __NVIC_PRIO_BITS 2 +#define __Vendor_SysTickConfig 0 + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ + +typedef struct +{ + __IO uint32_t SOPT1; + __IO uint32_t SOPT1CFG; + uint32_t RESERVED0[1023]; + __IO uint32_t SOPT2; + __I uint32_t RESERVED1[1]; + __IO uint32_t SOPT4; + __IO uint32_t SOPT5; + uint32_t RESERVED2[1]; + __IO uint32_t SOPT7; + uint32_t RESERVED3[2]; + __IO uint32_t SDID; + uint32_t RESERVED4[3]; + __IO uint32_t SCGC4; + __IO uint32_t SCGC5; + __IO uint32_t SCGC6; + __IO uint32_t SCGC7; + __IO uint32_t CLKDIV1; + uint32_t RESERVED5[1]; + __IO uint32_t FCFG1; + __IO uint32_t FCFG2; + uint32_t RESERVED6[1]; + __IO uint32_t UIDMH; + __IO uint32_t UIDML; + __IO uint32_t UIDL; + uint32_t RESERVED7[39]; + __IO uint32_t COPC; + __IO uint32_t SRVCOP; +} SIM_TypeDef; + +typedef struct +{ + __IO uint8_t PE1; + __IO uint8_t PE2; + __IO uint8_t PE3; + __IO uint8_t PE4; + __IO uint8_t ME; + __IO uint8_t F1; + __IO uint8_t F2; + __I uint8_t F3; + __IO uint8_t FILT1; + __IO uint8_t FILT2; +} LLWU_TypeDef; + +typedef struct +{ + __IO uint32_t PCR[32]; + __IO uint32_t GPCLR; + __IO uint32_t GPCHR; + uint32_t RESERVED0[6]; + __IO uint32_t ISFR; +} PORT_TypeDef; + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t C3; + __IO uint8_t C4; + __IO uint8_t C5; + __IO uint8_t C6; + __IO uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t SC; + uint8_t RESERVED1[1]; + __IO uint8_t ATCVH; + __IO uint8_t ATCVL; + __IO uint8_t C7; + __IO uint8_t C8; + __IO uint8_t C9; + __IO uint8_t C10; +} MCG_TypeDef; + +typedef struct +{ + __IO uint8_t CR; +} OSC_TypeDef; + +typedef struct +{ + __IO uint32_t SAR; + __IO uint32_t DAR; + __IO uint32_t DSR_BCR; + __IO uint32_t DCR; +} DMAChannel_TypeDef; + +typedef struct +{ + DMAChannel_TypeDef ch[4]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint8_t CHCFG[4]; +} DMAMUX_TypeDef; + +typedef struct +{ + __IO uint32_t SC; + __IO uint32_t CNT; + __IO uint32_t MOD; + struct { // Channels + __IO uint32_t SC; + __IO uint32_t V; + } C[6]; + uint32_t RESERVED0[5]; + __IO uint32_t STATUS; + uint32_t RESERVED1[12]; + __IO uint32_t CONF; +} TPM_TypeDef; + +typedef struct +{ + __IO uint32_t SC1A; // ADC Status and Control Registers 1 + __IO uint32_t SC1B; // ADC Status and Control Registers 1 + __IO uint32_t CFG1; // ADC Configuration Register 1 + __IO uint32_t CFG2; // ADC Configuration Register 2 + __I uint32_t RA; // ADC Data Result Register + __I uint32_t RB; // ADC Data Result Register + __IO uint32_t CV1; // Compare Value Registers + __IO uint32_t CV2; // Compare Value Registers + __IO uint32_t SC2; // Status and Control Register 2 + __IO uint32_t SC3; // Status and Control Register 3 + __IO uint32_t OFS; // ADC Offset Correction Register + __IO uint32_t PG; // ADC Plus-Side Gain Register + __IO uint32_t MG; // ADC Minus-Side Gain Register + __IO uint32_t CLPD; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLPS; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP4; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP3; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP2; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP1; // ADC Plus-Side General Calibration Value Register + __IO uint32_t CLP0; // ADC Plus-Side General Calibration Value Register + uint32_t RESERVED0[1]; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMD; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLMS; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM4; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM3; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM2; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM1; // ADC Minus-Side General Calibration Value Register + __IO uint32_t CLM0; // ADC Minus-Side General Calibration Value Register +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t PSR; + __IO uint32_t CMR; + __I uint32_t CNR; +} LPTMR_TypeDef; + +typedef struct +{ + __IO uint32_t GENCS; + __IO uint32_t DATA; + __IO uint32_t TSHD; +} TSI_TypeDef; + +typedef struct +{ + __IO uint32_t PDOR; + __IO uint32_t PSOR; + __IO uint32_t PCOR; + __IO uint32_t PTOR; + __IO uint32_t PDIR; + __IO uint32_t PDDR; +} GPIO_TypeDef; + +typedef struct +{ + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t BR; + __IO uint8_t S; + uint8_t RESERVED0[1]; + __IO uint8_t D; + uint8_t RESERVED1[1]; + __IO uint8_t M; +} SPI_TypeDef; + +typedef struct +{ + __IO uint8_t A1; + __IO uint8_t F; + __IO uint8_t C1; + __IO uint8_t S; + __IO uint8_t D; + __IO uint8_t C2; + __IO uint8_t FLT; + __IO uint8_t RA; + __IO uint8_t SMB; + __IO uint8_t A2; + __IO uint8_t SLTH; + __IO uint8_t SLTL; +} I2C_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t C4; +} UART_TypeDef; + +typedef struct +{ + __IO uint8_t BDH; + __IO uint8_t BDL; + __IO uint8_t C1; + __IO uint8_t C2; + __IO uint8_t S1; + __IO uint8_t S2; + __IO uint8_t C3; + __IO uint8_t D; + __IO uint8_t MA1; + __IO uint8_t MA2; + __IO uint8_t C4; + __IO uint8_t C5; +} UARTLP_TypeDef; + +typedef struct +{ + __IO uint8_t LVDSC1; + __IO uint8_t LVDSC2; + __IO uint8_t REGSC; +} PMC_TypeDef; + +/****************************************************************/ +/* Peripheral memory map */ +/****************************************************************/ +#define DMA_BASE ((uint32_t)0x40008100) +#define DMAMUX_BASE ((uint32_t)0x40021000) +#define TPM0_BASE ((uint32_t)0x40038000) +#define TPM1_BASE ((uint32_t)0x40039000) +#define TPM2_BASE ((uint32_t)0x4003A000) +#define ADC0_BASE ((uint32_t)0x4003B000) +#define LPTMR0_BASE ((uint32_t)0x40040000) +#define TSI0_BASE ((uint32_t)0x40045000) +#define SIM_BASE ((uint32_t)0x40047000) +#define PORTA_BASE ((uint32_t)0x40049000) +#define PORTB_BASE ((uint32_t)0x4004A000) +#define PORTC_BASE ((uint32_t)0x4004B000) +#define PORTD_BASE ((uint32_t)0x4004C000) +#define PORTE_BASE ((uint32_t)0x4004D000) +#define MCG_BASE ((uint32_t)0x40064000) +#define OSC0_BASE ((uint32_t)0x40065000) +#define I2C0_BASE ((uint32_t)0x40066000) +#define I2C1_BASE ((uint32_t)0x40067000) +#define UART0_BASE ((uint32_t)0x4006A000) +#define UART1_BASE ((uint32_t)0x4006B000) +#define UART2_BASE ((uint32_t)0x4006C000) +#define SPI0_BASE ((uint32_t)0x40076000) +#define SPI1_BASE ((uint32_t)0x40077000) +#define LLWU_BASE ((uint32_t)0x4007C000) +#define PMC_BASE ((uint32_t)0x4007D000) +#define GPIOA_BASE ((uint32_t)0x400FF000) +#define GPIOB_BASE ((uint32_t)0x400FF040) +#define GPIOC_BASE ((uint32_t)0x400FF080) +#define GPIOD_BASE ((uint32_t)0x400FF0C0) +#define GPIOE_BASE ((uint32_t)0x400FF100) + +/****************************************************************/ +/* Peripheral declaration */ +/****************************************************************/ +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE) +#define TPM0 ((TPM_TypeDef *) TPM0_BASE) +#define TPM1 ((TPM_TypeDef *) TPM1_BASE) +#define TPM2 ((TPM_TypeDef *) TPM2_BASE) +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE) +#define TSI0 ((TSI_TypeDef *) TSI0_BASE) +#define SIM ((SIM_TypeDef *) SIM_BASE) +#define LLWU ((LLWU_TypeDef *) LLWU_BASE) +#define PMC ((PMC_TypeDef *) PMC_BASE) +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) +#define PORTD ((PORT_TypeDef *) PORTD_BASE) +#define PORTE ((PORT_TypeDef *) PORTE_BASE) +#define MCG ((MCG_TypeDef *) MCG_BASE) +#define OSC0 ((OSC_TypeDef *) OSC0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define UART0 ((UARTLP_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) + +/****************************************************************/ +/* Peripheral Registers Bits Definition */ +/****************************************************************/ + +/****************************************************************/ +/* */ +/* System Integration Module (SIM) */ +/* */ +/****************************************************************/ +/********* Bits definition for SIM_SOPT1 register *************/ +#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */ +#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */ +#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */ +#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */ +#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */ +#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */ + +/******* Bits definition for SIM_SOPT1CFG register ************/ +#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */ +#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */ +#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */ + +/******* Bits definition for SIM_SOPT2 register ************/ +#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */ +#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */ +#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */ +#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */ +#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */ +#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */ +#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */ +#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */ +#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */ +#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */ +#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */ +#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */ + +/******* Bits definition for SIM_SCGC4 register ************/ +#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */ +#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */ +#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */ +#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */ +#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */ +#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */ +#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */ +#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */ +#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */ + +/******* Bits definition for SIM_SCGC5 register ************/ +#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */ +#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */ +#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */ +#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */ +#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */ +#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */ +#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */ +#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */ +#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */ +#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */ +#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */ +#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */ +#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */ +#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */ +#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */ + +/******* Bits definition for SIM_SCGC6 register ************/ +#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */ + +/****** Bits definition for SIM_CLKDIV1 register ***********/ +#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */ +#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */ +#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */ +#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */ + +/****************************************************************/ +/* */ +/* Low-Leakage Wakeup Unit (LLWU) */ +/* */ +/****************************************************************/ +/********** Bits definition for LLWU_PE1 register *************/ +#define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ +#define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ +#define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ +#define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ +#define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ +#define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ +#define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ +#define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ +#define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ +#define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ +#define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ +#define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ + +/********** Bits definition for LLWU_PE2 register *************/ +#define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ +#define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ +#define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ +#define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ +#define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ +#define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ +#define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ +#define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ +#define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ +#define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ +#define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ +#define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ + +/********** Bits definition for LLWU_PE3 register *************/ +#define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ +#define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ +#define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ +#define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ +#define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ +#define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ +#define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ +#define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ +#define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ +#define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ +#define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ +#define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ + +/********** Bits definition for LLWU_PE4 register *************/ +#define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ +#define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ +#define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ +#define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ +#define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ +#define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ +#define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ +#define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ +#define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ +#define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ +#define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ +#define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ + +/********** Bits definition for LLWU_ME register *************/ +#define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ +#define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ +#define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ +#define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ +#define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ +#define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ +#define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ +#define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ + +/********** Bits definition for LLWU_F1 register *************/ +#define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ +#define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ +#define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ +#define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ +#define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ +#define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ +#define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ +#define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ + +/********** Bits definition for LLWU_F2 register *************/ +#define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ +#define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ +#define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ +#define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ +#define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ +#define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ +#define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ +#define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ + +/********** Bits definition for LLWU_F3 register *************/ +#define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ +#define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ +#define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ +#define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ +#define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ +#define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ +#define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ +#define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ + +/********** Bits definition for LLWU_FILT1 register *************/ +#define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/********** Bits definition for LLWU_FILT2 register *************/ +#define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ +#define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ +#define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ +#define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ +#define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ +#define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ +#define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ +#define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ +#define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ +#define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ +#define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ + +/****************************************************************/ +/* */ +/* Port Control and interrupts (PORT) */ +/* */ +/****************************************************************/ +/******** Bits definition for PORTx_PCRn register *************/ +#define PORTx_PCRn_ISR ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ +#define PORTx_PCRn_IRQC_SHIFT 16 +#define PORTx_PCRn_IRQC_MASK ((uint32_t)0x000F0000) /*!< Interrupt Configuration */ +#define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) +#define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ +#define PORTx_PCRn_MUX_MASK ((uint32_t)0x00000700) /*!< Pin Mux Control (mask) */ +#define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ +#define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ +#define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ +#define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ +#define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ +#define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ + +/****************************************************************/ +/* */ +/* Oscillator (OSC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for OSC_CR register **************/ +#define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ +#define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ +#define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ +#define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ +#define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ +#define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ + +/****************************************************************/ +/* */ +/* Direct Memory Access (DMA) */ +/* */ +/****************************************************************/ +/*********** Bits definition for DMA_BCRn register ************/ +#define DMA_DSR_BCRn_CE ((uint32_t)((uint32_t)1 << 30)) /*!< Configuration Error */ +#define DMA_DSR_BCRn_BES ((uint32_t)((uint32_t)1 << 29)) /*!< Bus Error on Source */ +#define DMA_DSR_BCRn_BED ((uint32_t)((uint32_t)1 << 28)) /*!< Bus Error on Destination */ +#define DMA_DSR_BCRn_REQ ((uint32_t)((uint32_t)1 << 26)) /*!< Request */ +#define DMA_DSR_BCRn_BSY ((uint32_t)((uint32_t)1 << 25)) /*!< Busy */ +#define DMA_DSR_BCRn_DONE ((uint32_t)((uint32_t)1 << 24)) /*!< Transactions done */ +#define DMA_DSR_BCRn_BCR_SHIFT 0 /*!< Bytes yet to be transferred for block (shift) */ +#define DMA_DSR_BCRn_BCR_MASK ((uint32_t)((uint32_t)0x00FFFFFF << DMA_DSR_BCRn_BCR_SHIFT)) /*!< Bytes yet to be transferred for block (mask) */ +#define DMA_DSR_BCRn_BCR(x) ((uint32_t)(((uint32_t)(x) << DMA_DSR_BCRn_BCR_SHIFT) & DMA_DSR_BCRn_BCR_MASK)) /*!< Bytes yet to be transferred for block */ + +/*********** Bits definition for DMA_DCRn register ************/ +#define DMA_DCRn_EINT ((uint32_t)((uint32_t)1 << 31)) /*!< Enable interrupt on completion of transfer */ +#define DMA_DCRn_ERQ ((uint32_t)((uint32_t)1 << 30)) /*!< Enable peripheral request */ +#define DMA_DCRn_CS ((uint32_t)((uint32_t)1 << 29)) /*!< Cycle steal */ +#define DMA_DCRn_AA ((uint32_t)((uint32_t)1 << 28)) /*!< Auto-align */ +#define DMA_DCRn_EADREQ ((uint32_t)((uint32_t)1 << 23)) /*!< Enable asynchronous DMA requests */ +#define DMA_DCRn_SINC ((uint32_t)((uint32_t)1 << 22)) /*!< Source increment */ +#define DMA_DCRn_SSIZE_SHIFT 20 /*!< Source size (shift) */ +#define DMA_DCRn_SSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_SSIZE_SHIFT)) /*!< Source size (mask) */ +#define DMA_DCRn_SSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SSIZE_SHIFT) & DMA_DCRn_SSIZE_MASK)) /*!< Source size */ +#define DMA_DCRn_DINC ((uint32_t)((uint32_t)1 << 19)) /*!< Destination increment */ +#define DMA_DCRn_DSIZE_SHIFT 17 /*!< Destination size (shift) */ +#define DMA_DCRn_DSIZE_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_DSIZE_SHIFT)) /*!< Destination size (mask) */ +#define DMA_DCRn_DSIZE(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DSIZE_SHIFT) & DMA_DCRn_DSIZE_MASK)) /*!< Destination size */ +#define DMA_DCRn_START ((uint32_t)((uint32_t)1 << 16)) /*!< Start transfer */ +#define DMA_DCRn_SMOD_SHIFT 12 /*!< Source address modulo (shift) */ +#define DMA_DCRn_SMOD_MASK ((uint32_t)((uint32_t)0x0F << DMA_DCRn_SMOD_SHIFT)) /*!< Source address modulo (mask) */ +#define DMA_DCRn_SMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_SMOD_SHIFT) & DMA_DCRn_SMOD_MASK)) /*!< Source address modulo */ +#define DMA_DCRn_DMOD_SHIFT 8 /*!< Destination address modulo (shift) */ +#define DMA_DCRn_DMOD_MASK ((uint32_t)0x0F << DMA_DCRn_DMOD_SHIFT) /*!< Destination address modulo (mask) */ +#define DMA_DCRn_DMOD(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_DMOD_SHIFT) & DMA_DCRn_DMOD_MASK)) /*!< Destination address modulo */ +#define DMA_DCRn_D_REQ ((uint32_t)((uint32_t)1 << 7)) /*!< Disable request */ +#define DMA_DCRn_LINKCC_SHIFT 4 /*!< Link channel control (shift) */ +#define DMA_DCRn_LINKCC_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LINKCC_SHIFT)) /*!< Link channel control (mask) */ +#define DMA_DCRn_LINKCC(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LINKCC_SHIFT) & DMA_DCRn_LINKCC_MASK)) /*!< Link channel control */ +#define DMA_DCRn_LCH1_SHIFT 2 /*!< Link channel 1 (shift) */ +#define DMA_DCRn_LCH1_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH1_SHIFT)) /*!< Link channel 1 (mask) */ +#define DMA_DCRn_LCH1(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH1_SHIFT) & DMA_DCRn_LCH1_MASK)) /*!< Link channel 1 */ +#define DMA_DCRn_LCH2_SHIFT 0 /*!< Link channel 2 (shift) */ +#define DMA_DCRn_LCH2_MASK ((uint32_t)((uint32_t)0x03 << DMA_DCRn_LCH2_SHIFT)) /*!< Link channel 2 (mask) */ +#define DMA_DCRn_LCH2(x) ((uint32_t)(((uint32_t)(x) << DMA_DCRn_LCH2_SHIFT) & DMA_DCRn_LCH2_MASK)) /*!< Link channel 2 */ + +/****************************************************************/ +/* */ +/* Direct Memory Access Multiplexer (DMAMUX) */ +/* */ +/****************************************************************/ +/******** Bits definition for DMAMUX_CHCFGn register **********/ +#define DMAMUX_CHCFGn_ENBL ((uint8_t)((uint8_t)1 << 7)) /*!< DMA Channel Enable */ +#define DMAMUX_CHCFGn_TRIG ((uint8_t)((uint8_t)1 << 6)) /*!< DMA Channel Trigger Enable */ +#define DMAMUX_CHCFGn_SOURCE_SHIFT 0 /*!< DMA Channel Source (Slot) (shift) */ +#define DMAMUX_CHCFGn_SOURCE_MASK ((uint8_t)((uint8_t)0x3F << DMAMUX_CHCFGn_SOURCE_SHIFT)) /*!< DMA Channel Source (Slot) (mask) */ +#define DMAMUX_CHCFGn_SOURCE(x) ((uint8_t)(((uint8_t)(x) << DMAMUX_CHCFGn_SOURCE_SHIFT) & DMAMUX_CHCFGn_SOURCE_MASK)) /*!< DMA Channel Source (Slot) */ + +/****************************************************************/ +/* */ +/* Analog-to-Digital Converter (ADC) */ +/* */ +/****************************************************************/ +/*********** Bits definition for ADCx_SC1n register ***********/ +#define ADCx_SC1n_COCO ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Complete Flag */ +#define ADCx_SC1n_AIEN ((uint32_t)((uint32_t)1 << 6)) /*!< Interrupt Enable */ +#define ADCx_SC1n_DIFF ((uint32_t)((uint32_t)1 << 5)) /*!< Differential Mode Enable */ +#define ADCx_SC1n_ADCH_SHIFT 0 /*!< Input channel select (shift) */ +#define ADCx_SC1n_ADCH_MASK ((uint32_t)((uint32_t)0x1F << ADCx_SC1n_ADCH_SHIFT)) /*!< Input channel select (mask) */ +#define ADCx_SC1n_ADCH(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC1n_ADCH_SHIFT) & ADCx_SC1n_ADCH_MASK)) /*!< Input channel select */ + +/*********** Bits definition for ADCx_CFG1 register ***********/ +#define ADCx_CFG1_ADLPC ((uint32_t)((uint32_t)1 << 7)) /*!< Low-Power Configuration */ +#define ADCx_CFG1_ADIV_SHIFT 5 /*!< Clock Divide Select (shift) */ +#define ADCx_CFG1_ADIV_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADIV_SHIFT)) /*!< Clock Divide Select (mask) */ +#define ADCx_CFG1_ADIV(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADIV_SHIFT) & ADCx_CFG1_ADIV_MASK)) /*!< Clock Divide Select */ +#define ADCx_CFG1_ADLSMP ((uint32_t)((uint32_t)1 << 4)) /*!< Sample time configuration */ +#define ADCx_CFG1_MODE_SHIFT 2 /*!< Conversion mode (resolution) selection (shift) */ +#define ADCx_CFG1_MODE_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_MODE_SHIFT)) /*!< Conversion mode (resolution) selection (mask) */ +#define ADCx_CFG1_MODE(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_MODE_SHIFT) & ADCx_CFG1_MODE_MASK)) /*!< Conversion mode (resolution) selection */ +#define ADCx_CFG1_ADICLK_SHIFT 0 /*!< Input Clock Select (shift) */ +#define ADCx_CFG1_ADICLK_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG1_ADICLK_SHIFT)) /*!< Input Clock Select (mask) */ +#define ADCx_CFG1_ADICLK(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG1_ADICLK_SHIFT) & ADCx_CFG1_ADICLK_MASK)) /*!< Input Clock Select */ + +/*********** Bits definition for ADCx_CFG2 register ***********/ +#define ADCx_CFG2_MUXSEL ((uint32_t)((uint32_t)1 << 4)) /*!< ADC Mux Select */ +#define ADCx_CFG2_ADACKEN ((uint32_t)((uint32_t)1 << 3)) /*!< Asynchronous Clock Output Enable */ +#define ADCx_CFG2_ADHSC ((uint32_t)((uint32_t)1 << 2)) /*!< High-Speed Configuration */ +#define ADCx_CFG2_ADLSTS_SHIFT 0 /*!< Long Sample Time Select (shift) */ +#define ADCx_CFG2_ADLSTS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_CFG2_ADLSTS_SHIFT)) /*!< Long Sample Time Select (mask) */ +#define ADCx_CFG2_ADLSTS(x) ((uint32_t)(((uint32_t)(x) << ADCx_CFG2_ADLSTS_SHIFT) & ADCx_CFG2_ADLSTS_MASK)) /*!< Long Sample Time Select */ + +/*********** Bits definition for ADCx_SC2 register ***********/ +#define ADCx_SC2_ADACT ((uint32_t)((uint32_t)1 << 7)) /*!< Conversion Active */ +#define ADCx_SC2_ADTRG ((uint32_t)((uint32_t)1 << 6)) /*!< Conversion Trigger Select */ +#define ADCx_SC2_ACFE ((uint32_t)((uint32_t)1 << 5)) /*!< Compare Function Enable */ +#define ADCx_SC2_ACFGT ((uint32_t)((uint32_t)1 << 4)) /*!< Compare Function Greater Than Enable */ +#define ADCx_SC2_ACREN ((uint32_t)((uint32_t)1 << 3)) /*!< Compare Function Range Enable */ +#define ADCx_SC2_DMAEN ((uint32_t)((uint32_t)1 << 2)) /*!< DMA Enable */ +#define ADCx_SC2_REFSEL_SHIFT 0 /*!< Voltage Reference Selection (shift) */ +#define ADCx_SC2_REFSEL_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC2_REFSEL_SHIFT)) /*!< Voltage Reference Selection (mask) */ +#define ADCx_SC2_REFSEL(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC2_REFSEL_SHIFT) & ADCx_SC2_REFSEL_MASK)) /*!< Voltage Reference Selection */ + +/*********** Bits definition for ADCx_SC3 register ***********/ +#define ADCx_SC3_CAL ((uint32_t)((uint32_t)1 << 7)) /*!< Calibration */ +#define ADCx_SC3_CALF ((uint32_t)((uint32_t)1 << 6)) /*!< Calibration Failed Flag */ +#define ADCx_SC3_ADCO ((uint32_t)((uint32_t)1 << 3)) /*!< Continuous Conversion Enable */ +#define ADCx_SC3_AVGE ((uint32_t)((uint32_t)1 << 2)) /*!< Hardware Average Enable */ +#define ADCx_SC3_AVGS_SHIFT 0 /*!< Hardware Average Select (shift) */ +#define ADCx_SC3_AVGS_MASK ((uint32_t)((uint32_t)0x03 << ADCx_SC3_AVGS_SHIFT)) /*!< Hardware Average Select (mask) */ +#define ADCx_SC3_AVGS(x) ((uint32_t)(((uint32_t)(x) << ADCx_SC3_AVGS_SHIFT) & ADCx_SC3_AVGS_MASK)) /*!< Hardware Average Select */ + +/****************************************************************/ +/* */ +/* Low-Power Timer (LPTMR) */ +/* */ +/****************************************************************/ +/********** Bits definition for LPTMRx_CSR register ***********/ +#define LPTMRx_CSR_TCF ((uint32_t)((uint32_t)1 << 7)) /*!< Timer Compare Flag */ +#define LPTMRx_CSR_TIE ((uint32_t)((uint32_t)1 << 6)) /*!< Timer Interrupt Enable */ +#define LPTMRx_CSR_TPS_SHIFT 4 /*!< Timer Pin Select (shift) */ +#define LPTMRx_CSR_TPS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_CSR_TPS_SHIFT)) /*!< Timer Pin Select (mask) */ +#define LPTMRx_CSR_TPS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CSR_TPS_SHIFT) & LPTMRx_CSR_TPS_MASK)) /*!< Timer Pin Select */ +#define LPTMRx_CSR_TPP ((uint32_t)((uint32_t)1 << 3)) /*!< Timer Pin Polarity */ +#define LPTMRx_CSR_TFC ((uint32_t)((uint32_t)1 << 2)) /*!< Timer Free-Running Counter */ +#define LPTMRx_CSR_TMS ((uint32_t)((uint32_t)1 << 1)) /*!< Timer Mode Select */ +#define LPTMRx_CSR_TEN ((uint32_t)((uint32_t)1 << 0)) /*!< Timer Enable */ + +/********** Bits definition for LPTMRx_PSR register ***********/ +#define LPTMRx_PSR_PRESCALE_SHIFT 3 /*!< Prescale Value (shift) */ +#define LPTMRx_PSR_PRESCALE_MASK ((uint32_t)((uint32_t)0x0F << LPTMRx_PSR_PRESCALE_SHIFT)) /*!< Prescale Value (mask) */ +#define LPTMRx_PSR_PRESCALE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PRESCALE_SHIFT) & LPTMRx_PSR_PRESCALE_MASK)) /*!< Prescale Value */ +#define LPTMRx_PSR_PBYP ((uint32_t)((uint32_t)1 << 2)) /*!< Prescaler Bypass */ +#define LPTMRx_PSR_PCS_SHIFT 0 /*!< Prescaler Clock Select (shift) */ +#define LPTMRx_PSR_PCS_MASK ((uint32_t)((uint32_t)0x03 << LPTMRx_PSR_PCS_SHIFT)) /*!< Prescaler Clock Select (mask) */ +#define LPTMRx_PSR_PCS(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_PSR_PCS_SHIFT) & LPTMRx_PSR_PCS_MASK)) /*!< Prescaler Clock Select */ + +/********** Bits definition for LPTMRx_CMR register ***********/ +#define LPTMRx_CMR_COMPARE_SHIFT 0 /*!< Compare Value (shift) */ +#define LPTMRx_CMR_COMPARE_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CMR_COMPARE_SHIFT)) /*!< Compare Value (mask) */ +#define LPTMRx_CMR_COMPARE(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CMR_COMPARE_SHIFT) & LPTMRx_CMR_COMPARE_MASK)) /*!< Compare Value */ + +/********** Bits definition for LPTMRx_CNR register ***********/ +#define LPTMRx_CNR_COUNTER_SHIFT 0 /*!< Counter Value (shift) */ +#define LPTMRx_CNR_COUNTER_MASK ((uint32_t)((uint32_t)0xFFFF << LPTMRx_CNR_COUNTER_SHIFT)) /*!< Counter Value (mask) */ +#define LPTMRx_CNR_COUNTER(x) ((uint32_t)(((uint32_t)(x) << LPTMRx_CNR_COUNTER_SHIFT) & LPTMRx_CNR_COUNTER_MASK)) /*!< Counter Value */ + +/****************************************************************/ +/* */ +/* Touch Sensing Input (TSI) */ +/* */ +/****************************************************************/ +/********** Bits definition for TSIx_GENCS register ***********/ +#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */ +#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */ +#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */ +#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */ +#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */ +#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */ +#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */ +#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */ +#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */ +#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */ +#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */ +#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */ +#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */ +#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */ +#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */ +#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */ +#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */ +#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */ +#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */ +#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */ +#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */ +#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */ +#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */ +#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */ +#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */ + +/********** Bits definition for TSIx_DATA register ************/ +#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */ +#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */ +#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */ +#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */ +#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */ +#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */ +#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */ +#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */ + +/********** Bits definition for TSIx_TSHD register ************/ +#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */ +#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */ +#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */ +#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */ +#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */ +#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */ + +/****************************************************************/ +/* */ +/* Multipurpose Clock Generator (MCG) */ +/* */ +/****************************************************************/ +/*********** Bits definition for MCG_C1 register **************/ +#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */ +#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */ +#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */ +#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */ +#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */ +#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */ +#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */ +#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */ +#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */ +#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */ +#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */ +#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */ + +/*********** Bits definition for MCG_C2 register **************/ +#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */ +#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */ +#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */ +#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */ +#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */ +#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */ +#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */ +#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */ + +/*********** Bits definition for MCG_C3 register **************/ +#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */ +#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */ +#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */ + +/*********** Bits definition for MCG_C4 register **************/ +#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */ +#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */ +#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */ +#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */ +#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */ +#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */ + +/*********** Bits definition for MCG_C5 register **************/ +#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */ +#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */ +#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */ +#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */ +#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */ + +/*********** Bits definition for MCG_C6 register **************/ +#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */ +#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */ +#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */ +#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */ +#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */ +#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */ + +/************ Bits definition for MCG_S register **************/ +#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */ +#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */ +#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */ +#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */ +#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */ +#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */ +#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */ +#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */ +#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */ +#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */ +#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */ +#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */ +#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */ + +/************ Bits definition for MCG_SC register **************/ +#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */ +#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */ +#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */ +#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */ +#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */ +#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */ +#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */ +#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */ +#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */ +#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */ +#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */ +#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */ +#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */ +#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */ +#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */ +#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */ + +/*********** Bits definition for MCG_ATCVH register ************/ +#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */ +#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */ +#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */ + +/*********** Bits definition for MCG_ATCVL register ************/ +#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */ +#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */ +#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */ + +/************ Bits definition for MCG_C7 register **************/ +/* All MCG_C7 bits are reserved on the KL25Z. */ + +/************ Bits definition for MCG_C8 register **************/ +#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */ + +/************ Bits definition for MCG_C9 register **************/ +/* All MCG_C9 bits are reserved on the KL25Z. */ + +/************ Bits definition for MCG_C10 register *************/ +/* All MCG_C10 bits are reserved on the KL25Z. */ + + +/****************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/****************************************************************/ +/*********** Bits definition for SPIx_C1 register *************/ +#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */ +#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */ +#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */ +#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */ +#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */ +#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */ +#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */ +#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */ + +/*********** Bits definition for SPIx_C2 register *************/ +#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */ +#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */ +#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */ +#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */ +#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */ +#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */ +#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */ + +/*********** Bits definition for SPIx_BR register *************/ +#define SPIx_BR_SPPR ((uint8_t)0x70) /*!< SPI Baud rate Prescaler Divisor */ +#define SPIx_BR_SPR ((uint8_t)0x0F) /*!< SPI Baud rate Divisor */ + +#define SPIx_BR_SPPR_SHIFT 4 + +/*********** Bits definition for SPIx_S register **************/ +#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */ +#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */ +#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */ +#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */ + +/*********** Bits definition for SPIx_D register **************/ +#define SPIx_D_DATA ((uint8_t)0xFF) /*!< Data */ + +/*********** Bits definition for SPIx_M register **************/ +#define SPIx_M_DATA ((uint8_t)0xFF) /*!< SPI HW Compare value for Match */ + +/****************************************************************/ +/* */ +/* Inter-Integrated Circuit (I2C) */ +/* */ +/****************************************************************/ +/*********** Bits definition for I2Cx_A1 register *************/ +#define I2Cx_A1_AD ((uint8_t)0xFE) /*!< Address [7:1] */ + +#define I2Cx_A1_AD_SHIT 1 + +/*********** Bits definition for I2Cx_F register **************/ +#define I2Cx_F_MULT ((uint8_t)0xC0) /*!< Multiplier factor */ +#define I2Cx_F_ICR ((uint8_t)0x3F) /*!< Clock rate */ + +#define I2Cx_F_MULT_SHIFT 5 + +/*********** Bits definition for I2Cx_C1 register *************/ +#define I2Cx_C1_IICEN ((uint8_t)0x80) /*!< I2C Enable */ +#define I2Cx_C1_IICIE ((uint8_t)0x40) /*!< I2C Interrupt Enable */ +#define I2Cx_C1_MST ((uint8_t)0x20) /*!< Master Mode Select */ +#define I2Cx_C1_TX ((uint8_t)0x10) /*!< Transmit Mode Select */ +#define I2Cx_C1_TXAK ((uint8_t)0x08) /*!< Transmit Acknowledge Enable */ +#define I2Cx_C1_RSTA ((uint8_t)0x04) /*!< Repeat START */ +#define I2Cx_C1_WUEN ((uint8_t)0x02) /*!< Wakeup Enable */ +#define I2Cx_C1_DMAEN ((uint8_t)0x01) /*!< DMA Enable */ + +/*********** Bits definition for I2Cx_S register **************/ +#define I2Cx_S_TCF ((uint8_t)0x80) /*!< Transfer Complete Flag */ +#define I2Cx_S_IAAS ((uint8_t)0x40) /*!< Addressed As A Slave */ +#define I2Cx_S_BUSY ((uint8_t)0x20) /*!< Bus Busy */ +#define I2Cx_S_ARBL ((uint8_t)0x10) /*!< Arbitration Lost */ +#define I2Cx_S_RAM ((uint8_t)0x08) /*!< Range Address Match */ +#define I2Cx_S_SRW ((uint8_t)0x04) /*!< Slave Read/Write */ +#define I2Cx_S_IICIF ((uint8_t)0x02) /*!< Interrupt Flag */ +#define I2Cx_S_RXAK ((uint8_t)0x01) /*!< Receive Acknowledge */ + +/*********** Bits definition for I2Cx_D register **************/ +#define I2Cx_D_DATA ((uint8_t)0xFF) /*!< Data */ + +/*********** Bits definition for I2Cx_C2 register *************/ +#define I2Cx_C2_GCAEN ((uint8_t)0x80) /*!< General Call Address Enable */ +#define I2Cx_C2_ADEXT ((uint8_t)0x40) /*!< Address Extension */ +#define I2Cx_C2_HDRS ((uint8_t)0x20) /*!< High Drive Select */ +#define I2Cx_C2_SBRC ((uint8_t)0x10) /*!< Slave Baud Rate Control */ +#define I2Cx_C2_RMEN ((uint8_t)0x08) /*!< Range Address Matching Enable */ +#define I2Cx_C2_AD_10_8 ((uint8_t)0x03) /*!< Slave Address [10:8] */ + +/*********** Bits definition for I2Cx_FLT register ************/ +#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */ +#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */ +#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */ +#define I2Cx_FLT_FLT ((uint8_t)0x1F) /*!< I2C Programmable Filter Factor */ + +/*********** Bits definition for I2Cx_RA register *************/ +#define I2Cx_RA_RAD ((uint8_t)0xFE) /*!< Range Slave Address */ + +#define I2Cx_RA_RAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SMB register ************/ +#define I2Cx_SMB_FACK ((uint8_t)0x80) /*!< Fast NACK/ACK Enable */ +#define I2Cx_SMB_ALERTEN ((uint8_t)0x40) /*!< SMBus Alert Response Address Enable */ +#define I2Cx_SMB_SIICAEN ((uint8_t)0x20) /*!< Second I2C Address Enable */ +#define I2Cx_SMB_TCKSEL ((uint8_t)0x10) /*!< Timeout Counter Clock Select */ +#define I2Cx_SMB_SLTF ((uint8_t)0x08) /*!< SCL Low Timeout Flag */ +#define I2Cx_SMB_SHTF1 ((uint8_t)0x04) /*!< SCL High Timeout Flag 1 */ +#define I2Cx_SMB_SHTF2 ((uint8_t)0x02) /*!< SCL High Timeout Flag 2 */ +#define I2Cx_SMB_SHTF2IE ((uint8_t)0x01) /*!< SHTF2 Interrupt Enable */ + +/*********** Bits definition for I2Cx_A2 register *************/ +#define I2Cx_A2_SAD ((uint8_t)0xFE) /*!< SMBus Address */ + +#define I2Cx_A2_SAD_SHIFT 1 + +/*********** Bits definition for I2Cx_SLTH register ***********/ +#define I2Cx_SLTH_SSLT ((uint8_t)0xFF) /*!< MSB of SCL low timeout value */ + +/*********** Bits definition for I2Cx_SLTL register ***********/ +#define I2Cx_SLTL_SSLT ((uint8_t)0xFF) /*!< LSB of SCL low timeout value */ + +/****************************************************************/ +/* */ +/* Universal Asynchronous Receiver/Transmitter (UART) */ +/* */ +/****************************************************************/ +/********* Bits definition for UARTx_BDH register *************/ +#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */ +#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */ +#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */ +#define UARTx_BDH_SBR ((uint8_t)0x1F) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for UARTx_BDL register *************/ +#define UARTx_BDL_SBR ((uint8_t)0xFF) /*!< Baud Rate Modulo Divisor */ + +/********* Bits definition for UARTx_C1 register **************/ +#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */ +#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */ +#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */ +#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */ +#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */ +#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */ +#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */ +#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */ +#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */ + +/********* Bits definition for UARTx_C2 register **************/ +#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */ +#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */ +#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */ +#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */ +#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */ +#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */ +#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */ +#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */ + +/********* Bits definition for UARTx_S1 register **************/ +#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */ +#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */ +#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */ +#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */ +#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */ +#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */ +#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */ +#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */ + +/********* Bits definition for UARTx_S2 register **************/ +#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */ +#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */ +#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */ +#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */ +#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */ +#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */ +#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */ +#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */ + +/********* Bits definition for UARTx_C3 register **************/ +#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */ +#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */ +#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */ +#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */ +#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */ +#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */ +#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */ +#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */ +#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */ +#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */ + +/********* Bits definition for UARTx_D register ***************/ +#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */ +#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */ +#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */ +#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */ +#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */ +#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */ +#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */ +#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */ + +/********* Bits definition for UARTx_MA1 register *************/ +#define UARTx_MA1_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_MA2 register *************/ +#define UARTx_MA2_MA ((uint8_t)0xFF) /*!< Match Address */ + +/********* Bits definition for UARTx_C4 register **************/ +#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */ +#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */ +#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */ +#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */ +#define UARTx_C4_RDMAS ((uint8_t)0x80) /*!< Receiver Full DMA Select */ +#define UARTx_C4_OSR ((uint8_t)0x1F) /*!< Over Sampling Ratio */ + +/********* Bits definition for UARTx_C5 register **************/ +#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */ +#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */ +#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */ +#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */ +/****************************************************************/ +/* */ +/* Power Management Controller (PMC) */ +/* */ +/****************************************************************/ +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC1_LVDF ((uint8_t)0x80) /*!< Low-Voltage Detect Flag */ +#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) /*!< Low-Voltage Detect Acknowledge */ +#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) /*!< Low-Voltage Detect Interrupt Enable */ +#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) /*!< Low-Voltage Detect Reset Enable */ +#define PMC_LVDSC1_LVDV_MASK ((uint8_t)0x3) /*!< Low-Voltage Detect Voltage Select */ +#define PMC_LVDSC1_LVDV_SHIFT 0 +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) +/********* Bits definition for PMC_LVDSC1 register *************/ +#define PMC_LVDSC2_LVWF ((uint8_t)0x80) /*!< Low-Voltage Warning Flag */ +#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) /*!< Low-Voltage Warning Acknowledge */ +#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) /*!< Low-Voltage Warning Interrupt Enable */ +#define PMC_LVDSC2_LVWV_MASK 0x3 /*!< Low-Voltage Warning Voltage Select */ +#define PMC_LVDSC2_LVWV_SHIFT 0 +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) +/********* Bits definition for PMC_REGSC register *************/ +#define PMC_REGSC_BGEN ((uint8_t)0x10) /*!< Bandgap Enable In VLPx Operation */ +#define PMC_REGSC_ACKISO ((uint8_t)0x8) /*!< Acknowledge Isolation */ +#define PMC_REGSC_REGONS ((uint8_t)0x4) /*!< Regulator In Run Regulation Status */ +#define PMC_REGSC_BGBE ((uint8_t)0x1) /*!< Bandgap Buffer Enable */ + +#endif diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.c b/os/hal/ports/KINETIS/KL2x/pal_lld.c new file mode 100644 index 0000000..a894c6a --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/pal_lld.c @@ -0,0 +1,225 @@ +/*
+ ChibiOS - Copyright (C) 2013..2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pal_lld.c
+ * @brief Kinetis KL2x PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief STM32 I/O ports configuration.
+ * @details Ports A-D(E, F, G, H) clocks enabled.
+ *
+ * @param[in] config the STM32 ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ int i, j;
+
+ /* Enable clocking of all Ports */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+ for (i = 0; i < TOTAL_PORTS; i++) {
+ for (j = 0; j < PADS_PER_PORT; j++) {
+ pal_lld_setpadmode(config->ports[i].port,
+ j,
+ config->ports[i].pads[j]);
+ }
+ }
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+
+ (void)port;
+ (void)mask;
+ (void)mode;
+
+}
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+uint8_t pal_lld_readpad(ioportid_t port, uint8_t pad)
+{
+ return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
+}
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+void pal_lld_writepad(ioportid_t port, uint8_t pad, uint8_t bit)
+{
+ if (bit == PAL_HIGH)
+ port->PDOR |= ((uint32_t) 1 << pad);
+ else
+ port->PDOR &= ~((uint32_t) 1 << pad);
+}
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
+{
+ PORT_TypeDef *portcfg = NULL;
+
+ osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
+
+ if (mode == PAL_MODE_OUTPUT_PUSHPULL)
+ port->PDDR |= ((uint32_t) 1 << pad);
+ else
+ port->PDDR &= ~((uint32_t) 1 << pad);
+
+ if (port == IOPORT1)
+ portcfg = PORTA;
+ else if (port == IOPORT2)
+ portcfg = PORTB;
+ else if (port == IOPORT3)
+ portcfg = PORTC;
+ else if (port == IOPORT4)
+ portcfg = PORTD;
+ else if (port == IOPORT5)
+ portcfg = PORTE;
+
+ osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() - invalid port");
+
+ switch (mode) {
+ case PAL_MODE_RESET:
+ case PAL_MODE_INPUT:
+ case PAL_MODE_OUTPUT_PUSHPULL:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
+ break;
+ case PAL_MODE_INPUT_PULLUP:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE | PORTx_PCRn_PS;
+ break;
+ case PAL_MODE_INPUT_PULLDOWN:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1) | PORTx_PCRn_PE;
+ break;
+ case PAL_MODE_UNCONNECTED:
+ case PAL_MODE_INPUT_ANALOG:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(0);
+ break;
+ case PAL_MODE_ALTERNATIVE_1:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(1);
+ break;
+ case PAL_MODE_ALTERNATIVE_2:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(2);
+ break;
+ case PAL_MODE_ALTERNATIVE_3:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(3);
+ break;
+ case PAL_MODE_ALTERNATIVE_4:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(4);
+ break;
+ case PAL_MODE_ALTERNATIVE_5:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(5);
+ break;
+ case PAL_MODE_ALTERNATIVE_6:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(6);
+ break;
+ case PAL_MODE_ALTERNATIVE_7:
+ portcfg->PCR[pad] = PORTx_PCRn_MUX(7);
+ break;
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pal_lld.h b/os/hal/ports/KINETIS/KL2x/pal_lld.h new file mode 100644 index 0000000..8b38709 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/pal_lld.h @@ -0,0 +1,331 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pal_lld.h
+ * @brief Kinetis KL2x PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+#define PAL_MODE_ALTERNATIVE_1 0x10
+#define PAL_MODE_ALTERNATIVE_2 0x11
+#define PAL_MODE_ALTERNATIVE_3 0x12
+#define PAL_MODE_ALTERNATIVE_4 0x13
+#define PAL_MODE_ALTERNATIVE_5 0x14
+#define PAL_MODE_ALTERNATIVE_6 0x15
+#define PAL_MODE_ALTERNATIVE_7 0x16
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+#define TOTAL_PORTS 5
+#define PADS_PER_PORT 32
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint8_t iomode_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef GPIO_TypeDef * ioportid_t;
+
+typedef struct {
+ ioportid_t port;
+ iomode_t pads[PADS_PER_PORT];
+} PortConfig;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct
+{
+ PortConfig ports[TOTAL_PORTS];
+} PALConfig;
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
+
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief First I/O port identifier.
+ * @details Low level drivers can define multiple ports, it is suggested to
+ * use this naming convention.
+ */
+#define IOPORT1 GPIOA
+#define IOPORT2 GPIOB
+#define IOPORT3 GPIOC
+#define IOPORT4 GPIOD
+#define IOPORT5 GPIOE
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) \
+ (port)->PDIR
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) \
+ (port)->PDOR
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) \
+ (port)->PDOR = (bits)
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) \
+ (port)->PSOR = (bits)
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) \
+ (port)->PCOR = (bits)
+
+/**
+ * @brief Toggles a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be XORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_toggleport(port, bits) \
+ (port)->PTOR = (bits)
+
+/**
+ * @brief Reads a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) 0
+
+/**
+ * @brief Writes a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode) \
+ _pal_lld_setpadmode(port, pad, mode)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+ void pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/platform.mk b/os/hal/ports/KINETIS/KL2x/platform.mk new file mode 100644 index 0000000..90671ee --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/platform.mk @@ -0,0 +1,15 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/i2c_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/ext_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD/adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x/st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS}/os/hal/ports/KINETIS/KL2x \
+ ${CHIBIOS}/os/hal/ports/KINETIS/LLD
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.c b/os/hal/ports/KINETIS/KL2x/pwm_lld.c new file mode 100644 index 0000000..4ba7d6e --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.c @@ -0,0 +1,400 @@ +/*
+ ChibiOS - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define KINETIS_TPM0_CHANNELS 6
+#define KINETIS_TPM1_CHANNELS 2
+#define KINETIS_TPM2_CHANNELS 2
+
+#define KINETIS_TPM0_HANDLER Vector84
+#define KINETIS_TPM1_HANDLER Vector88
+#define KINETIS_TPM2_HANDLER Vector8C
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer TPM0 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer TPM1 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer TPM2 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->tpm->STATUS;
+ pwmp->tpm->STATUS = 0xFFFFFFFF;
+
+ if (((sr & TPM_SC_TOF) != 0) &&
+ (pwmp->config->callback != NULL))
+ pwmp->config->callback(pwmp);
+ if (((sr & TPM_STATUS_CH0F) != 0) &&
+ (pwmp->config->channels[0].callback != NULL))
+ pwmp->config->channels[0].callback(pwmp);
+ if (((sr & TPM_STATUS_CH1F) != 0) &&
+ (pwmp->config->channels[1].callback != NULL))
+ pwmp->config->channels[1].callback(pwmp);
+ if (((sr & TPM_STATUS_CH2F) != 0) &&
+ (pwmp->config->channels[2].callback != NULL))
+ pwmp->config->channels[2].callback(pwmp);
+ if (((sr & TPM_STATUS_CH3F) != 0) &&
+ (pwmp->config->channels[3].callback != NULL))
+ pwmp->config->channels[3].callback(pwmp);
+ if (((sr & TPM_STATUS_CH4F) != 0) &&
+ (pwmp->config->channels[4].callback != NULL))
+ pwmp->config->channels[4].callback(pwmp);
+ if (((sr & TPM_STATUS_CH5F) != 0) &&
+ (pwmp->config->channels[5].callback != NULL))
+ pwmp->config->channels[5].callback(pwmp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_TPM0
+/**
+ * @brief TPM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM0_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM0 */
+
+#if KINETIS_PWM_USE_TPM1
+/**
+ * @brief TPM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM1_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM1 */
+
+#if KINETIS_PWM_USE_TPM2
+/**
+ * @brief TPM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_TPM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_TPM0_CHANNELS;
+ PWMD1.tpm = TPM0;
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_TPM1_CHANNELS;
+ PWMD2.tpm = TPM1;
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_TPM2_CHANNELS;
+ PWMD3.tpm = TPM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint32_t psc;
+ int i;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_TPM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM0;
+ nvicEnableVector(TPM0_IRQn, KINETIS_PWM_TPM0_IRQ_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM1;
+ nvicEnableVector(TPM1_IRQn, KINETIS_PWM_TPM1_IRQ_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM2;
+ nvicEnableVector(TPM2_IRQn, KINETIS_PWM_TPM2_IRQ_PRIORITY);
+ }
+#endif
+ }
+
+ /* Disable LPTPM counter.*/
+ pwmp->tpm->SC = 0;
+ /* Clear count register.*/
+ pwmp->tpm->CNT = 0;
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ /* Prescaler register value determination.
+ Prescaler register value conveniently corresponds to bit position,
+ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (1UL << i)) {
+ break;
+ }
+ }
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWM up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->tpm->SC = TPM_SC_CMOD_LPTPM_CLK | i;
+ /* Configure period.*/
+ pwmp->tpm->MOD = pwmp->period - 1;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_TPM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM0;
+ nvicDisableVector(TPM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM1;
+ nvicDisableVector(TPM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM2;
+ nvicDisableVector(TPM2_IRQn);
+ }
+#endif
+ /* Disable LPTPM counter.*/
+ pwmp->tpm->SC = 0;
+ pwmp->tpm->MOD = 0;
+ }
+}
+
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = TPM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= TPM_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= TPM_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->tpm->C[channel].SC & TPM_CnSC_CHIE)
+ mode |= TPM_CnSC_CHIE;
+
+ pwmp->tpm->C[channel].SC = mode;
+ pwmp->tpm->C[channel].V = width;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC = 0;
+ pwmp->tpm->C[channel].V = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+
+ pwmp->tpm->SC |= TPM_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+
+ pwmp->tpm->SC &= ~TPM_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC |= TPM_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC &= ~TPM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/pwm_lld.h b/os/hal/ports/KINETIS/KL2x/pwm_lld.h new file mode 100644 index 0000000..fe255bd --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/pwm_lld.h @@ -0,0 +1,243 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#include "kinetis_tpm.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_TPM0)
+#define KINETIS_PWM_USE_TPM0 FALSE
+#endif
+#if !defined(KINETIS_PWM_USE_TPM1)
+#define KINETIS_PWM_USE_TPM1 FALSE
+#endif
+#if !defined(KINETIS_PWM_USE_TPM2)
+#define KINETIS_PWM_USE_TPM2 FALSE
+#endif
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 6
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
+#error "PWM driver activated but no TPM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the TPM registers block.
+ */
+ TPM_TypeDef *tpm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ ((pwmp)->tpm->MOD = ((period) - 1))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.c b/os/hal/ports/KINETIS/KL2x/serial_lld.c new file mode 100644 index 0000000..f0cbc46 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/serial_lld.c @@ -0,0 +1,353 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.c
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+#include "kl25z.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] u pointer to an UART I/O block
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UARTLP_TypeDef *u = sdp->uart;
+
+ if (u->S1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&sdp->iqueue, u->D) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (u->S1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ u->C2 &= ~UARTx_C2_TIE;
+ } else {
+ u->D = b;
+ }
+ }
+
+ if (u->S1 & UARTx_S1_IDLE)
+ u->S1 = UARTx_S1_IDLE; // Clear IDLE (S1 bits are write-1-to-clear).
+
+ if (u->S1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ // FIXME: need to add set_error()
+ // Clear flags (S1 bits are write-1-to-clear).
+ u->S1 = UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ }
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UARTLP_TypeDef *u = sdp->uart;
+
+ if (u->S1 & UARTx_S1_TDRE) {
+ msg_t b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ u->D = b;
+ u->C2 |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(UARTLP_TypeDef *uart, const SerialConfig *config)
+{
+ uint32_t uart_clock;
+
+ uart->C1 = 0;
+ uart->C3 = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+ uart->S1 = UARTx_S1_IDLE | UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ while (uart->S1 & UARTx_S1_RDRF) {
+ (void)uart->D;
+ }
+
+#if KINETIS_SERIAL_USE_UART0
+ if (uart == UART0) {
+ /* UART0 can be clocked from several sources. */
+ uart_clock = KINETIS_UART0_CLOCK_FREQ;
+ }
+#endif
+#if KINETIS_SERIAL_USE_UART1
+ if (uart == UART1) {
+ uart_clock = KINETIS_BUSCLK_FREQUENCY;
+ }
+#endif
+#if KINETIS_SERIAL_USE_UART2
+ if (uart == UART2) {
+ uart_clock = KINETIS_BUSCLK_FREQUENCY;
+ }
+#endif
+
+ /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
+ uint16_t divisor = (uart_clock / 16) / config->sc_speed;
+ uart->C4 = UARTx_C4_OSR & (16 - 1);
+ uart->BDH = (divisor >> 8) & UARTx_BDH_SBR;
+ uart->BDL = (divisor & UARTx_BDL_SBR);
+
+ uart->C2 = UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector70) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector74) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(Vector78) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.uart = UART0;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+ SD2.uart = UART1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart = UART2;
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
+ SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp->uart, config);
+ nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ nvicDisableVector(UART0_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+ nvicDisableVector(UART1_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ nvicDisableVector(UART2_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/serial_lld.h b/os/hal/ports/KINETIS/KL2x/serial_lld.h new file mode 100644 index 0000000..2d003b0 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/serial_lld.h @@ -0,0 +1,163 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.h
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SD1 driver enable switch.
+ * @details If set to @p TRUE the support for SD1 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART0 FALSE
+#endif
+/**
+ * @brief SD2 driver enable switch.
+ * @details If set to @p TRUE the support for SD2 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART1 FALSE
+#endif
+/**
+ * @brief SD3 driver enable switch.
+ * @details If set to @p TRUE the support for SD3 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART2 FALSE
+#endif
+
+/**
+ * @brief UART0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART0_PRIORITY 12
+#endif
+
+/**
+ * @brief UART1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART1_PRIORITY 12
+#endif
+
+/**
+ * @brief UART2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART2_PRIORITY 12
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /* End of the mandatory fields.*/
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the UART registers block.*/ \
+ UARTLP_TypeDef *uart;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.c b/os/hal/ports/KINETIS/KL2x/st_lld.c new file mode 100644 index 0000000..1f8cb63 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/st_lld.c @@ -0,0 +1,98 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/KL2x/st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+ in this mode.*/
+ SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+
+ /* IRQ enabled.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/KL2x/st_lld.h b/os/hal/ports/KINETIS/KL2x/st_lld.h new file mode 100644 index 0000000..24044e5 --- /dev/null +++ b/os/hal/ports/KINETIS/KL2x/st_lld.h @@ -0,0 +1,156 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ST_IRQ_PRIORITY 8
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* _ST_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/adc_lld.c b/os/hal/ports/KINETIS/LLD/adc_lld.c new file mode 100644 index 0000000..c0904c8 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/adc_lld.c @@ -0,0 +1,258 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/adc_lld.c
+ * @brief KINETIS ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define ADC_CHANNEL_MASK 0x1f
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void calibrate(ADCDriver *adcp) {
+
+ /* Clock Divide by 8, Use Bus Clock Div 2 */
+ /* At 48MHz this results in ADCCLK of 48/8/2 == 3MHz */
+ adcp->adc->CFG1 = ADCx_CFG1_ADIV(ADCx_CFG1_ADIV_DIV_8) |
+ ADCx_CFG1_ADICLK(ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2);
+
+ /* Use software trigger and disable DMA etc. */
+ adcp->adc->SC2 = 0;
+
+ /* Enable Hardware Average, Average 32 Samples, Calibrate */
+ adcp->adc->SC3 = ADCx_SC3_AVGE |
+ ADCx_SC3_AVGS(ADCx_SC3_AVGS_AVERAGE_32_SAMPLES) |
+ ADCx_SC3_CAL;
+
+ /* FIXME: May take several ms. Use an interrupt instead of busy wait */
+ /* Wait for calibration completion */
+ while (!(adcp->adc->SC1A & ADCx_SC1n_COCO))
+ ;
+
+ uint16_t gain = ((adcp->adc->CLP0 + adcp->adc->CLP1 + adcp->adc->CLP2 +
+ adcp->adc->CLP3 + adcp->adc->CLP4 + adcp->adc->CLPS) / 2) | 0x8000;
+ adcp->adc->PG = gain;
+
+ gain = ((adcp->adc->CLM0 + adcp->adc->CLM1 + adcp->adc->CLM2 +
+ adcp->adc->CLM3 + adcp->adc->CLM4 + adcp->adc->CLMS) / 2) | 0x8000;
+ adcp->adc->MG = gain;
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_ADC0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ ADCDriver *adcp = &ADCD1;
+
+ /* Disable Interrupt, Disable Channel */
+ adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
+
+ /* Read the sample into the buffer */
+ adcp->samples[adcp->current_index++] = adcp->adc->RA;
+
+ bool more = true;
+
+ /* At the end of the buffer then we may be finished */
+ if (adcp->current_index == adcp->number_of_samples) {
+ _adc_isr_full_code(&ADCD1);
+
+ adcp->current_index = 0;
+
+ /* We are never finished in circular mode */
+ more = ADCD1.grpp->circular;
+ }
+
+ if (more) {
+
+ /* Signal half completion in circular mode. */
+ if (ADCD1.grpp->circular &&
+ (adcp->current_index == (adcp->number_of_samples / 2))) {
+
+ _adc_isr_half_code(&ADCD1);
+ }
+
+ /* Skip to the next channel */
+ do {
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ } while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0);
+
+ /* Enable Interrupt, Select the Channel */
+ adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if KINETIS_ADC_USE_ADC0
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+#endif
+
+ /* The shared vector is initialized on driver initialization and never
+ disabled.*/
+ nvicEnableVector(ADC0_IRQn, KINETIS_ADC_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ /* If in stopped state then enables the ADC clock.*/
+ if (adcp->state == ADC_STOP) {
+ SIM->SCGC6 |= SIM_SCGC6_ADC0;
+
+#if KINETIS_ADC_USE_ADC0
+ if (&ADCD1 == adcp) {
+ adcp->adc = ADC0;
+ if (adcp->config->calibrate) {
+ calibrate(adcp);
+ }
+ }
+#endif /* KINETIS_ADC_USE_ADC0 */
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock.*/
+ if (adcp->state == ADC_READY) {
+ SIM->SCGC6 &= ~SIM_SCGC6_ADC0;
+
+#if KINETIS_ADC_USE_ADC0
+ if (&ADCD1 == adcp) {
+ /* Disable Interrupt, Disable Channel */
+ adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* Enable the Bandgap Buffer if channel mask includes BANDGAP */
+ if (grpp->channel_mask & ADC_BANDGAP) {
+ PMC->REGSC |= PMC_REGSC_BGBE;
+ }
+
+ adcp->number_of_samples = adcp->depth * grpp->num_channels;
+ adcp->current_index = 0;
+
+ /* Skip to the next channel */
+ adcp->current_channel = 0;
+ while (((1 << adcp->current_channel) & grpp->channel_mask) == 0) {
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ }
+
+ /* Set clock speed and conversion size */
+ adcp->adc->CFG1 = grpp->cfg1;
+
+ /* Set averaging */
+ adcp->adc->SC3 = grpp->sc3;
+
+ /* Enable Interrupt, Select Channel */
+ adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* Disable the Bandgap buffer if channel mask includes BANDGAP */
+ if (grpp->channel_mask & ADC_BANDGAP) {
+ /* Clear BGBE, ACKISO is w1c, avoid setting */
+ PMC->REGSC &= ~(PMC_REGSC_BGBE | PMC_REGSC_ACKISO);
+ }
+
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/adc_lld.h b/os/hal/ports/KINETIS/LLD/adc_lld.h new file mode 100644 index 0000000..22db2c0 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/adc_lld.h @@ -0,0 +1,360 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/adc_lld.h
+ * @brief KINETIS ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Minimum ADC clock frequency.
+ */
+#define KINETIS_ADCCLK_MIN 600000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define KINETIS_ADCCLK_MAX 36000000
+
+#define ADCx_SC3_AVGS_AVERAGE_4_SAMPLES 0
+#define ADCx_SC3_AVGS_AVERAGE_8_SAMPLES 1
+#define ADCx_SC3_AVGS_AVERAGE_16_SAMPLES 2
+#define ADCx_SC3_AVGS_AVERAGE_32_SAMPLES 3
+
+#define ADCx_CFG1_ADIV_DIV_1 0
+#define ADCx_CFG1_ADIV_DIV_2 1
+#define ADCx_CFG1_ADIV_DIV_4 2
+#define ADCx_CFG1_ADIV_DIV_8 3
+
+#define ADCx_CFG1_ADIVCLK_BUS_CLOCK 0
+#define ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2 1
+#define ADCx_CFG1_ADIVCLK_BUS_ALTCLK 2
+#define ADCx_CFG1_ADIVCLK_BUS_ADACK 3
+
+#define ADCx_CFG1_MODE_8_OR_9_BITS 0
+#define ADCx_CFG1_MODE_12_OR_13_BITS 1
+#define ADCx_CFG1_MODE_10_OR_11_BITS 2
+#define ADCx_CFG1_MODE_16_BITS 3
+
+#define ADCx_SC1n_ADCH_DAD0 0
+#define ADCx_SC1n_ADCH_DAD1 1
+#define ADCx_SC1n_ADCH_DAD2 2
+#define ADCx_SC1n_ADCH_DAD3 3
+#define ADCx_SC1n_ADCH_DADP0 0
+#define ADCx_SC1n_ADCH_DADP1 1
+#define ADCx_SC1n_ADCH_DADP2 2
+#define ADCx_SC1n_ADCH_DADP3 3
+#define ADCx_SC1n_ADCH_AD4 4
+#define ADCx_SC1n_ADCH_AD5 5
+#define ADCx_SC1n_ADCH_AD6 6
+#define ADCx_SC1n_ADCH_AD7 7
+#define ADCx_SC1n_ADCH_AD8 8
+#define ADCx_SC1n_ADCH_AD9 9
+#define ADCx_SC1n_ADCH_AD10 10
+#define ADCx_SC1n_ADCH_AD11 11
+#define ADCx_SC1n_ADCH_AD12 12
+#define ADCx_SC1n_ADCH_AD13 13
+#define ADCx_SC1n_ADCH_AD14 14
+#define ADCx_SC1n_ADCH_AD15 15
+#define ADCx_SC1n_ADCH_AD16 16
+#define ADCx_SC1n_ADCH_AD17 17
+#define ADCx_SC1n_ADCH_AD18 18
+#define ADCx_SC1n_ADCH_AD19 19
+#define ADCx_SC1n_ADCH_AD20 20
+#define ADCx_SC1n_ADCH_AD21 21
+#define ADCx_SC1n_ADCH_AD22 22
+#define ADCx_SC1n_ADCH_AD23 23
+#define ADCx_SC1n_ADCH_TEMP_SENSOR 26
+#define ADCx_SC1n_ADCH_BANDGAP 27
+#define ADCx_SC1n_ADCH_VREFSH 29
+#define ADCx_SC1n_ADCH_VREFSL 30
+#define ADCx_SC1n_ADCH_DISABLED 31
+
+#define ADC_DAD0 (1 << ADCx_SC1n_ADCH_DAD0)
+#define ADC_DAD1 (1 << ADCx_SC1n_ADCH_DAD1)
+#define ADC_DAD2 (1 << ADCx_SC1n_ADCH_DAD2)
+#define ADC_DAD3 (1 << ADCx_SC1n_ADCH_DAD3)
+#define ADC_DADP0 (1 << ADCx_SC1n_ADCH_DADP0)
+#define ADC_DADP1 (1 << ADCx_SC1n_ADCH_DADP1)
+#define ADC_DADP2 (1 << ADCx_SC1n_ADCH_DADP2)
+#define ADC_DADP3 (1 << ADCx_SC1n_ADCH_DADP3)
+#define ADC_AD4 (1 << ADCx_SC1n_ADCH_AD4)
+#define ADC_AD5 (1 << ADCx_SC1n_ADCH_AD5)
+#define ADC_AD6 (1 << ADCx_SC1n_ADCH_AD6)
+#define ADC_AD7 (1 << ADCx_SC1n_ADCH_AD7)
+#define ADC_AD8 (1 << ADCx_SC1n_ADCH_AD8)
+#define ADC_AD9 (1 << ADCx_SC1n_ADCH_AD9)
+#define ADC_AD10 (1 << ADCx_SC1n_ADCH_AD10)
+#define ADC_AD11 (1 << ADCx_SC1n_ADCH_AD11)
+#define ADC_AD12 (1 << ADCx_SC1n_ADCH_AD12)
+#define ADC_AD13 (1 << ADCx_SC1n_ADCH_AD13)
+#define ADC_AD14 (1 << ADCx_SC1n_ADCH_AD14)
+#define ADC_AD15 (1 << ADCx_SC1n_ADCH_AD15)
+#define ADC_AD16 (1 << ADCx_SC1n_ADCH_AD16)
+#define ADC_AD17 (1 << ADCx_SC1n_ADCH_AD17)
+#define ADC_AD18 (1 << ADCx_SC1n_ADCH_AD18)
+#define ADC_AD19 (1 << ADCx_SC1n_ADCH_AD19)
+#define ADC_AD20 (1 << ADCx_SC1n_ADCH_AD20)
+#define ADC_AD21 (1 << ADCx_SC1n_ADCH_AD21)
+#define ADC_AD22 (1 << ADCx_SC1n_ADCH_AD22)
+#define ADC_AD23 (1 << ADCx_SC1n_ADCH_AD23)
+#define ADC_TEMP_SENSOR (1 << ADCx_SC1n_ADCH_TEMP_SENSOR)
+#define ADC_BANDGAP (1 << ADCx_SC1n_ADCH_BANDGAP)
+#define ADC_VREFSH (1 << ADCx_SC1n_ADCH_VREFSH)
+#define ADC_VREFSL (1 << ADCx_SC1n_ADCH_VREFSL)
+#define ADC_DISABLED (1 << ADCx_SC1n_ADCH_DISABLED)
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_ADC_USE_ADC0) || defined(__DOXYGEN__)
+#define KINETIS_ADC_USE_ADC0 FALSE
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(KINETIS_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ADC_IRQ_PRIORITY 5
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 && !KINETIS_HAS_ADC0
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !KINETIS_ADC_USE_ADC0
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Bitmask of channels for ADC conversion.
+ */
+ uint32_t channel_mask;
+ /**
+ * @brief ADC CFG1 register initialization data.
+ * @note All the required bits must be defined into this field.
+ */
+ uint32_t cfg1;
+ /**
+ * @brief ADC SC3 register initialization data.
+ * @note All the required bits must be defined into this field.
+ */
+ uint32_t sc3;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /* Perform first time calibration */
+ bool calibrate;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+ /**
+ * @brief Number of samples expected.
+ */
+ size_t number_of_samples;
+ /**
+ * @brief Current position in the buffer.
+ */
+ size_t current_index;
+ /**
+ * @brief Current channel index into group channel_mask.
+ */
+ size_t current_channel;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/ext_lld.c b/os/hal/ports/KINETIS/LLD/ext_lld.c new file mode 100644 index 0000000..e85f032 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/ext_lld.c @@ -0,0 +1,361 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/ext_lld.c
+ * @brief KINETIS EXT subsystem low level driver source.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define PCR_IRQC_DISABLED 0x0
+#define PCR_IRQC_DMA_RISING_EDGE 0x1
+#define PCR_IRQC_DMA_FALLING_EDGE 0x2
+#define PCR_IRQC_DMA_EITHER_EDGE 0x3
+
+#define PCR_IRQC_LOGIC_ZERO 0x8
+#define PCR_IRQC_RISING_EDGE 0x9
+#define PCR_IRQC_FALLING_EDGE 0xA
+#define PCR_IRQC_EITHER_EDGE 0xB
+#define PCR_IRQC_LOGIC_ONE 0xC
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTD1 driver identifier.
+ */
+EXTDriver EXTD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/* A channel map for each channel.
+ *
+ * The index is the pin number.
+ * The result is the channel for that pin.
+ */
+#if KINETIS_EXT_PORTA_WIDTH > 0
+uint8_t porta_channel_map[KINETIS_EXT_PORTA_WIDTH];
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+uint8_t portb_channel_map[KINETIS_EXT_PORTB_WIDTH];
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+uint8_t portc_channel_map[KINETIS_EXT_PORTC_WIDTH];
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+uint8_t portd_channel_map[KINETIS_EXT_PORTD_WIDTH];
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+uint8_t porte_channel_map[KINETIS_EXT_PORTE_WIDTH];
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_exti_irq_enable(void) {
+
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ nvicEnableVector(PINA_IRQn, KINETIS_EXT_PORTA_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ nvicEnableVector(PINB_IRQn, KINETIS_EXT_PORTB_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ nvicEnableVector(PINC_IRQn, KINETIS_EXT_PORTC_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ nvicEnableVector(PIND_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ nvicEnableVector(PINE_IRQn, KINETIS_EXT_PORTE_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_exti_irq_disable(void) {
+
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ nvicDisableVector(PINA_IRQn);
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ nvicDisableVector(PINB_IRQn);
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ nvicDisableVector(PINC_IRQn);
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ nvicDisableVector(PIND_IRQn);
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ nvicDisableVector(PINE_IRQn);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*
+ * Generic interrupt handler.
+ */
+static inline void irq_handler(PORT_TypeDef * const port, const unsigned port_width, const uint8_t *channel_map) {
+ unsigned pin;
+ uint32_t isfr = port->ISFR;
+
+ /* Clear all pending interrupts on this port. */
+ port->ISFR = 0xFFFFFFFF;
+
+ for (pin = 0; pin < port_width; pin++) {
+ if (isfr & (1 << pin)) {
+ expchannel_t channel = channel_map[pin];
+ EXTD1.config->channels[channel].cb(&EXTD1, channel);
+ }
+ }
+}
+
+/**
+ * @brief PORTA interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTA_IRQ_VECTOR) && KINETIS_EXT_PORTA_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTA_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTA, KINETIS_EXT_PORTA_WIDTH, porta_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTA_WIDTH > 0 */
+
+/**
+ * @brief PORTB interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTB_IRQ_VECTOR) && KINETIS_EXT_PORTB_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTB_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTB_WIDTH > 0 */
+
+/**
+ * @brief PORTC interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTC_IRQ_VECTOR) && KINETIS_EXT_PORTC_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTC_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTC_WIDTH > 0 */
+
+/**
+ * @brief PORTD interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTD_IRQ_VECTOR) && KINETIS_EXT_PORTD_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTD_WIDTH > 0 */
+
+/**
+ * @brief PORTE interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTE_IRQ_VECTOR) && KINETIS_EXT_PORTE_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTE_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTE_WIDTH > 0 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level EXT driver initialization.
+ *
+ * @notapi
+ */
+void ext_lld_init(void) {
+
+ /* Driver initialization.*/
+ extObjectInit(&EXTD1);
+}
+
+/**
+ * @brief Configures and activates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_start(EXTDriver *extp) {
+ expchannel_t channel;
+
+ if (extp->state == EXT_STOP)
+ ext_lld_exti_irq_enable();
+
+ /* Configuration of automatic channels.*/
+ for (channel = 0; channel < EXT_MAX_CHANNELS; channel++) {
+
+ uint32_t mode = extp->config->channels[channel].mode;
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+
+ /* Initialize the channel map */
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ if (port == PORTA)
+ porta_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ if (port == PORTB)
+ portb_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ if (port == PORTC)
+ portc_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ if (port == PORTD)
+ portd_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ if (port == PORTE)
+ porte_channel_map[pin] = channel;
+ else
+#endif
+ {}
+
+ if (mode & EXT_CH_MODE_AUTOSTART)
+ ext_lld_channel_enable(extp, channel);
+ else if (port != NULL)
+ ext_lld_channel_disable(extp, channel);
+ }
+}
+
+/**
+ * @brief Deactivates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_stop(EXTDriver *extp) {
+
+ if (extp->state == EXT_ACTIVE)
+ ext_lld_exti_irq_disable();
+}
+
+/**
+ * @brief Enables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be enabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+
+ uint32_t irqc;
+ uint32_t mode = extp->config->channels[channel].mode;
+ if (mode & EXT_CH_MODE_RISING_EDGE)
+ irqc = PCR_IRQC_RISING_EDGE;
+ else if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
+ irqc = PCR_IRQC_FALLING_EDGE;
+ else if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES)
+ irqc = PCR_IRQC_EITHER_EDGE;
+ else
+ irqc = PCR_IRQC_DISABLED;
+
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+
+ uint32_t pcr = port->PCR[pin];
+
+ /* Clear all the IRQC bits */
+ pcr &= ~PORTx_PCRn_IRQC_MASK;
+ /* Set the required IRQC bits */
+ pcr |= PORTx_PCRn_IRQC(irqc);
+
+ port->PCR[pin] = pcr;
+}
+
+/**
+ * @brief Disables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be disabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+ port->PCR[pin] |= PORTx_PCRn_IRQC(PCR_IRQC_DISABLED);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/ext_lld.h b/os/hal/ports/KINETIS/LLD/ext_lld.h new file mode 100644 index 0000000..465bb89 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/ext_lld.h @@ -0,0 +1,188 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/ext_lld.h
+ * @brief KINETIS EXT subsystem low level driver header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef _EXT_LLD_H_
+#define _EXT_LLD_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of EXT channels required.
+ */
+#define EXT_MAX_CHANNELS KINETIS_EXTI_NUM_CHANNELS
+
+/**
+ * @name KINETIS-specific EXT channel modes
+ * @{
+ */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief PORTA interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTA_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTB interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTB_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTC interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTC_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTD interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTD_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTE interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTE_IRQ_PRIORITY 3
+#endif
+/** @} */
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief EXT channel identifier.
+ */
+typedef uint32_t expchannel_t;
+
+/**
+ * @brief Type of an EXT generic notification callback.
+ *
+ * @param[in] extp pointer to the @p EXPDriver object triggering the
+ * callback
+ */
+typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
+
+/**
+ * @brief Channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel mode.
+ */
+ uint32_t mode;
+ /**
+ * @brief Channel callback.
+ */
+ extcallback_t cb;
+
+ /**
+ * @brief Port.
+ */
+ PORT_TypeDef *port;
+
+ /**
+ * @brief Pin.
+ */
+ uint32_t pin;
+} EXTChannelConfig;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Channel configurations.
+ */
+ EXTChannelConfig channels[EXT_MAX_CHANNELS];
+ /* End of the mandatory fields.*/
+} EXTConfig;
+
+/**
+ * @brief Structure representing an EXT driver.
+ */
+struct EXTDriver {
+ /**
+ * @brief Driver state.
+ */
+ extstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const EXTConfig *config;
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern EXTDriver EXTD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_init(void);
+ void ext_lld_start(EXTDriver *extp);
+ void ext_lld_stop(EXTDriver *extp);
+ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
+ void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* _EXT_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.c b/os/hal/ports/KINETIS/LLD/i2c_lld.c new file mode 100644 index 0000000..4e42d16 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.c @@ -0,0 +1,415 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/i2c_lld.c
+ * @brief KINETIS I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief I2C0 driver identifier.
+ */
+#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/**
+ * @brief I2C1 driver identifier.
+ */
+#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void config_frequency(I2CDriver *i2cp) {
+
+ /* Each index in the table corresponds to a a frequency
+ * divider used to generate the SCL clock from the main
+ * system clock.
+ */
+ uint16_t icr_table[] = {
+ /* 0x00 - 0x0F */
+ 20,22,24,26,28,30,34,40,28,32,36,40,44,48,56,68,
+ /* 0x10 - 0x1F */
+ 48,56,64,72,80,88,104,128,80,96,112,128,144,160,192,240,
+ /* 0x20 - 0x2F */
+ 160,192,224,256,288,320,384,480,320,384,448,512,576,640,768,960,
+ /* 0x30 - 0x3F */
+ 640,768,896,1024,1152,1280,1536,1920,1280,1536,1792,2048,2304,2560,3072,3840,
+ };
+
+ int length = sizeof(icr_table) / sizeof(icr_table[0]);
+ uint16_t divisor;
+ uint8_t i = 0, index = 0;
+ uint16_t best, diff;
+
+ if (i2cp->config != NULL)
+ divisor = KINETIS_SYSCLK_FREQUENCY / i2cp->config->clock;
+ else
+ divisor = KINETIS_SYSCLK_FREQUENCY / 100000;
+
+ best = ~0;
+ index = 0;
+ /* Tries to find the SCL clock which is the closest
+ * approximation to the clock passed in config. To
+ * stay on the safe side, only values that generate
+ * lower frequency are used.
+ */
+ for (i = 0; i < length; i++) {
+ if (icr_table[i] >= divisor) {
+ diff = icr_table[i] - divisor;
+ if (diff < best) {
+ best = diff;
+ index = i;
+ }
+ }
+ }
+
+ i2cp->i2c->F = index;
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] i2cp pointer to an I2CDriver
+ */
+static void serve_interrupt(I2CDriver *i2cp) {
+
+ I2C_TypeDef *i2c = i2cp->i2c;
+ intstate_t state = i2cp->intstate;
+
+ if (i2c->S & I2Cx_S_ARBL) {
+
+ i2cp->errors |= I2C_ARBITRATION_LOST;
+ i2c->S |= I2Cx_S_ARBL;
+
+ } else if (state == STATE_SEND) {
+
+ if (i2c->S & I2Cx_S_RXAK)
+ i2cp->errors |= I2C_ACK_FAILURE;
+ else if (i2cp->txbuf != NULL && i2cp->txidx < i2cp->txbytes)
+ i2c->D = i2cp->txbuf[i2cp->txidx++];
+ else
+ i2cp->intstate = STATE_STOP;
+
+ } else if (state == STATE_DUMMY) {
+
+ if (i2c->S & I2Cx_S_RXAK)
+ i2cp->errors |= I2C_ACK_FAILURE;
+ else {
+ i2c->C1 &= ~I2Cx_C1_TX;
+
+ if (i2cp->rxbytes > 1)
+ i2c->C1 &= ~I2Cx_C1_TXAK;
+ else
+ i2c->C1 |= I2Cx_C1_TXAK;
+ (void) i2c->D;
+ i2cp->intstate = STATE_RECV;
+ }
+
+ } else if (state == STATE_RECV) {
+
+ if (i2cp->rxbytes > 1) {
+ if (i2cp->rxidx == (i2cp->rxbytes - 2))
+ i2c->C1 |= I2Cx_C1_TXAK;
+ else
+ i2c->C1 &= ~I2Cx_C1_TXAK;
+ }
+
+ if (i2cp->rxidx == i2cp->rxbytes - 1)
+ i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+
+ i2cp->rxbuf[i2cp->rxidx++] = i2c->D;
+
+ if (i2cp->rxidx == i2cp->rxbytes)
+ i2cp->intstate = STATE_STOP;
+ }
+
+ /* Reset interrupt flag */
+ i2c->S |= I2Cx_S_IICIF;
+
+ if (i2cp->errors != I2C_NO_ERROR)
+ _i2c_wakeup_error_isr(i2cp);
+
+ if (i2cp->intstate == STATE_STOP)
+ _i2c_wakeup_isr(i2cp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_I2C0_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&I2CD1);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
+
+/* FIXME: KL2x has I2C1 on Vector64; K2x don't have I2C1! */
+OSAL_IRQ_HANDLER(Vector64) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&I2CD2);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if KINETIS_I2C_USE_I2C0
+ i2cObjectInit(&I2CD1);
+ I2CD1.thread = NULL;
+ I2CD1.i2c = I2C0;
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ i2cObjectInit(&I2CD2);
+ I2CD2.thread = NULL;
+ I2CD2.i2c = I2C1;
+#endif
+
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+
+ if (i2cp->state == I2C_STOP) {
+
+ /* TODO:
+ * The PORT must be enabled somewhere. The PIN multiplexer
+ * will map the I2C functionality to some PORT which must
+ * than be enabled. The easier way is enabling all PORTs at
+ * startup, which is currently being done in __early_init.
+ */
+
+#if KINETIS_I2C_USE_I2C0
+ if (&I2CD1 == i2cp) {
+ SIM->SCGC4 |= SIM_SCGC4_I2C0;
+ nvicEnableVector(I2C0_IRQn, KINETIS_I2C_I2C0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ if (&I2CD2 == i2cp) {
+ SIM->SCGC4 |= SIM_SCGC4_I2C1;
+ nvicEnableVector(I2C1_IRQn, KINETIS_I2C_I2C1_PRIORITY);
+ }
+#endif
+
+ }
+
+ config_frequency(i2cp);
+ i2cp->i2c->C1 |= I2Cx_C1_IICEN | I2Cx_C1_IICIE;
+ i2cp->intstate = STATE_STOP;
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+ if (i2cp->state != I2C_STOP) {
+
+ i2cp->i2c->C1 &= ~(I2Cx_C1_IICEN | I2Cx_C1_IICIE);
+
+#if KINETIS_I2C_USE_I2C0
+ if (&I2CD1 == i2cp) {
+ SIM->SCGC4 &= ~SIM_SCGC4_I2C0;
+ nvicDisableVector(I2C0_IRQn);
+ }
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ if (&I2CD2 == i2cp) {
+ SIM->SCGC4 &= ~SIM_SCGC4_I2C1;
+ nvicDisableVector(I2C1_IRQn);
+ }
+#endif
+
+ }
+}
+
+static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ (void)timeout;
+ msg_t msg;
+
+ uint8_t op = (i2cp->intstate == STATE_SEND) ? 0 : 1;
+
+ i2cp->errors = I2C_NO_ERROR;
+ i2cp->addr = addr;
+
+ i2cp->txbuf = txbuf;
+ i2cp->txbytes = txbytes;
+ i2cp->txidx = 0;
+
+ i2cp->rxbuf = rxbuf;
+ i2cp->rxbytes = rxbytes;
+ i2cp->rxidx = 0;
+
+ /* send START */
+ i2cp->i2c->C1 |= I2Cx_C1_MST;
+ i2cp->i2c->C1 |= I2Cx_C1_TX;
+
+ /* FIXME: should not use busy waiting! */
+ while (!(i2cp->i2c->S & I2Cx_S_BUSY));
+
+ i2cp->i2c->D = addr << 1 | op;
+
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE);
+
+ /* FIXME */
+ //if (i2cp->i2c->S & I2Cx_S_RXAK)
+ // i2cp->errors |= I2C_ACK_FAILURE;
+
+ if (msg == MSG_OK && txbuf != NULL && rxbuf != NULL) {
+ i2cp->i2c->C1 |= I2Cx_C1_RSTA;
+ /* FIXME */
+ while (!(i2cp->i2c->S & I2Cx_S_BUSY));
+
+ i2cp->intstate = STATE_DUMMY;
+ i2cp->i2c->D = i2cp->addr << 1 | 1;
+
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, TIME_INFINITE);
+ }
+
+ i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+ /* FIXME */
+ while (i2cp->i2c->S & I2Cx_S_BUSY);
+
+ return msg;
+}
+
+/**
+ * @brief Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ i2cp->intstate = STATE_DUMMY;
+ return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout);
+}
+
+/**
+ * @brief Transmits data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[in] txbuf pointer to the transmit buffer
+ * @param[in] txbytes number of bytes to be transmitted
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ i2cp->intstate = STATE_SEND;
+ return _i2c_txrx_timeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/i2c_lld.h b/os/hal/ports/KINETIS/LLD/i2c_lld.h new file mode 100644 index 0000000..11de3ae --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/i2c_lld.h @@ -0,0 +1,208 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/i2c_lld.h
+ * @brief KINETIS I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define STATE_STOP 0x00
+#define STATE_SEND 0x01
+#define STATE_RECV 0x02
+#define STATE_DUMMY 0x03
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2C0 driver enable switch.
+ * @details If set to @p TRUE the support for I2C0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_I2C_USE_I2C0) || defined(__DOXYGEN__)
+#define KINETIS_I2C_USE_I2C0 FALSE
+#endif
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define KINETIS_I2C_USE_I2C1 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* @brief Type representing I2C address. */
+typedef uint8_t i2caddr_t;
+
+/* @brief Type of I2C Driver condition flags. */
+typedef uint32_t i2cflags_t;
+
+/* @brief Type used to control the ISR state machine. */
+typedef uint8_t intstate_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+
+ /* @brief Clock to be used for the I2C bus. */
+ uint32_t clock;
+
+} I2CConfig;
+
+/**
+ * @brief Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2cstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2CConfig *config;
+ /**
+ * @brief Error flags.
+ */
+ i2cflags_t errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#elif CH_CFG_USE_SEMAPHORES
+ semaphore_t semaphore;
+#endif
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+ I2C_DRIVER_EXT_FIELDS
+#endif
+ /* @brief Thread waiting for I/O completion. */
+ thread_reference_t thread;
+ /* @brief Current slave address without R/W bit. */
+ i2caddr_t addr;
+
+ /* End of the mandatory fields.*/
+
+ /* @brief Pointer to the buffer with data to send. */
+ const uint8_t *txbuf;
+ /* @brief Number of bytes of data to send. */
+ size_t txbytes;
+ /* @brief Current index in buffer when sending data. */
+ size_t txidx;
+ /* @brief Pointer to the buffer to put received data. */
+ uint8_t *rxbuf;
+ /* @brief Number of bytes of data to receive. */
+ size_t rxbytes;
+ /* @brief Current index in buffer when receiving data. */
+ size_t rxidx;
+ /* @brief Tracks current ISR state. */
+ intstate_t intstate;
+ /* @brief Low-level register access. */
+ I2C_TypeDef *i2c;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Get errors from I2C driver.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+#if KINETIS_I2C_USE_I2C0
+extern I2CDriver I2CD1;
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+extern I2CDriver I2CD2;
+#endif
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2c_lld_init(void);
+ void i2c_lld_start(I2CDriver *i2cp);
+ void i2c_lld_stop(I2CDriver *i2cp);
+ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C */
+
+#endif /* _I2C_LLD_H_ */
+
+/** @} */
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