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| author | marcoveeneman <marco-veeneman@hotmail.com> | 2015-03-17 21:44:45 +0100 |
|---|---|---|
| committer | marcoveeneman <marco-veeneman@hotmail.com> | 2015-03-17 21:44:45 +0100 |
| commit | 6c105d29d2e8a3ea3a8b361214659d3715bf7bb9 (patch) | |
| tree | 7c937d5a4c45267c6230f5ff77f5dbdbf5f5b933 /os/hal/ports/TIVA/TM4C123x/tm4c123x.h | |
| parent | e941fc7f5bd63c65c8b2cc987f6e01f1dc5ffa7d (diff) | |
| download | ChibiOS-Contrib-6c105d29d2e8a3ea3a8b361214659d3715bf7bb9.tar.gz ChibiOS-Contrib-6c105d29d2e8a3ea3a8b361214659d3715bf7bb9.tar.bz2 ChibiOS-Contrib-6c105d29d2e8a3ea3a8b361214659d3715bf7bb9.zip | |
Changed Tiva UDMA peripheral structure for TM4C123x.
Diffstat (limited to 'os/hal/ports/TIVA/TM4C123x/tm4c123x.h')
| -rw-r--r-- | os/hal/ports/TIVA/TM4C123x/tm4c123x.h | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h index dbae42c..b3444e9 100644 --- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h +++ b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h @@ -505,7 +505,8 @@ typedef struct */ typedef struct { - __IO uint32_t CR[2]; /**< Control 0, 1 */ + __IO uint32_t CR0; /**< Control 0 */ + __IO uint32_t CR1; /**< Control 1 */ __IO uint32_t DR; /**< Data */ __I uint32_t SR; /**< Status */ __IO uint32_t CPSR; /**< Clock Prescale */ @@ -742,11 +743,16 @@ typedef struct __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */ __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */ __O uint32_t SWREQ; /**< Channel Software Request */ - UDMA_SC_t USEBURST; /**< Channel Useburst registers */ - UDMA_SC_t REQMASK; /**< Channel Request Mask registers */ - UDMA_SC_t ENA; /**< Channel Enable registers */ - UDMA_SC_t ALT; /**< Channel Primary Alternate registers */ - UDMA_SC_t PRIO; /**< Channel Priority registers */ + __IO uint32_t USEBURSTSET; /**< Channel Useburst Set */ + __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear */ + __IO uint32_t REQMASKSET; /**< Channel Request Mask Set */ + __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear */ + __IO uint32_t ENASET; /**< Channel Enable Set */ + __O uint32_t ENACLR; /**< Channel Enable Clear */ + __IO uint32_t ALTSET; /**< Channel Primary Alternate Set */ + __O uint32_t ALTCLR; /**< Channel Primary Alternate Clear */ + __IO uint32_t PRIOSET; /**< Channel Priority Set */ + __O uint32_t PRIOCLR; /**< Channel Priority Clear */ __I uint32_t _RESERVED0[3]; /**< Reserved */ __IO uint32_t ERRCLR; /**< Bus Error Clear */ __I uint32_t _RESERVED1[300];/**< Reserved */ |