Replaced custom register bitfield macros by TivaWare bitfield macros.

2 files changed, 14 insertions, 171 deletions

diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
index 7203e74..2e3b213 100644
--- a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
@@ -143,7 +143,7 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config)
   HWREG(u + UART_O_CTL)  = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
 
   /* Enable interrupts.*/
-  HWREG(u + UART_O_IM)   = TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM;
+  HWREG(u + UART_O_IM)   = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM;
 }
 
 /**
@@ -153,7 +153,7 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config)
  */
 static void uart_deinit(uint32_t u)
 {
-  HWREG(u + UART_O_CTL) &= ~TIVA_CTL_UARTEN;
+  HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
 }
 
 /**
@@ -166,13 +166,13 @@ static void set_error(SerialDriver *sdp, uint16_t err)
 {
   eventflags_t sts = 0;
   
-  if (err & TIVA_MIS_FEMIS)
+  if (err & UART_MIS_FEMIS)
     sts |= SD_FRAMING_ERROR;
-  if (err & TIVA_MIS_PEMIS)
+  if (err & UART_MIS_PEMIS)
     sts |= SD_PARITY_ERROR;
-  if (err & TIVA_MIS_BEMIS)
+  if (err & UART_MIS_BEMIS)
     sts |= SD_BREAK_DETECTED;
-  if (err & TIVA_MIS_OEMIS)
+  if (err & UART_MIS_OEMIS)
     sts |= SD_OVERRUN_ERROR;
   osalSysLockFromISR();
   chnAddFlagsI(sdp, sts);
@@ -195,17 +195,17 @@ static void serial_serve_interrupt(SerialDriver *sdp)
   
   HWREG(u + UART_O_ICR) = mis;		/* clear interrupts */
 
-  if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) {
+  if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) {
     set_error(sdp, mis);
   }
 
-  if ((mis & TIVA_MIS_RXMIS) || (mis &  TIVA_MIS_RTMIS)) {
+  if ((mis & UART_MIS_RXMIS) || (mis &  UART_MIS_RTMIS)) {
     osalSysLockFromISR();
     if (iqIsEmptyI(&sdp->iqueue)) {
       chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
     }
     osalSysUnlockFromISR();
-    while ((HWREG(u + UART_O_FR) & TIVA_FR_RXFE) == 0) {
+    while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) {
       osalSysLockFromISR();
       if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) {
         chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
@@ -214,14 +214,14 @@ static void serial_serve_interrupt(SerialDriver *sdp)
     }
   }
 
-  if (mis & TIVA_MIS_TXMIS) {
-    while ((HWREG(u + UART_O_FR) & TIVA_FR_TXFF) == 0) {
+  if (mis & UART_MIS_TXMIS) {
+    while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
       msg_t b;
       osalSysLockFromISR();
       b = oqGetI(&sdp->oqueue);
       osalSysUnlockFromISR();
       if (b < Q_OK) {
-        HWREG(u + UART_O_IM) &= ~TIVA_IM_TXIM;
+        HWREG(u + UART_O_IM) &= ~UART_IM_TXIM;
         osalSysLockFromISR();
         chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
         osalSysUnlockFromISR();
@@ -239,7 +239,7 @@ static void fifo_load(SerialDriver *sdp)
 {
   uint32_t u = sdp->uart;
 
-  while ((HWREG(u + UART_O_FR) & TIVA_FR_TXFF) == 0) {
+  while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) {
     msg_t b = oqGetI(&sdp->oqueue);
     if (b < Q_OK) {
       chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
@@ -248,7 +248,7 @@ static void fifo_load(SerialDriver *sdp)
     HWREG(u + UART_O_DR) = b;
   }
 
-  HWREG(u + UART_O_IM) |= TIVA_IM_TXIM;   /* transmit interrupt enable */
+  HWREG(u + UART_O_IM) |= UART_IM_TXIM;   /* transmit interrupt enable */
 }
 
 /**
diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
index 49239fb..d52828c 100644
--- a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
+++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h
@@ -31,163 +31,6 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
-/**
- * @name    FR register bits definitions
- * @{
- */
-
-#define TIVA_FR_CTS         (1 << 0)
-
-#define TIVA_FR_BUSY        (1 << 3)
-
-#define TIVA_FR_RXFE        (1 << 4)
-
-#define TIVA_FR_TXFF        (1 << 5)
-
-#define TIVA_FR_RXFF        (1 << 6)
-
-#define TIVA_FR_TXFE        (1 << 7)
-
-/**
- * @}
- */
-
-/**
- * @name    LCRH register bits definitions
- * @{
- */
-
-#define TIVA_LCRH_BRK       (1 << 0)
-
-#define TIVA_LCRH_PEN       (1 << 1)
-
-#define TIVA_LCRH_EPS       (1 << 2)
-
-#define TIVA_LCRH_STP2      (1 << 3)
-
-#define TIVA_LCRH_FEN       (1 << 4)
-
-#define TIVA_LCRH_WLEN_MASK (3 << 5)
-#define TIVA_LCRH_WLEN_5    (0 << 5)
-#define TIVA_LCRH_WLEN_6    (1 << 5)
-#define TIVA_LCRH_WLEN_7    (2 << 5)
-#define TIVA_LCRH_WLEN_8    (3 << 5)
-
-#define TIVA_LCRH_SPS       (1 << 7)
-
-/**
- * @}
- */
- 
-/**
- * @name    CTL register bits definitions
- * @{
- */
-
-#define TIVA_CTL_UARTEN     (1 << 0)
-
-#define TIVA_CTL_SIREN      (1 << 1)
-
-#define TIVA_CTL_SIRLP      (1 << 2)
-
-#define TIVA_CTL_SMART      (1 << 3)
-
-#define TIVA_CTL_EOT        (1 << 4)
-
-#define TIVA_CTL_HSE        (1 << 5)
-
-#define TIVA_CTL_LBE        (1 << 7)
-
-#define TIVA_CTL_TXE        (1 << 8)
-
-#define TIVA_CTL_RXE        (1 << 9)
-
-#define TIVA_CTL_RTS        (1 << 11)
-
-#define TIVA_CTL_RTSEN      (1 << 14)
-
-#define TIVA_CTL_CTSEN      (1 << 15)
-
-/**
- * @}
- */
-
-/**
- * @name    IFLS register bits definitions
- * @{
- */
-
-#define TIVA_IFLS_TXIFLSEL_MASK     (7 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_8_F    (0 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_4_F    (1 << 0)
-#define TIVA_IFLS_TXIFLSEL_1_2_F    (2 << 0)
-#define TIVA_IFLS_TXIFLSEL_3_4_F    (3 << 0)
-#define TIVA_IFLS_TXIFLSEL_7_8_F    (4 << 0)
-
-#define TIVA_IFLS_RXIFLSEL_MASK     (7 << 3)
-#define TIVA_IFLS_RXIFLSEL_7_8_E    (0 << 3)
-#define TIVA_IFLS_RXIFLSEL_3_4_E    (1 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_2_E    (2 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_4_E    (3 << 3)
-#define TIVA_IFLS_RXIFLSEL_1_8_E    (4 << 3)
-
-/**
- * @}
- */
-
-/**
- * @name    MIS register bits definitions
- * @{
- */
-
-#define TIVA_MIS_CTSMIS             (1 << 1)
-
-#define TIVA_MIS_RXMIS              (1 << 4)
-
-#define TIVA_MIS_TXMIS              (1 << 5)
-
-#define TIVA_MIS_RTMIS              (1 << 6)
-
-#define TIVA_MIS_FEMIS              (1 << 7)
-
-#define TIVA_MIS_PEMIS              (1 << 8)
-
-#define TIVA_MIS_BEMIS              (1 << 9)
-
-#define TIVA_MIS_OEMIS              (1 << 10)
-
-#define TIVA_MIS_9BITMIS            (1 << 12)
-
-/**
- * @}
- */
-
-/**
- * @name    IM register bits definitions
- * @{
- */
-
-#define TIVA_IM_CTSIM               (1 << 1)
-
-#define TIVA_IM_RXIM                (1 << 4)
-
-#define TIVA_IM_TXIM                (1 << 5)
-
-#define TIVA_IM_RTIM                (1 << 6)
-
-#define TIVA_IM_FEIM                (1 << 7)
-
-#define TIVA_IM_PEIM                (1 << 8)
-
-#define TIVA_IM_BEIM                (1 << 9)
-
-#define TIVA_IM_OEIM                (1 << 10)
-
-#define TIVA_IM_9BITIM              (1 << 12)
-
-/**
- * @}
- */
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/