Replaced custom register bitfield macros by TivaWare bitfield macros.

2 files changed, 32 insertions, 79 deletions

diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
index 3b49d6c..cf70dca 100644
--- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
@@ -30,6 +30,33 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+// interrupt states
+#define STATE_IDLE          0
+#define STATE_WRITE_NEXT    1
+#define STATE_WRITE_FINAL   2
+#define STATE_WAIT_ACK      3
+#define STATE_SEND_ACK      4
+#define STATE_READ_ONE      5
+#define STATE_READ_FIRST    6
+#define STATE_READ_NEXT     7
+#define STATE_READ_FINAL    8
+#define STATE_READ_WAIT     9
+
+#define TIVA_I2C_SIGNLE_SEND                (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_START           (I2C_MCS_RUN | I2C_MCS_START)
+#define TIVA_I2C_BURST_SEND_CONTINUE        (I2C_MCS_RUN)
+#define TIVA_I2C_BURST_SEND_FINISH          (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_STOP            (I2C_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_ERROR_STOP      (I2C_MCS_STOP)
+
+#define TIVA_I2C_SINGLE_RECEIVE             (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_START        (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_CONTINUE     (I2C_MCS_RUN | I2C_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_FINISH       (I2C_MCS_RUN | I2C_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP   (I2C_MCS_STOP)
+
+#define MTPR_VALUE          ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
+
 /*===========================================================================*/
 /* Driver constants.                                                         */
 /*===========================================================================*/
@@ -134,10 +161,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
   // read interrupt status
   status = HWREG(i2c + I2C_O_MCS);
 
-  if (status & TIVA_MCS_ERROR) {
+  if (status & I2C_MCS_ERROR) {
     i2cp->errors |= I2C_BUS_ERROR;
   }
-  if (status & TIVA_MCS_ARBLST) {
+  if (status & I2C_MCS_ARBLST) {
     i2cp->errors |= I2C_ARBITRATION_LOST;
   }
 
@@ -760,7 +787,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the bus is not busy then the operation can continue, note, the
        loop is exited in the locked state.*/
-    if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0)
+    if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
       break;
 
     /* If the system time went outside the allowed window then a timeout
@@ -834,7 +861,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the bus is not busy then the operation can continue, note, the
        loop is exited in the locked state.*/
-    if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0)
+    if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0)
       break;
 
     /* If the system time went outside the allowed window then a timeout
@@ -852,7 +879,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
   HWREG(i2c + I2C_O_MSA) = i2cp->addr;
 
   /* enable interrupts */
-  HWREG(i2c + I2C_O_MIMR) = TIVA_MIMR_IM;
+  HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM;
 
   /* put data in register */
   HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
index 09a062f..4eabda8 100644
--- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h
@@ -31,80 +31,6 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
-#define MTPR_VALUE          ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
-
-#define TIVA_MSA_RS         (1 << 0)
-#define TIVA_MSA_SA         (127 << 1)
-
-#define TIVA_MCS_BUSY       (1 << 0)
-#define TIVA_MCS_ERROR      (1 << 1)
-#define TIVA_MCS_ADRACK     (1 << 2)
-#define TIVA_MCS_DATACK     (1 << 3)
-#define TIVA_MCS_ARBLST     (1 << 4)
-#define TIVA_MCS_IDLE       (1 << 5)
-#define TIVA_MCS_BUSBSY     (1 << 6)
-#define TIVA_MCS_CLKTO      (1 << 7)
-
-#define TIVA_MCS_RUN        (1 << 0)
-#define TIVA_MCS_START      (1 << 1)
-#define TIVA_MCS_STOP       (1 << 2)
-#define TIVA_MCS_ACK        (1 << 3)
-#define TIVA_MCS_HS         (1 << 4)
-
-#define TIVA_I2C_SIGNLE_SEND                (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_START           (TIVA_MCS_RUN | TIVA_MCS_START)
-#define TIVA_I2C_BURST_SEND_CONTINUE        (TIVA_MCS_RUN)
-#define TIVA_I2C_BURST_SEND_FINISH          (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_STOP            (TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_SEND_ERROR_STOP      (TIVA_MCS_STOP)
-
-#define TIVA_I2C_SINGLE_RECEIVE             (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_START        (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_CONTINUE     (TIVA_MCS_RUN | TIVA_MCS_ACK)
-#define TIVA_I2C_BURST_RECEIVE_FINISH       (TIVA_MCS_RUN | TIVA_MCS_STOP)
-#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP   (TIVA_MCS_STOP)
-
-#define TIVA_MDR_DATA       (255 << 0)
-
-#define TIVA_MTPR_TPR       (127 << 0)
-#define TIVA_MTPR_HS        (1 << 7)
-
-#define TIVA_MIMR_IM        (1 << 0)
-#define TIVA_MIMR_CLKIM     (1 << 1)
-
-#define TIVA_MRIS_RIS       (1 << 0)
-#define TIVA_MRIS_CLKRIS    (1 << 1)
-
-#define TIVA_MMIS_MIS       (1 << 0)
-#define TIVA_MMIS_CLKMIS    (1 << 1)
-
-#define TIVA_MICR_IC        (1 << 0)
-#define TIVA_MICR_CLKIC     (1 << 1)
-
-#define TIVA_MCR_LPBK       (1 << 0)
-#define TIVA_MCR_MFE        (1 << 4)
-#define TIVA_MCR_SFE        (1 << 5)
-#define TIVA_MCR_GFE        (1 << 6)
-
-#define TIVA_MCLKOCNT_CNTL  (255 << 0)
-
-#define TIVA_MBMON_SCL      (1 << 0)
-#define TIVA_MBMON_SDA      (1 << 1)
-
-#define TIVA_MCR2_GFPW      (7 << 4)
-
-// interrupt states
-#define STATE_IDLE          0
-#define STATE_WRITE_NEXT    1
-#define STATE_WRITE_FINAL   2
-#define STATE_WAIT_ACK      3
-#define STATE_SEND_ACK      4
-#define STATE_READ_ONE      5
-#define STATE_READ_FIRST    6
-#define STATE_READ_NEXT     7
-#define STATE_READ_FINAL    8
-#define STATE_READ_WAIT     9
-
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/