diff options
| author | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-08 20:14:13 +0100 |
|---|---|---|
| committer | Fabien Poussin <fabien.poussin@gmail.com> | 2018-03-08 20:14:13 +0100 |
| commit | ae7a4d40b84d8afc999691577210696f16e682f6 (patch) | |
| tree | bc7d2dbfeeb6961018da845454232a6d641fcc04 /os/hal/ports/STM32 | |
| parent | 32f792087ac05ef8e2c1bafbe5fdaf0f44c302f7 (diff) | |
| download | ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.tar.gz ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.tar.bz2 ChibiOS-Contrib-ae7a4d40b84d8afc999691577210696f16e682f6.zip | |
Fixes for STM32F0 testhal
Diffstat (limited to 'os/hal/ports/STM32')
| -rwxr-xr-x | os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c | 24 |
2 files changed, 14 insertions, 14 deletions
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index a2cf026..701b87d 100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -155,7 +155,7 @@ void crc_lld_start(CRCDriver *crcp) { if (crcp->config == NULL) crcp->config = &default_config; - rccEnableCRC(FALSE); + rccEnableCRC(); #if STM32_CRC_PROGRAMMABLE == TRUE crcp->crc->INIT = crcp->config->initial_val; @@ -234,7 +234,7 @@ void crc_lld_stop(CRCDriver *crcp) { #else (void)crcp; #endif - rccDisableCRC(FALSE); + rccDisableCRC(); } /** diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index 6138481..cef015e 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) { /* Clock activation and timer reset.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccEnableTIM1(FALSE);
+ rccEnableTIM1();
rccResetTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccEnableTIM2(FALSE);
+ rccEnableTIM2();
rccResetTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccEnableTIM3(FALSE);
+ rccEnableTIM3();
rccResetTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccEnableTIM4(FALSE);
+ rccEnableTIM4();
rccResetTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccEnableTIM5(FALSE);
+ rccEnableTIM5();
rccResetTIM5();
}
#endif
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccEnableTIM8(FALSE);
+ rccEnableTIM8();
rccResetTIM8();
}
#endif
@@ -235,33 +235,33 @@ void qei_lld_stop(QEIDriver *qeip) { /* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
}
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
}
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