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| author | barthess <barthess@yandex.ru> | 2016-07-14 13:18:21 +0300 |
|---|---|---|
| committer | barthess <barthess@yandex.ru> | 2016-07-14 13:18:21 +0300 |
| commit | c7afdebe336e148a4e05453324fbbbcf1bb5a399 (patch) | |
| tree | eaf42d4a6cb00ad0efc5f736a150066ddf6d5518 /os/hal/ports/STM32/LLD | |
| parent | 097a59799a39eb5889d241537d024fd8f9d6a0ab (diff) | |
| download | ChibiOS-Contrib-c7afdebe336e148a4e05453324fbbbcf1bb5a399.tar.gz ChibiOS-Contrib-c7afdebe336e148a4e05453324fbbbcf1bb5a399.tar.bz2 ChibiOS-Contrib-c7afdebe336e148a4e05453324fbbbcf1bb5a399.zip | |
Added room for STM32F7x
Diffstat (limited to 'os/hal/ports/STM32/LLD')
| -rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h | 20 |
2 files changed, 17 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index 8b1082c..40ad05c 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -96,7 +96,8 @@ void fsmc_init(void) { #endif #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) #if STM32_USE_FSMC_SDRAM FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index 7889b01..f9d8a60 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -35,7 +35,8 @@ * (Re)define if needed base address constants supplied in ST's CMSIS */ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) #if !defined(FSMC_Bank1_R_BASE) #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #endif @@ -80,7 +81,8 @@ #define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) #define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) #endif @@ -157,7 +159,8 @@ typedef struct { } FSMC_SRAM_NOR_TypeDef; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) typedef struct { __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ @@ -205,7 +208,8 @@ typedef struct { #define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) #define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) #define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) #else #define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) @@ -221,6 +225,11 @@ typedef struct { #define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) #define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) #define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) +#endif /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -303,7 +312,8 @@ struct FSMCDriver { FSMC_NAND_TypeDef *nand2; #endif #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) #if STM32_USE_FSMC_SDRAM FSMC_SDRAM_TypeDef *sdram; #endif |