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authorStephane D'Alu <sdalu@sdalu.com>2016-02-06 02:15:26 +0100
committerStephane D'Alu <sdalu@sdalu.com>2016-02-06 02:15:26 +0100
commit90800edb90ad0fcf8e7f53e5d32a4df9a0c62c6c (patch)
treedc12113f25fd8717932e2386aff7ba42cc2399a6 /os/hal/ports/NRF51/NRF51822/st_lld.c
parent3c6756556d46ba9349e0b9526c9f5f83e111a080 (diff)
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fixed tickless for RTC, removed it for TIMER
Diffstat (limited to 'os/hal/ports/NRF51/NRF51822/st_lld.c')
-rw-r--r--os/hal/ports/NRF51/NRF51822/st_lld.c48
1 files changed, 1 insertions, 47 deletions
diff --git a/os/hal/ports/NRF51/NRF51822/st_lld.c b/os/hal/ports/NRF51/NRF51822/st_lld.c
index 51f942b..e3ae3f2 100644
--- a/os/hal/ports/NRF51/NRF51822/st_lld.c
+++ b/os/hal/ports/NRF51/NRF51822/st_lld.c
@@ -129,30 +129,6 @@ OSAL_IRQ_HANDLER(Vector6C) {
OSAL_IRQ_EPILOGUE();
}
#endif
-
-#if (NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_TIMER)
-/**
- * @brief System Timer vector. (TIMER0)
- * @details This interrupt is used for freerunning mode (tick-less)
- * if selected with NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_TIMER
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector60) {
-
- OSAL_IRQ_PROLOGUE();
-
- /* Clear timer compare event */
- if (NRF_TIMER0->EVENTS_COMPARE[0] != 0)
- NRF_TIMER0->EVENTS_COMPARE[0] = 0;
-
- osalSysLockFromISR();
- osalOsTimerHandlerI();
- osalSysUnlockFromISR();
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
#endif
/*===========================================================================*/
@@ -172,34 +148,12 @@ void st_lld_init(void) {
NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
+ NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
/* Start timer */
nvicEnableVector(RTC0_IRQn, 8);
NRF_RTC0->TASKS_START = 1;
#endif
-
-#if (NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_TIMER)
- NRF_TIMER0->TASKS_CLEAR = 1;
-
- /*
- * Using 32-bit mode with prescaler 16 configures this
- * timer with a 1MHz clock.
- */
- NRF_TIMER0->BITMODE = 3;
- NRF_TIMER0->PRESCALER = 4;
-
- /*
- * Configure timer 0 compare capture 1 to generate interrupt
- * for overflow according to ST_OVERFLOW_VALUE
- */
- NRF_TIMER0->CC[0] = (1000000 / OSAL_ST_FREQUENCY) - 1;
- NRF_TIMER0->SHORTS = 1;
- NRF_TIMER0->INTENSET = 0x10000;
-
- /* Start timer */
- nvicEnableVector(TIMER0_IRQn, 8);
- NRF_TIMER0->TASKS_START = 1;
-#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC