diff options
| author | Michael Walker <walkerstop@gmail.com> | 2018-05-02 03:33:23 -0700 |
|---|---|---|
| committer | Michael Walker <walkerstop@gmail.com> | 2018-05-02 03:33:23 -0700 |
| commit | 6d879f58f5b56eda3330aa6e7f8382f441adecf4 (patch) | |
| tree | dad3f1f3b6ac3927484ee22002a947662a8a0173 /os/hal/ports/KINETIS/LLD | |
| parent | 4e9f077fb10255dced1da4d5d2ad9f8ae41442a2 (diff) | |
| parent | d4d384557df0e8e7a8071553448b0c42849f98c0 (diff) | |
| download | ChibiOS-Contrib-6d879f58f5b56eda3330aa6e7f8382f441adecf4.tar.gz ChibiOS-Contrib-6d879f58f5b56eda3330aa6e7f8382f441adecf4.tar.bz2 ChibiOS-Contrib-6d879f58f5b56eda3330aa6e7f8382f441adecf4.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'os/hal/ports/KINETIS/LLD')
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_i2c_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_sdc_lld.c | 977 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_sdc_lld.h | 202 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_serial_lld.c | 251 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_serial_lld.h | 69 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 57 | ||||
| -rw-r--r-- | os/hal/ports/KINETIS/LLD/hal_usb_lld.h | 23 |
7 files changed, 1492 insertions, 89 deletions
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index c6b3d11..a005c32 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -442,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* wait until the bus is released */
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
- end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+ end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
while(true) {
osalSysLock();
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c new file mode 100644 index 0000000..1b19a90 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c @@ -0,0 +1,977 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017..2018 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.c
+ * @brief Kinetis SDC subsystem low level driver.
+ *
+ * This driver provides a single SDC driver based on the Kinetis
+ * "Secured Digital Host Controller (SDHC)" peripheral.
+ *
+ * In order to use this driver, other peripherals must also be configured:
+ *
+ * The MPU must either be disabled (CESR=0), or it must be configured
+ * to allow the SDHC peripheral DMA access to any data buffers (read
+ * or write).
+ *
+ * The SDHC signals must be routed to the desired pins, and pullups/pulldowns
+ * configured. + *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_mmcsd.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* We configure the SDHC block to use the system clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+
+#ifndef KINETIS_SDHC_PRIORITY
+#define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */
+#endif
+
+/* The DTOC value (data timeout counter) controls how long the SDHC
+ will wait for a data transfer before indicating a timeout to
+ us. The card can tell us how long that should be, but various SDHC
+ documentation suggests that we should always allow around 500 msec
+ even if the card says it will finish sooner. This only comes into
+ play if there's a malfunction or something, so it's not critical to
+ get it exactly right.
+
+ It controls the ratio between the SDCLK frequency and the
+ timeout, so we have a different DTOCV for each bus clock
+ frequency.
+*/
+#define DTOCV_300ms_400kHz 4 /* 4 -> 2^17 -> 328 msec */
+#define DTOCV_700ms_25MHz 11 /* 11 -> 2^24 -> 671 msec */
+#define DTOCV_700ms_50MHz 12 /* 12 -> 2^25 -> 671 msec */
+
+#if 0
+#define TRACE(t, val) chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))
+#define TRACEI(t, val) chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))
+#else
+#define TRACE(t, val)
+#define TRACEI(t, val)
+#endif
+
+#define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )
+
+/* Error bits from the SD / MMC Card Status response word. */
+/* TODO: These really belong in a HLD, not here. */
+#define MMC_ERR_OUT_OF_RANGE (1U << 31)
+#define MMC_ERR_ADDRESS (1U << 30)
+#define MMC_ERR_BLOCK_LEN (1U << 29)
+#define MMC_ERR_ERASE_SEQ (1U << 28)
+#define MMC_ERR_ERASE_PARAM (1U << 27)
+#define MMC_ERR_WP (1U << 26)
+#define MMC_ERR_CARD_IS_LOCKED (1U << 25)
+#define MMC_ERR_LOCK_UNLOCK_FAILED (1U << 24)
+#define MMC_ERR_COM_CRC_ERROR (1U << 23)
+#define MMC_ERR_ILLEGAL_COMMAND (1U << 22)
+#define MMC_ERR_CARD_ECC_FAILED (1U << 21)
+#define MMC_ERR_CARD_CONTROLLER (1U << 20)
+#define MMC_ERR_ERROR (1U << 19)
+#define MMC_ERR_CSD_OVERWRITE (1U << 16)
+#define MMC_ERR_AKE_SEQ (1U << 3)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SDCD1 driver identifier.
+ */
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+SDCDriver SDCD1;
+#else
+#error HAL_USE_SDC is true but PLATFORM_SDC_USE_SDC1 is false
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void recover_after_botched_transfer(SDCDriver *);
+static msg_t wait_interrupt(SDCDriver *, uint32_t);
+static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_t);
+
+/**
+ * Compute the SDCLKFS and DVS values for a given SDCLK divisor.
+ *
+ * Note that in the current code, this function is always called with
+ * a constant argument (there are only a handful of valid SDCLK
+ * frequencies), and so GCC computes the results at compile time and
+ * does not actually emit this function into the output at all unless
+ * you're compiling with optimizations turned off.
+ *
+ * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY
+ * that is not a compile-time constant, this function would get emitted.
+ */
+static uint32_t divisor_settings(unsigned divisor)
+{
+ /* First, handle all the special cases */
+ if (divisor <= 1) {
+ /* Pass through */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(0);
+ }
+ if (divisor <= 16 && (divisor & 0x01)) {
+ /* Disable the prescaler, just use the divider. */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(divisor - 1);
+ }
+ if (divisor <= 32 && !(divisor & 0x01)) {
+ /* Prescale by 2, but do the rest with the divider */
+ return SDHC_SYSCTL_SDCLKFS(0x01) | SDHC_SYSCTL_DVS((divisor >> 1) - 1);
+ }
+ if (divisor >= 0x1000) {
+ /* It's not possible to divide by more than 2^12. If we're asked to,
+ just do the best we can. */
+ return SDHC_SYSCTL_SDCLKFS(0x80) | SDHC_SYSCTL_DVS(0xF);
+ }
+
+ /* The bit position in SDCLKFS provides a power-of-two prescale
+ factor, and the four bits in DVS allow division by up to 16
+ (division by DVS+1). We want to approximate `divisor` using these
+ terms, but we want to round up --- it's OK to run the card a
+ little bit too slow, but not OK to run it a little bit too
+ fast. */
+
+ unsigned shift = (8 * sizeof(unsigned int) - 4) - __builtin_clz(divisor);
+
+ /* Shift the divisor value right so that it only occupies the four
+ lowest bits. Subtract one because that's how the DVS circuit
+ works. Add one if we shifted any 1-bits off the bottom, so that
+ we always round up. */
+ unsigned dvs = (divisor >> shift) - ((divisor & ((1 << shift)-1))? 0 : 1);
+
+ return SDHC_SYSCTL_SDCLKFS(1 << (shift-1)) | SDHC_SYSCTL_DVS(dvs);
+}
+
+/**
+ * @brief Enable the SDHC clock when stable.
+ *
+ * Waits for the clock divider in the SDHC block to stabilize, then
+ * enables the SD clock.
+ */
+static void enable_clock_when_stable(uint32_t new_sysctl)
+{
+ SDHC->SYSCTL = new_sysctl;
+
+ /* Wait for clock divider to stabilize */
+ while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ /* Restart the clock */
+ SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;
+}
+
+/**
+ * Translate error bits from a CMD transaction to the HAL's error flag set.
+ */
+static sdcflags_t translate_cmd_error(uint32_t status) {
+ /* Translate the failure into the flags understood by the top half */
+
+ sdcflags_t errors = 0;
+
+ if (status & SDHC_IRQSTAT_CTOE || !(status & SDHC_IRQSTAT_CC)) {
+ errors |= SDC_COMMAND_TIMEOUT;
+ }
+ if (status & SDHC_IRQSTAT_CCE) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ /* If CTOE and CCE are both set, this indicates that the Kinetis
+ SDHC peripheral has detected a CMD line conflict in a
+ multi-master scenario. There's no specific code for that, so just
+ pass it through as a combined timeout+CRC failure. */
+
+ /* Translate any other framing and protocol errors into CRC errors. */
+ if (status & ~(SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE|SDHC_IRQSTAT_CC)) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ return errors;
+}
+
+/**
+ * Translate error bits from a card's R1 response word into the HAL's
+ * error flag set.
+ *
+ * This function should probably be in the HLD, not here.
+ */
+static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {
+ sdcflags_t errors = 0;
+
+ cardstatus &= MMCSD_R1_ERROR_MASK;
+
+ if (cardstatus & MMC_ERR_COM_CRC_ERROR)
+ errors |= SDC_CMD_CRC_ERROR;
+
+ if (cardstatus & MMC_ERR_CARD_ECC_FAILED)
+ errors |= SDC_DATA_CRC_ERROR;
+
+ /* TODO: Extend the HLD error codes at least enough to distinguish
+ between invalid command/parameter errors (card is OK, but
+ retrying w/o change won't help) and other errors */
+ if (cardstatus & ~(MMC_ERR_COM_CRC_ERROR|MMC_ERR_CARD_ECC_FAILED))
+ errors |= SDC_UNHANDLED_ERROR;
+
+ return errors;
+}
+
+/**
+ * @brief Perform one CMD transaction on the SD bus.
+ */
+static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
+ /* SDCLKEN (CMD clock enabled) should be true;
+ * SDSTB (clock stable) should be true;
+ * CIHB (command inhibit / busy) should be false */
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");
+ osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");
+ osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);
+ osalDbgCheck((SDHC->IRQSTAT & (SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC)) == 0);
+
+ /* This initiates the CMD transaction */
+ TRACE(1, cmd);
+ SDHC->XFERTYP = cmd;
+
+ uint32_t events =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+ wait_interrupt(sdcp, SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC);
+ uint32_t status = SDHC->IRQSTAT & events;
+
+ /* These bits are write-1-to-clear (w1c) */
+ SDHC->IRQSTAT = status;
+
+ /* In the normal case, the CC (command complete) bit is set but none
+ of the others are */
+ if (status == SDHC_IRQSTAT_CC)
+ return HAL_SUCCESS;
+
+ /* Translate the failure into the flags understood by the top half */
+ sdcp->errors |= translate_cmd_error(status);
+
+ TRACE(9, SDHC->PRSSTAT);
+
+ /* Issue a reset to the CMD portion of the SDHC peripheral to clear the
+ error bits and enable subsequent commands */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Perform one data transaction on the SD bus.
+ */
+static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
+
+ osalDbgCheck(cmd & SDHC_XFERTYP_DPSEL);
+ osalDbgCheck(cmd & SDHC_XFERTYP_DMAEN);
+
+ const uint32_t cmd_end_bits =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+
+ const uint32_t transfer_end_bits =
+ SDHC_IRQSTAT_DMAE | SDHC_IRQSTAT_AC12E | SDHC_IRQSTAT_DEBE |
+ SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_TC;
+
+ TRACE(3, cmd);
+
+ osalSysLock();
+ osalDbgCheck(sdcp->thread == NULL);
+
+ /* Clear anything pending from an earlier transfer */
+ SDHC->IRQSTAT = cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT;
+
+ /* Enable interrupts on completions or failures */
+ uint32_t old_staten = SDHC->IRQSTATEN;
+ SDHC->IRQSTATEN = (old_staten & ~(SDHC_IRQSTAT_BRR|SDHC_IRQSTAT_BWR)) | (cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT);
+ SDHC->IRQSIGEN = SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;
+
+ /* Start the transfer */
+ SDHC->XFERTYP = cmd;
+
+ /* Await an interrupt */
+ osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+
+ /* Retrieve the flags and clear them */
+ uint32_t cmdstat = SDHC->IRQSTAT & cmd_end_bits;
+ SDHC->IRQSTAT = cmdstat;
+ TRACE(2, cmdstat);
+
+ /* If the command failed, the transfer won't happen */
+ if (cmdstat != SDHC_IRQSTAT_CC) {
+ /* The command couldn't be sent, or wasn't acknowledged */
+ sdcp->errors |= translate_cmd_error(cmdstat);
+
+ /* Clear the error status */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ if (cmdstat == (SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE)) {
+ /* A CMD-line conflict is unlikely, but doesn't require further recovery */
+ } else {
+ /* For most error situations, we don't know whether the command
+ failed to send or we got line noise while receiving. Make sure
+ we're in a sane state by resetting the connection. */
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ uint32_t cmdresp = SDHC->CMDRSP[0];
+ TRACE(11, cmdresp);
+ if (cmdresp & MMCSD_R1_ERROR_MASK) {
+ /* The command was sent, and the card responded with an error indication */
+ sdcp->errors |= translate_mmcsd_error(cmdresp);
+ return HAL_FAILED;
+ }
+
+ /* Check for end of data transfer phase */
+ uint32_t datastat;
+ for (;;) {
+ datastat = SDHC->IRQSTAT & (transfer_end_bits | SDHC_IRQSTAT_DINT);
+ if (datastat & transfer_end_bits)
+ break;
+ wait_interrupt(sdcp, transfer_end_bits);
+ }
+ TRACE(6, datastat);
+ SDHC->IRQSTAT = datastat;
+
+ /* Handle data transfer errors */
+ if ((datastat & ~(SDHC_IRQSTAT_DINT)) != SDHC_IRQSTAT_TC) {
+ bool should_cancel = false;
+
+ /* Data phase errors */
+ if (datastat & (SDHC_IRQSTAT_DCE|SDHC_IRQSTAT_DEBE)) {
+ sdcp->errors |= SDC_DATA_CRC_ERROR;
+ should_cancel = true;
+ }
+ if (datastat & SDHC_IRQSTAT_DTOE) {
+ sdcp->errors |= SDC_DATA_TIMEOUT;
+ should_cancel = true;
+ }
+
+ /* Internal DMA error */
+ if (datastat & SDHC_IRQSTAT_DMAE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ if (!(datastat & SDHC_IRQSTAT_TC))
+ should_cancel = true;
+ }
+
+ if (datastat & SDHC_IRQSTAT_AC12E) {
+ uint32_t cmd12error = SDHC->AC12ERR;
+
+ /* We don't know if CMD12 was successfully executed */
+ should_cancel = true;
+
+ if (cmd12error & SDHC_AC12ERR_AC12NE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ } else {
+ if (cmd12error & SDHC_AC12ERR_AC12TOE)
+ sdcp->errors |= SDC_COMMAND_TIMEOUT;
+ if (cmd12error & (SDHC_AC12ERR_AC12CE|SDHC_AC12ERR_AC12EBE))
+ sdcp->errors |= SDC_CMD_CRC_ERROR;
+ }
+ }
+
+ if (should_cancel) {
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ /* For a read transfer, make sure the DMA has finished transferring
+ * to host memory. (For a write transfer, the DMA necessarily finishes
+ * before the transfer does, so we don't need to wait for it
+ * specially.) */
+ if (!(datastat & SDHC_IRQSTAT_DINT)) {
+ for(;;) {
+ datastat = SDHC->IRQSTAT & (SDHC_IRQSTAT_DINT|SDHC_IRQSTAT_DMAE);
+ if (datastat) {
+ SDHC->IRQSTAT = datastat;
+ TRACE(7, datastat);
+ break;
+ }
+ /* ...?? */
+ }
+ }
+
+ SDHC->IRQSTATEN = old_staten;
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait for an interrupt from the SDHC peripheral.
+ *
+ * @param[in] mask Bits to enable in IRQSIGEN.
+ *
+ * @return MSG_OK
+ */
+static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {
+ osalSysLock();
+ SDHC->IRQSIGEN = mask;
+ msg_t wakeup = osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+ return wakeup;
+}
+
+static void recover_after_botched_transfer(SDCDriver *sdcp) {
+
+ /* Query the card state */
+ uint32_t cardstatus;
+ if (sdc_lld_send_cmd_short_crc(sdcp,
+ MMCSD_CMD_SEND_STATUS,
+ sdcp->rca, &cardstatus) == HAL_SUCCESS) {
+ sdcp->errors |= translate_mmcsd_error(cardstatus);
+ uint32_t state = MMCSD_R1_STS(cardstatus);
+ if (state == MMCSD_STS_DATA) {
+
+ /* Send a CMD12 to make sure the card isn't still transferring anything */
+ SDHC->CMDARG = 0;
+ send_and_wait_cmd(sdcp,
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_STOP_TRANSMISSION) |
+ SDHC_XFERTYP_CMDTYP_ABORT |
+ /* TODO: Should we set CICEN and CCCEN here? */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b);
+ }
+ }
+
+ /* And reset the data block of the SDHC peripheral */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;
+}
+
+/**
+ * @brief Perform one data transfer command
+ *
+ * Sends a command to the card and waits for the corresponding data transfer
+ * (either a read or write) to complete.
+ */
+static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
+ uintptr_t buf, uint32_t n,
+ uint32_t cmdx) {
+
+ osalDbgCheck(n > 0);
+ osalDbgCheck((buf & 0x03) == 0); /* Must be 32-bit aligned */
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ /* We always operate in terms of 512-byte blocks; the upper-layer
+ driver doesn't change the block size. The SDHC spec suggests that
+ only low-capacity cards support block sizes other than 512 bytes
+ anyway (SDHC "Physical Layer Simplified Specification" ver 6.0) */
+
+ if (sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) {
+ SDHC->CMDARG = startblk;
+ } else {
+ SDHC->CMDARG = startblk * MMCSD_BLOCK_SIZE;
+ }
+
+ /* Store the DMA start address */
+ SDHC->DSADDR = buf;
+
+ uint32_t xfer;
+ /* For data transfers, we need to set some extra bits in XFERTYP according to the
+ transfer we're starting:
+ DPSEL -> enable data transfer
+ DTDSEL -> 1 for a read (card-to-host) transfer
+ MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT
+ AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer
+
+ Setting BLKCOUNT to 1 seems to be necessary even if MSBSEL+BCEN
+ is not set, despite the datasheet suggesting otherwise. I'm not
+ sure if this is a silicon bug or if I'm misunderstanding the
+ datasheet.
+ */
+ SDHC->BLKATTR =
+ SDHC_BLKATTR_BLKCNT(n) |
+ SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
+ if (n == 1) {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ } else {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_MSBSEL | SDHC_XFERTYP_BCEN | SDHC_XFERTYP_AC12EN |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ }
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SDHC_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ osalSysLockFromISR();
+
+ TRACEI(4, SDHC->IRQSTAT);
+
+ /* We disable the interrupts, and wake up the usermode task to read
+ * the flags from IRQSTAT.
+ */
+ SDHC->IRQSIGEN = 0;
+
+ osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+ osalSysUnlockFromISR();
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+#if PLATFORM_SDC_USE_SDC1 == TRUE
+ sdcObjectInit(&SDCD1);
+#endif
+}
+
+
+/**
+ * @brief Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+ if (sdcp->state == BLK_STOP) {
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |
+ SIM_SOPT2_SDHCSRC(0); /* SDHC clock source 0: Core/system clock. */
+ SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */
+
+ /* Reset the SDHC block */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTA;
+ while(SDHC->SYSCTL & SDHC_SYSCTL_RSTA) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ SDHC->IRQSIGEN = 0;
+ nvicEnableVector(SDHC_IRQn, KINETIS_SDHC_PRIORITY);
+ }
+}
+
+/**
+ * @brief Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+ if (sdcp->state != BLK_STOP) {
+ /* TODO: Should we perform a reset (RSTA) before putting the
+ peripheral to sleep? */
+
+ /* Disable the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Turn off interrupts */
+ nvicDisableVector(SDHC_IRQn);
+ SDHC->IRQSIGEN = 0;
+ SDHC->IRQSTATEN &= ~( SDHC_IRQSTATEN_CINTSEN |
+ SDHC_IRQSTATEN_CINSEN |
+ SDHC_IRQSTATEN_CRMSEN );
+
+ /* Disable the clock to the SDHC peripheral block */
+ SIM->SCGC3 &= ~( SIM_SCGC3_SDHC );
+ }
+}
+
+/**
+ * @brief Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ /* Stop the card clock (it should already be stopped) */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor and DTOCV for a 400kHz card closk */
+ uint32_t sysctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_300ms_400kHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 400000));
+
+ /* Restart the clock */
+ enable_clock_when_stable(sysctl);
+
+ /* Reset any protocol machinery; this also runs the clock for 80
+ cycles without any data bits to help initalize the card's state
+ (the Kinetis peripheral docs say that this is required after card
+ insertion or power-on, but the abridged SDHC specifications I
+ have don't seem to mention it) */
+ SDHC->SYSCTL |= SDHC_SYSCTL_INITA;
+
+ TRACE(9, SDHC->PRSSTAT);
+}
+
+/**
+ * @brief Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+
+ (void)sdcp;
+
+ /* Stop the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor */
+ uint32_t ctl;
+ switch (clk) {
+ default:
+ case SDC_CLK_25MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_25MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 25000000));
+ break;
+ case SDC_CLK_50MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_50MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 50000000));
+ break;
+ }
+
+ /* Restart the clock */
+ enable_clock_when_stable(ctl);
+}
+
+/**
+ * @brief Stops the SDIO clock.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+ (void)sdcp;
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+}
+
+/**
+ * @brief Switches the bus to 4 bit or 8 bit mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] mode bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+ (void)sdcp;
+ uint32_t proctl = SDHC->PROCTL & ~( SDHC_PROCTL_DTW_MASK );
+
+ switch (mode) {
+ case SDC_MODE_1BIT:
+ proctl |= SDHC_PROCTL_DTW_1BIT;
+ break;
+ case SDC_MODE_4BIT:
+ proctl |= SDHC_PROCTL_DTW_4BIT;
+ break;
+ case SDC_MODE_8BIT:
+ proctl |= SDHC_PROCTL_DTW_8BIT;
+ break;
+ default:
+ osalDbgAssert(false, "invalid bus mode");
+ break;
+ }
+
+ SDHC->PROCTL = proctl;
+}
+
+/**
+ * @brief Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_NONE;
+
+ send_and_wait_cmd(sdcp, xfer);
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected.
+ * @note The CRC is not verified.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=1, CCCEN=1 */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+ TRACE(11, *resp);
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (four words)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+
+ /* In response format R2 (the 136-bit or "long" response) the CRC7
+ field is valid, but the command index field is set to all 1s, so
+ we need to disable the command index check function (CICEN=0). */
+
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=1 */
+ SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_136;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ resp[0] = SDHC->CMDRSP[0];
+ resp[1] = SDHC->CMDRSP[1];
+ resp[2] = SDHC->CMDRSP[2];
+ resp[3] = SDHC->CMDRSP[3];
+
+ return waited;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] n number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_SINGLE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_MULTIPLE_BLOCK);
+ cmdx |= SDHC_XFERTYP_DTDSEL;
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Writes one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] n number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_MULTIPLE_BLOCK);
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Waits for card idle condition.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ return HAL_SUCCESS;
+}
+
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument) {
+ uintptr_t bufaddr = (uintptr_t)buf;
+
+ osalDbgCheck((bufaddr & 0x03) == 0); /* Must be 32-bit aligned */
+ osalDbgCheck(bytes > 0);
+ osalDbgCheck(bytes < 4096);
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ TRACE(5, argument);
+
+ /* Store the cmd argument and DMA start address */
+ SDHC->CMDARG = argument;
+ SDHC->DSADDR = bufaddr;
+
+ /* We're reading one block, of a (possibly) nonstandard size */
+ SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(bytes);
+
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) | /* the command */
+ SDHC_XFERTYP_DTDSEL | /* read transfer (card -> host) */
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48 |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN; /* DMA-assisted data transfer */
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return ( SDHC->PRSSTAT & SDHC_PRSSTAT_CLSL )? true : false;
+}
+
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ (void)sdcp;
+ return false;
+}
+
+#endif /* HAL_USE_SDC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h new file mode 100644 index 0000000..9f77bf6 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h @@ -0,0 +1,202 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.h
+ * @brief PLATFORM SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define SDHC_XFERTYP_CMDTYP_NORMAL SDHC_XFERTYP_CMDTYP(0)
+#define SDHC_XFERTYP_CMDTYP_SUSPEND SDHC_XFERTYP_CMDTYP(1)
+#define SDHC_XFERTYP_CMDTYP_RESUME SDHC_XFERTYP_CMDTYP(2)
+#define SDHC_XFERTYP_CMDTYP_ABORT SDHC_XFERTYP_CMDTYP(3)
+
+#define SDHC_XFERTYP_RSPTYP_NONE SDHC_XFERTYP_RSPTYP(0) /* no response */
+#define SDHC_XFERTYP_RSPTYP_136 SDHC_XFERTYP_RSPTYP(1) /* 136-bit response */
+#define SDHC_XFERTYP_RSPTYP_48 SDHC_XFERTYP_RSPTYP(2) /* 48-bit response */
+#define SDHC_XFERTYP_RSPTYP_48b SDHC_XFERTYP_RSPTYP(3) /* 48-bit plus busy */
+
+#define SDHC_PROCTL_DTW_1BIT SDHC_PROCTL_DTW(0)
+#define SDHC_PROCTL_DTW_4BIT SDHC_PROCTL_DTW(1)
+#define SDHC_PROCTL_DTW_8BIT SDHC_PROCTL_DTW(2)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief SDC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDC1 is included.
+ * @note The default is @p TRUE if HAL_USE_SDC is set.
+ */
+#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
+#define PLATFORM_SDC_USE_SDC1 TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
+} SDCConfig;
+
+/**
+ * @brief @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods \
+ _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+ _sdc_driver_methods
+};
+
+/**
+ * @brief Structure representing an SDC driver.
+ */
+struct SDCDriver {
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct SDCDriverVMT *vmt;
+ _mmcsd_block_device_data
+ /**
+ * @brief Current configuration data.
+ */
+ const SDCConfig *config;
+ /**
+ * @brief Various flags regarding the mounted card.
+ */
+ sdcmode_t cardmode;
+ /**
+ * @brief Errors flags.
+ */
+ sdcflags_t errors;
+ /**
+ * @brief Card RCA.
+ */
+ uint32_t rca;
+ /* End of the mandatory fields.*/
+
+ /* Platform specific fields */
+ thread_reference_t thread;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sdc_lld_init(void);
+ void sdc_lld_start(SDCDriver *sdcp);
+ void sdc_lld_stop(SDCDriver *sdcp);
+ void sdc_lld_start_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
+ void sdc_lld_stop_clk(SDCDriver *sdcp);
+ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC == TRUE */
+
+#endif /* HAL_SDC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c index c80cf22..c92fa5c 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+ Copyright (C) 2017 Wim Lewis
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,6 +51,18 @@ SerialDriver SD2; SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -95,33 +108,37 @@ static void serve_error_interrupt(SerialDriver *sdp) { UART_w_TypeDef *u = &(sdp->uart);
uint8_t s1 = *(u->s1_p);
- /* S1 bits are write-1-to-clear for UART0 on KL2x. */
- /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ /* Clearing on K20x, K60x, and KL2x/UART>0 is done by reading S1 and
* then reading D.*/
-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
- if(sdp == &SD1) {
- if(s1 & UARTx_S1_IDLE) {
- *(u->s1_p) |= UARTx_S1_IDLE;
- }
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
- if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- set_error(sdp, s1);
- *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
- return;
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
}
-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+}
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+static void serve_error_interrupt_uart0(void) {
+ SerialDriver *sdp = &SD1;
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
if(s1 & UARTx_S1_IDLE) {
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_IDLE;
}
if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
set_error(sdp, s1);
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
}
}
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
/**
* @brief Common IRQ handler.
@@ -161,6 +178,12 @@ static void serve_interrupt(SerialDriver *sdp) { }
}
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ serve_error_interrupt_uart0();
+ return;
+ }
+#endif
serve_error_interrupt(sdp);
}
@@ -184,29 +207,28 @@ static void preload(SerialDriver *sdp) { /**
* @brief Driver output notification.
*/
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
+static void notify(io_queue_t *qp)
{
- (void)qp;
- preload(&SD1);
+ preload(qp->q_link);
}
-#endif
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
+/**
+ * @brief Common driver initialization, except LP.
+ */
+static void sd_lld_init_driver(SerialDriver *SDn, UART_TypeDef *UARTn) {
+ /* Driver initialization.*/
+ sdObjectInit(SDn, NULL, notify);
+ SDn->uart.bdh_p = &(UARTn->BDH);
+ SDn->uart.bdl_p = &(UARTn->BDL);
+ SDn->uart.c1_p = &(UARTn->C1);
+ SDn->uart.c2_p = &(UARTn->C2);
+ SDn->uart.c3_p = &(UARTn->C3);
+ SDn->uart.c4_p = &(UARTn->C4);
+ SDn->uart.s1_p = (volatile uint8_t *)&(UARTn->S1);
+ SDn->uart.s2_p = &(UARTn->S2);
+ SDn->uart.d_p = &(UARTn->D);
+ SDn->uart.uart_p = UARTn;
}
-#endif
/**
* @brief Common UART configuration.
@@ -240,9 +262,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART0 */
-#elif defined(K20x) /* KL2x */
+#elif defined(K20x) || defined(K60x) /* KL2x */
- /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */
#if KINETIS_SERIAL_USE_UART0
if(sdp == &SD1)
divisor = KINETIS_SYSCLK_FREQUENCY;
@@ -260,9 +282,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
*(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
-#if defined(K20x)
+#if defined(K20x) || defined(K60x)
*(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
-#endif /* K20x */
+#endif /* K20x, K60x */
/* Line settings. */
*(uart->c1_p) = 0;
@@ -300,12 +322,40 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#if KINETIS_HAS_SERIAL_ERROR_IRQ
#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
+#if defined(KL2x)
+ serve_error_interrupt_uart0();
+#else
serve_error_interrupt(&SD1);
+#endif
OSAL_IRQ_EPILOGUE();
}
#endif
@@ -326,6 +376,30 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
/*===========================================================================*/
@@ -341,19 +415,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART0
/* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
#if ! KINETIS_SERIAL0_IS_LPUART
- SD1.uart.bdh_p = &(UART0->BDH);
- SD1.uart.bdl_p = &(UART0->BDL);
- SD1.uart.c1_p = &(UART0->C1);
- SD1.uart.c2_p = &(UART0->C2);
- SD1.uart.c3_p = &(UART0->C3);
- SD1.uart.c4_p = &(UART0->C4);
- SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
- SD1.uart.s2_p = &(UART0->S2);
- SD1.uart.d_p = &(UART0->D);
+ sd_lld_init_driver(&SD1, UART0);
#else /* ! KINETIS_SERIAL0_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD1, NULL, notify);
SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -377,20 +443,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART1
/* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
#if ! KINETIS_SERIAL1_IS_LPUART
- SD2.uart.bdh_p = &(UART1->BDH);
- SD2.uart.bdl_p = &(UART1->BDL);
- SD2.uart.c1_p = &(UART1->C1);
- SD2.uart.c2_p = &(UART1->C2);
- SD2.uart.c3_p = &(UART1->C3);
- SD2.uart.c4_p = &(UART1->C4);
- SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
- SD2.uart.s2_p = &(UART1->S2);
- SD2.uart.d_p = &(UART1->D);
- SD2.uart.uart_p = UART1;
+ sd_lld_init_driver(&SD2, UART1);
#else /* ! KINETIS_SERIAL1_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD2, NULL, notify);
SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -406,19 +463,20 @@ void sd_lld_init(void) { #endif /* KINETIS_SERIAL_USE_UART1 */
#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart.bdh_p = &(UART2->BDH);
- SD3.uart.bdl_p = &(UART2->BDL);
- SD3.uart.c1_p = &(UART2->C1);
- SD3.uart.c2_p = &(UART2->C2);
- SD3.uart.c3_p = &(UART2->C3);
- SD3.uart.c4_p = &(UART2->C4);
- SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
- SD3.uart.s2_p = &(UART2->S2);
- SD3.uart.d_p = &(UART2->D);
- SD3.uart.uart_p = UART2;
+ sd_lld_init_driver(&SD3, UART2);
#endif /* KINETIS_SERIAL_USE_UART2 */
+
+#if KINETIS_SERIAL_USE_UART3
+ sd_lld_init_driver(&SD4, UART3);
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ sd_lld_init_driver(&SD5, UART4);
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ sd_lld_init_driver(&SD6, UART5);
+#endif /* KINETIS_SERIAL_USE_UART5 */
}
/**
@@ -505,6 +563,33 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART2 */
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ SIM->SCGC4 |= SIM_SCGC4_UART3;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART3Status_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ nvicEnableVector(UART3Error_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ SIM->SCGC1 |= SIM_SCGC1_UART4;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART4Status_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ nvicEnableVector(UART4Error_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ SIM->SCGC1 |= SIM_SCGC1_UART5;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART5Status_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ nvicEnableVector(UART5Error_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART5 */
+
}
/* Configures the peripheral.*/
@@ -575,6 +660,30 @@ void sd_lld_stop(SerialDriver *sdp) { SIM->SCGC4 &= ~SIM_SCGC4_UART2;
}
#endif
+
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ nvicDisableVector(UART3Status_IRQn);
+ nvicDisableVector(UART3Error_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART3;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ nvicDisableVector(UART4Status_IRQn);
+ nvicDisableVector(UART4Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART4;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ nvicDisableVector(UART5Status_IRQn);
+ nvicDisableVector(UART5Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART5;
+ }
+#endif
}
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h index f11c063..3cb6d2b 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h @@ -60,6 +60,27 @@ #if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
#define KINETIS_SERIAL_USE_UART2 FALSE
#endif
+/**
+ * @brief SD4 driver enable switch.
+ * @details If set to @p TRUE the support for SD4 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART3 FALSE
+#endif
+/**
+ * @brief SD5 driver enable switch.
+ * @details If set to @p TRUE the support for SD5 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART4 FALSE
+#endif
+/**
+ * @brief SD6 driver enable switch.
+ * @details If set to @p TRUE the support for SD6 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART5 FALSE
+#endif
/**
* @brief UART0 interrupt priority level setting.
@@ -83,6 +104,27 @@ #endif
/**
+ * @brief UART3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART3_PRIORITY 12
+#endif
+
+/**
+ * @brief UART4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART4_PRIORITY 12
+#endif
+
+/**
+ * @brief UART5 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART5_PRIORITY 12
+#endif
+
+/**
* @brief UART0 clock source.
*/
#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
@@ -115,8 +157,21 @@ #error "UART2 not present in the selected device"
#endif
+#if KINETIS_SERIAL_USE_UART3 && !KINETIS_HAS_SERIAL3
+#error "UART3 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !KINETIS_HAS_SERIAL4
+#error "UART4 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !KINETIS_HAS_SERIAL5
+#error "UART5 not present in the selected device"
+#endif
+
#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
- KINETIS_SERIAL_USE_UART2)
+ KINETIS_SERIAL_USE_UART2 || KINETIS_SERIAL_USE_UART3 || \
+ KINETIS_SERIAL_USE_UART4 || KINETIS_SERIAL_USE_UART5)
#error "Serial driver activated but no UART peripheral assigned"
#endif
@@ -203,6 +258,18 @@ extern SerialDriver SD2; extern SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c index e8d9778..ba91d24 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -158,7 +158,7 @@ void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n) USBInEndpointState *isp = epc->in_state;
bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
-
+
if (n > (size_t)epc->in_maxsize)
n = (size_t)epc->in_maxsize;
@@ -244,19 +244,16 @@ OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) { {
case BDT_PID_SETUP: // SETUP
{
- /* Clear any pending IN stuff */
- _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
- /* Also in the chibios state machine */
+ /* Clear receiving in the chibios state machine */
(usbp)->receiving &= ~1;
- /* After a SETUP, IN is always DATA1 */
- usbp->epc[ep]->in_state->data_bank = DATA1;
-
- /* Call SETUP function (ChibiOS core), which sends back stuff */
+ /* Call SETUP function (ChibiOS core), which prepares
+ * for send or receive and releases the buffer
+ */
_usb_isr_invoke_setup_cb(usbp, ep);
- /* Buffer is released by the above callback. */
- /* from Paul: "unfreeze the USB, now that we're ready" */
- USB0->CTL = USBx_CTL_USBENSOFEN;
+ /* When a setup packet is received, tx is suspended,
+ * so it needs to be resumed here.
+ */
+ USB0->CTL &= ~USBx_CTL_TXSUSPENDTOKENBUSY;
} break;
case BDT_PID_IN: // IN
{
@@ -728,9 +725,23 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { }
/* Release the buffer
* Setup packet is always DATA0
- * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ * Release the current DATA0 buffer
+ */
bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
- _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ /* If DATA1 was expected, then the states are out of sync.
+ * So reset the other buffer too, and set it as DATA1.
+ * This should not happen in normal cases, but is possible in
+ * error situations. NOTE: it's possible that this is too late
+ * and the next packet has already been received and dropped, but
+ * there's nothing that we can do about that anymore at this point.
+ */
+ if (os->data_bank == DATA1)
+ {
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)];
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ }
+ /* After a SETUP, both in and out are always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
os->data_bank = DATA1;
}
@@ -762,8 +773,22 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { * @notapi
*/
void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
- (void)ep;
+ if (ep == 0 && usbp->ep0state == USB_EP0_IN_SENDING_STS) {
+ /* When a status packet is about to be sent on endpoint 0 the
+ * next packet will be a setup packet, which means that the
+ * buffer we expect after this should be DATA0, and the following
+ * DATA1. Since no out packets should be in flight at this time
+ * it's safe to initialize the buffers according to the expectations
+ * here.
+ */
+ const USBEndpointConfig* epc = usbp->epc[ep];
+ bd_t * bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even)];
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even^ODD)];
+
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ epc->out_state->data_bank = DATA0;
+ }
usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h index 615d10d..ed65b3b 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h @@ -76,6 +76,13 @@ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
#endif
+/**
+ * @brief Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -97,6 +104,10 @@ #error "KINETIS_USB_IRQ_VECTOR not defined"
#endif
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -413,6 +424,18 @@ struct USBDriver { #endif /* KINETIS_USB0_IS_USBOTG */
#endif
+/**
+ * @brief Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp) \
+ do{ \
+ USB0->CTL |= USBx_CTL_RESUME; \
+ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
+ USB0->CTL &= ~USBx_CTL_RESUME; \
+ } while (false)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
|