diff options
| author | TexZK <texzk@email.it> | 2015-06-24 21:24:45 +0200 |
|---|---|---|
| committer | TexZK <texzk@email.it> | 2015-06-24 21:24:45 +0200 |
| commit | 542d79ef90862518ffcfb500679e293e5a89c864 (patch) | |
| tree | 29e548064386cdd2ce063396d2331b6deafa33dd /demos/STM32 | |
| parent | 57d8d8f5496922112f9af6251545d26ce5e915d6 (diff) | |
| download | ChibiOS-Contrib-542d79ef90862518ffcfb500679e293e5a89c864.tar.gz ChibiOS-Contrib-542d79ef90862518ffcfb500679e293e5a89c864.tar.bz2 ChibiOS-Contrib-542d79ef90862518ffcfb500679e293e5a89c864.zip | |
LTDC and DMA2D ported to ChibiOS/RT 3
+ LTDC and DMA2D peripheral drivers
+ LTDC and DMA2D demo project
Diffstat (limited to 'demos/STM32')
26 files changed, 11088 insertions, 0 deletions
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject new file mode 100644 index 0000000..ddfa092 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject @@ -0,0 +1,58 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.114656749">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.114656749." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1821379090" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.586544031" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1379525985" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="RT-STM32F429-DISCOVERY-DMA2D.null.1703860681" name="RT-STM32F429-DISCOVERY-DMA2D"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.114656749">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Default">
+ <resource resourceType="PROJECT" workspacePath="/RT-STM32F429-DISCOVERY-DMA2D"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore new file mode 100644 index 0000000..060dd31 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore @@ -0,0 +1,2 @@ +build/
+.dep/
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project new file mode 100644 index 0000000..b445991 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project @@ -0,0 +1,90 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RT-STM32F429-DISCOVERY-DMA2D</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>?name?</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildArguments</key>
+ <value>-j1</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildCommand</key>
+ <value>make</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.contents</key>
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>true</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ <link>
+ <name>test</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/test</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml new file mode 100644 index 0000000..cb0455a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml @@ -0,0 +1,11 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="0.114656749" name="Default">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
+ </extension>
+ </configuration>
+</project>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile new file mode 100644 index 0000000..3de08f4 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile @@ -0,0 +1,229 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+# Startup files.
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ ./main.c \
+ ./ili9341.c \
+ ./wolf3d_palette.c \
+ ./res/wolf3d_vgagraph_chunk87.c \
+ ./stmdrivers/stm32f4xx_fmc.c \
+ ./stmdrivers/stm32f429i_discovery_sdram.c \
+ # eol
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various \
+ $(CHIBIOS)/os/hal/lib/streams \
+ ./res \
+ ./stmdrivers \
+ # eol
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h new file mode 100644 index 0000000..48ada74 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h @@ -0,0 +1,499 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS TRUE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..a7d2f61 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
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+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
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+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
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+</listAttribute>
+</launchConfiguration>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch new file mode 100644 index 0000000..2f1fa66 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
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diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h new file mode 100644 index 0000000..e9ab9d7 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h @@ -0,0 +1,334 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI TRUE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.c new file mode 100644 index 0000000..f2efa8d --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.c @@ -0,0 +1,418 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ili9341.c
+ * @brief ILI9341 TFT LCD diaplay controller driver.
+ * @note Does not support multiple calling threads natively.
+ */
+
+#include "ch.h"
+#include "hal.h"
+#include "ili9341.h"
+
+/**
+ * @addtogroup ili9341
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if !ILI9341_USE_CHECKS && !defined(__DOXYGEN__)
+/* Disable checks as needed.*/
+
+#ifdef osalDbgCheck
+#undef osalDbgCheck
+#endif
+#define osalDbgCheck(c, func) { \
+ (void)(c), (void)__QUOTE_THIS(func)"()"; \
+}
+
+#ifdef osalDbgAssert
+#undef osalDbgAssert
+#endif
+#define osalDbgAssert(c, m, r) { \
+ (void)(c); \
+}
+
+#ifdef osalDbgCheckClassS
+#undef osalDbgCheckClassS
+#endif
+#define osalDbgCheckClassS() {}
+
+#ifdef osalDbgCheckClassS
+#undef osalDbgCheckClassS
+#endif
+#define osalDbgCheckClassI() {}
+
+#endif /* ILI9341_USE_CHECKS */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ILI9341D1 driver identifier.*/
+ILI9341Driver ILI9341D1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the standard part of a @p ILI9341Driver structure.
+ *
+ * @param[out] driverp pointer to the @p ILI9341Driver object
+ *
+ * @init
+ */
+void ili9341ObjectInit(ILI9341Driver *driverp) {
+
+ osalDbgCheck(driverp != NULL);
+
+ driverp->state = ILI9341_STOP;
+ driverp->config = NULL;
+#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxObjectInit(&driverp->lock);
+#else
+ chSemObjectInit(&driverp->lock, 1);
+#endif
+#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */
+}
+
+/**
+ * @brief Configures and activates the ILI9341 peripheral.
+ * @pre ILI9341 is stopped.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ * @param[in] configp pointer to the @p ILI9341Config object
+ *
+ * @api
+ */
+void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp) {
+
+ chSysLock();
+ osalDbgCheck(driverp != NULL);
+ osalDbgCheck(configp != NULL);
+ osalDbgCheck(configp->spi != NULL);
+ osalDbgAssert(driverp->state == ILI9341_STOP, "invalid state");
+
+ spiSelectI(configp->spi);
+ spiUnselectI(configp->spi);
+ driverp->config = configp;
+ driverp->state = ILI9341_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Deactivates the ILI9341 peripheral.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @api
+ */
+void ili9341Stop(ILI9341Driver *driverp) {
+
+ chSysLock();
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_READY, "invalid state");
+
+ driverp->state = ILI9341_STOP;
+ chSysUnlock();
+}
+
+#if ILI9341_USE_MUTUAL_EXCLUSION
+
+/**
+ * @brief Gains exclusive access to the ILI9341 module.
+ * @details This function tries to gain ownership to the ILI9341 module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @sclass
+ */
+void ili9341AcquireBusS(ILI9341Driver *driverp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(driverp == &ILI9341D1);
+ osalDbgAssert(driverp->state == ILI9341_READY, "not ready");
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxLockS(&driverp->lock);
+#else
+ chSemWaitS(&driverp->lock);
+#endif
+}
+
+/**
+ * @brief Gains exclusive access to the ILI9341 module.
+ * @details This function tries to gain ownership to the ILI9341 module, if the
+ * module is already being used then the invoking thread is queued.
+ * @pre In order to use this function the option
+ * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @api
+ */
+void ili9341AcquireBus(ILI9341Driver *driverp) {
+
+ chSysLock();
+ ili9341AcquireBusS(driverp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Releases exclusive access to the ILI9341 module.
+ * @pre In order to use this function the option
+ * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @sclass
+ */
+void ili9341ReleaseBusS(ILI9341Driver *driverp) {
+
+ osalDbgCheckClassS();
+ osalDbgCheck(driverp == &ILI9341D1);
+ osalDbgAssert(driverp->state == ILI9341_READY, "not ready");
+
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ chMtxUnlockS(&driverp->lock);
+#else
+ chSemSignalI(&driverp->lock);
+#endif
+}
+
+/**
+ * @brief Releases exclusive access to the ILI9341 module.
+ * @pre In order to use this function the option
+ * @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @api
+ */
+void ili9341ReleaseBus(ILI9341Driver *driverp) {
+
+ chSysLock();
+ ili9341ReleaseBusS(driverp);
+ chSysUnlock();
+}
+
+#endif /* ILI9341_USE_MUTUAL_EXCLUSION */
+
+#if ILI9341_IM == ILI9341_IM_4LSI_1 /* 4-wire, half-duplex */
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @iclass
+ */
+void ili9341SelectI(ILI9341Driver *driverp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_READY, "invalid state");
+
+ driverp->state = ILI9341_ACTIVE;
+ spiSelectI(driverp->config->spi);
+}
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ * @pre ILI9341 is ready.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @api
+ */
+void ili9341Select(ILI9341Driver *driverp) {
+
+ chSysLock();
+ ili9341SelectI(driverp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ * @pre ILI9341 is active.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @iclass
+ */
+void ili9341UnselectI(ILI9341Driver *driverp) {
+
+ osalDbgCheckClassI();
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ spiUnselectI(driverp->config->spi);
+ driverp->state = ILI9341_READY;
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ * @pre ILI9341 is active.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @iclass
+ */
+void ili9341Unselect(ILI9341Driver *driverp) {
+
+ chSysLock();
+ ili9341UnselectI(driverp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Write command byte.
+ * @details Sends a command byte via SPI.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ * @param[in] cmd command byte
+ *
+ * @api
+ */
+void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd) {
+
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ driverp->value = cmd;
+ palClearPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* !Cmd */
+ spiSend(driverp->config->spi, 1, &driverp->value);
+}
+
+/**
+ * @brief Write data byte.
+ * @details Sends a data byte via SPI.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ * @param[in] value data byte
+ *
+ * @api
+ */
+void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value) {
+
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ driverp->value = value;
+ palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
+ spiSend(driverp->config->spi, 1, &driverp->value);
+}
+
+/**
+ * @brief Read data byte.
+ * @details Receives a data byte via SPI.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ *
+ * @return data byte
+ *
+ * @api
+ */
+uint8_t ili9341ReadByte(ILI9341Driver *driverp) {
+
+ osalDbgAssert(FALSE, "should not be used");
+
+ osalDbgCheck(driverp != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
+ spiReceive(driverp->config->spi, 1, &driverp->value);
+ return driverp->value;
+}
+
+/**
+ * @brief Write data chunk.
+ * @details Sends a data chunk via SPI.
+ * @pre The chunk must be accessed by DMA.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ * @param[in] chunk chunk bytes
+ * @param[in] length chunk length
+ *
+ * @api
+ */
+void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[],
+ size_t length) {
+
+ osalDbgCheck(driverp != NULL);
+ osalDbgCheck(chunk != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ if (length != 0) {
+ palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
+ spiSend(driverp->config->spi, length, chunk);
+ }
+}
+
+/**
+ * @brief Read data chunk.
+ * @details Receives a data chunk via SPI.
+ * @pre The chunk must be accessed by DMA.
+ *
+ * @param[in] driverp pointer to the @p ILI9341Driver object
+ * @param[out] chunk chunk bytes
+ * @param[in] length chunk length
+ *
+ * @api
+ */
+void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[],
+ size_t length) {
+
+ osalDbgCheck(driverp != NULL);
+ osalDbgCheck(chunk != NULL);
+ osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
+
+ if (length != 0) {
+ palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
+ spiReceive(driverp->config->spi, length, chunk);
+ }
+}
+
+#else /* ILI9341_IM == * */
+#error "Only the ILI9341_IM_4LSI_1 interface mode is currently supported"
+#endif /* ILI9341_IM == * */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.h new file mode 100644 index 0000000..3e34772 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.h @@ -0,0 +1,593 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file ili9341.h
+ * @brief ILI9341 TFT LCD diaplay controller driver.
+ */
+
+#ifndef _ILI9341_H_
+#define _ILI9341_H_
+
+/**
+ * @addtogroup ili9341
+ * @{
+ */
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ILI9341 regulative commands
+ * @{
+ */
+#define ILI9341_CMD_NOP (0x00) /**< No operation.*/
+#define ILI9341_CMD_RESET (0x01) /**< Software reset.*/
+#define ILI9341_GET_ID_INFO (0x04) /**< Get ID information.*/
+#define ILI9341_GET_STATUS (0x09) /**< Get status.*/
+#define ILI9341_GET_PWR_MODE (0x0A) /**< Get power mode.*/
+#define ILI9341_GET_MADCTL (0x0B) /**< Get MADCTL.*/
+#define ILI9341_GET_PIX_FMT (0x0C) /**< Get pixel format.*/
+#define ILI9341_GET_IMG_FMT (0x0D) /**< Get image format.*/
+#define ILI9341_GET_SIG_MODE (0x0E) /**< Get signal mode.*/
+#define ILI9341_GET_SELF_DIAG (0x0F) /**< Get self-diagnostics.*/
+#define ILI9341_CMD_SLEEP_ON (0x10) /**< Enter sleep mode.*/
+#define ILI9341_CMD_SLEEP_OFF (0x11) /**< Exist sleep mode.*/
+#define ILI9341_CMD_PARTIAL_ON (0x12) /**< Enter partial mode.*/
+#define ILI9341_CMD_PARTIAL_OFF (0x13) /**< Exit partial mode.*/
+#define ILI9341_CMD_INVERT_ON (0x20) /**< Enter inverted mode.*/
+#define ILI9341_CMD_INVERT_OFF (0x21) /**< Exit inverted mode.*/
+#define ILI9341_SET_GAMMA (0x26) /**< Set gamma params.*/
+#define ILI9341_CMD_DISPLAY_OFF (0x28) /**< Disable display.*/
+#define ILI9341_CMD_DISPLAY_ON (0x29) /**< Enable display.*/
+#define ILI9341_SET_COL_ADDR (0x2A) /**< Set column address.*/
+#define ILI9341_SET_PAGE_ADDR (0x2B) /**< Set page address.*/
+#define ILI9341_SET_MEM (0x2C) /**< Set memory.*/
+#define ILI9341_SET_COLOR (0x2D) /**< Set color.*/
+#define ILI9341_GET_MEM (0x2E) /**< Get memory.*/
+#define ILI9341_SET_PARTIAL_AREA (0x30) /**< Set partial area.*/
+#define ILI9341_SET_VSCROLL (0x33) /**< Set vertical scroll def.*/
+#define ILI9341_CMD_TEARING_ON (0x34) /**< Tearing line enabled.*/
+#define ILI9341_CMD_TEARING_OFF (0x35) /**< Tearing line disabled.*/
+#define ILI9341_SET_MEM_ACS_CTL (0x36) /**< Set mem access ctl.*/
+#define ILI9341_SET_VSCROLL_ADDR (0x37) /**< Set vscroll start addr.*/
+#define ILI9341_CMD_IDLE_OFF (0x38) /**< Exit idle mode.*/
+#define ILI9341_CMD_IDLE_ON (0x39) /**< Enter idle mode.*/
+#define ILI9341_SET_PIX_FMT (0x3A) /**< Set pixel format.*/
+#define ILI9341_SET_MEM_CONT (0x3C) /**< Set memory continue.*/
+#define ILI9341_GET_MEM_CONT (0x3E) /**< Get memory continue.*/
+#define ILI9341_SET_TEAR_SCANLINE (0x44) /**< Set tearing scanline.*/
+#define ILI9341_GET_TEAR_SCANLINE (0x45) /**< Get tearing scanline.*/
+#define ILI9341_SET_BRIGHTNESS (0x51) /**< Set brightness.*/
+#define ILI9341_GET_BRIGHTNESS (0x52) /**< Get brightness.*/
+#define ILI9341_SET_DISPLAY_CTL (0x53) /**< Set display ctl.*/
+#define ILI9341_GET_DISPLAY_CTL (0x54) /**< Get display ctl.*/
+#define ILI9341_SET_CABC (0x55) /**< Set CABC.*/
+#define ILI9341_GET_CABC (0x56) /**< Get CABC.*/
+#define ILI9341_SET_CABC_MIN (0x5E) /**< Set CABC min.*/
+#define ILI9341_GET_CABC_MIN (0x5F) /**< Set CABC max.*/
+#define ILI9341_GET_ID1 (0xDA) /**< Get ID1.*/
+#define ILI9341_GET_ID2 (0xDB) /**< Get ID2.*/
+#define ILI9341_GET_ID3 (0xDC) /**< Get ID3.*/
+/** @} */
+
+/**
+ * @name ILI9341 extended commands
+ * @{
+ */
+#define ILI9341_SET_RGB_IF_SIG_CTL (0xB0) /**< RGB IF signal ctl.*/
+#define ILI9341_SET_FRAME_CTL_NORMAL (0xB1) /**< Set frame ctl (normal).*/
+#define ILI9341_SET_FRAME_CTL_IDLE (0xB2) /**< Set frame ctl (idle).*/
+#define ILI9341_SET_FRAME_CTL_PARTIAL (0xB3) /**< Set frame ctl (partial).*/
+#define ILI9341_SET_INVERSION_CTL (0xB4) /**< Set inversion ctl.*/
+#define ILI9341_SET_BLANKING_PORCH_CTL (0xB5) /**< Set blanking porch ctl.*/
+#define ILI9341_SET_FUNCTION_CTL (0xB6) /**< Set function ctl.*/
+#define ILI9341_SET_ENTRY_MODE (0xB7) /**< Set entry mode.*/
+#define ILI9341_SET_LIGHT_CTL_1 (0xB8) /**< Set backlight ctl 1.*/
+#define ILI9341_SET_LIGHT_CTL_2 (0xB9) /**< Set backlight ctl 2.*/
+#define ILI9341_SET_LIGHT_CTL_3 (0xBA) /**< Set backlight ctl 3.*/
+#define ILI9341_SET_LIGHT_CTL_4 (0xBB) /**< Set backlight ctl 4.*/
+#define ILI9341_SET_LIGHT_CTL_5 (0xBC) /**< Set backlight ctl 5.*/
+#define ILI9341_SET_LIGHT_CTL_7 (0xBE) /**< Set backlight ctl 7.*/
+#define ILI9341_SET_LIGHT_CTL_8 (0xBF) /**< Set backlight ctl 8.*/
+#define ILI9341_SET_POWER_CTL_1 (0xC0) /**< Set power ctl 1.*/
+#define ILI9341_SET_POWER_CTL_2 (0xC1) /**< Set power ctl 2.*/
+#define ILI9341_SET_VCOM_CTL_1 (0xC5) /**< Set VCOM ctl 1.*/
+#define ILI9341_SET_VCOM_CTL_2 (0xC6) /**< Set VCOM ctl 2.*/
+#define ILI9341_SET_NVMEM (0xD0) /**< Set NVMEM data.*/
+#define ILI9341_GET_NVMEM_KEY (0xD1) /**< Get NVMEM protect key.*/
+#define ILI9341_GET_NVMEM_STATUS (0xD2) /**< Get NVMEM status.*/
+#define ILI9341_GET_ID4 (0xD3) /**< Get ID4.*/
+#define ILI9341_SET_PGAMMA (0xE0) /**< Set positive gamma.*/
+#define ILI9341_SET_NGAMMA (0xE1) /**< Set negative gamma.*/
+#define ILI9341_SET_DGAMMA_CTL_1 (0xE2) /**< Set digital gamma ctl 1.*/
+#define ILI9341_SET_DGAMMA_CTL_2 (0xE3) /**< Set digital gamma ctl 2.*/
+#define ILI9341_SET_IF_CTL (0xF6) /**< Set interface control.*/
+/** @} */
+
+/**
+ * @name ILI9341 interface modes
+ * @{
+ */
+#define ILI9341_IM_3LSI_1 (0x5) /**< 3-line serial, mode 1.*/
+#define ILI9341_IM_3LSI_2 (0xD) /**< 3-line serial, mode 2.*/
+#define ILI9341_IM_4LSI_1 (0x6) /**< 4-line serial, mode 1.*/
+#define ILI9341_IM_4LSI_2 (0xE) /**< 4-line serial, mode 2.*/
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name ILI9341 configuration options
+ * @{
+ */
+
+/**
+ * @brief Enables the @p ili9341AcquireBus() and @p ili9341ReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ILI9341_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ILI9341_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/**
+ * @brief ILI9341 Interface Mode.
+ */
+#if !defined(ILI9341_IM) || defined(__DOXYGEN__)
+#define ILI9341_IM (ILI9341_IM_4LSI_1)
+#endif
+
+/**
+ * @brief Enables checks for ILI9341 functions.
+ * @note Disabling this option saves both code and data space.
+ * @note Disabling checks by ChibiOS will automatically disable ILI9341
+ * checks.
+ */
+#if !defined(ILI9341_USE_CHECKS) || defined(__DOXYGEN__)
+#define ILI9341_USE_CHECKS TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if ((TRUE == ILI9341_USE_MUTUAL_EXCLUSION) && \
+ (TRUE != CH_CFG_USE_MUTEXES) && \
+ (TRUE != CH_CFG_USE_SEMAPHORES))
+#error "ILI9341_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
+#endif
+
+/* TODO: Add the remaining modes.*/
+#if (ILI9341_IM != ILI9341_IM_4LSI_1)
+#error "Only ILI9341_IM_4LSI_1 interface mode is supported currently"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* Complex types forwarding.*/
+typedef struct ILI9341Config ILI9341Config;
+typedef enum ili9341state_t ili9341state_t;
+typedef struct ILI9341Driver ILI9341Driver;
+
+/**
+ * @brief ILI9341 driver configuration.
+ */
+typedef struct ILI9341Config {
+ SPIDriver *spi; /**< SPI driver used by ILI9341.*/
+#if (ILI9341_IM == ILI9341_IM_4LSI_1)
+ ioportid_t dcx_port; /**< <tt>D/!C</tt> signal port.*/
+ uint16_t dcx_pad; /**< <tt>D/!C</tt> signal pad.*/
+#endif /* ILI9341_IM == * */ /* TODO: Add all modes.*/
+} ILI9341Config;
+
+/**
+ * @brief ILI9341 driver state.
+ */
+typedef enum ili9341state_t {
+ ILI9341_UNINIT = (0), /**< Not initialized.*/
+ ILI9341_STOP = (1), /**< Stopped.*/
+ ILI9341_READY = (2), /**< Ready.*/
+ ILI9341_ACTIVE = (3), /**< Exchanging data.*/
+} ili9341state_t;
+
+/**
+ * @brief ILI9341 driver.
+ */
+typedef struct ILI9341Driver {
+ ili9341state_t state; /**< Driver state.*/
+ const ILI9341Config *config; /**< Driver configuration.*/
+
+ /* Multithreading stuff.*/
+#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION)
+#if (TRUE == CH_CFG_USE_MUTEXES)
+ mutex_t lock; /**< Multithreading lock.*/
+#elif (TRUE == CH_CFG_USE_SEMAPHORES)
+ semaphore_t lock; /**< Multithreading lock.*/
+#endif
+#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */
+
+ /* Temporary variables.*/
+ uint8_t value; /**< Non-stacked value, for SPI with CCM.*/
+} ILI9341Driver;
+
+/**
+ * @name ILI9341 command params (little endian)
+ * @{
+ */
+#pragma pack(push, 1)
+
+typedef union {
+ struct ILI9341ParamBits_GET_ID_INFO {
+ uint8_t reserved_;
+ uint8_t ID1;
+ uint8_t ID2;
+ uint8_t ID3;
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_GET_ID_INFO;
+
+typedef union {
+ struct ILI9341ParamBits_GET_STATUS {
+ unsigned _reserved_1 : 5; /* D[ 4: 0] */
+ unsigned tearing_mode : 1; /* D[ 5] */
+ unsigned gamma_curve : 3; /* D[ 8: 6] */
+ unsigned tearing : 1; /* D[ 9] */
+ unsigned display : 1; /* D[10] */
+ unsigned all_on : 1; /* D[11] */
+ unsigned all_off : 1; /* D[12] */
+ unsigned invert : 1; /* D[13] */
+ unsigned _reserved_2 : 1; /* D[14] */
+ unsigned vscroll : 1; /* D[15] */
+ unsigned normal : 1; /* D[16] */
+ unsigned sleep : 1; /* D[17] */
+ unsigned partial : 1; /* D[18] */
+ unsigned idle : 1; /* D[19] */
+ unsigned pixel_format : 3; /* D[22:20] */
+ unsigned _reserved_3 : 2; /* D[24:23] */
+ unsigned hrefr_rtl_nltr : 1; /* D[25] */
+ unsigned bgr_nrgb : 1; /* D[26] */
+ unsigned vrefr_btt_nttb : 1; /* D[27] */
+ unsigned transpose : 1; /* D[28] */
+ unsigned coladr_rtl_nltr : 1; /* D[29] */
+ unsigned rowadr_btt_nttb : 1; /* D[30] */
+ unsigned booster : 1; /* D[31] */
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_GET_STATUS;
+
+typedef union {
+ struct ILI9341ParamBits_GET_PWR_MODE {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned display : 1; /* D[2] */
+ unsigned normal : 1; /* D[3] */
+ unsigned sleep : 1; /* D[4] */
+ unsigned partial : 1; /* D[5] */
+ unsigned idle : 1; /* D[6] */
+ unsigned booster : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_PWR_MODE;
+
+typedef union {
+ struct ILI9341ParamBits_GET_MADCTL {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned refr_rtl_nltr : 1; /* D[2] */
+ unsigned bgr_nrgb : 1; /* D[3] */
+ unsigned refr_btt_nttb : 1; /* D[4] */
+ unsigned invert : 1; /* D[5] */
+ unsigned rtl_nltr : 1; /* D[6] */
+ unsigned btt_nttb : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_MADCTL;
+
+typedef union {
+ struct ILI9341ParamBits_GET_PIX_FMT {
+ unsigned DBI : 3; /* D[2:0] */
+ unsigned _reserved_1 : 1; /* D[3] */
+ unsigned DPI : 3; /* D[6:4] */
+ unsigned RIM : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_PIX_FMT;
+
+typedef union {
+ struct ILI9341ParamBits_GET_IMG_FMT {
+ unsigned gamma_curve : 3; /* D[2:0] */
+ unsigned _reserved_1 : 5; /* D[7:3] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_IMG_FMT;
+
+typedef union {
+ struct ILI9341ParamBits_GET_SIG_MODE {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned data_enable : 1; /* D[2] */
+ unsigned pixel_clock : 1; /* D[3] */
+ unsigned vsync : 1; /* D[4] */
+ unsigned hsync : 1; /* D[5] */
+ unsigned tearing_mode : 1; /* D[6] */
+ unsigned tearing : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_SIG_MODE;
+
+typedef union {
+ struct ILI9341ParamBits_GET_SELF_DIAG {
+ unsigned _reserved_1 : 6; /* D[5:0] */
+ unsigned func_err : 1; /* D[6] */
+ unsigned reg_err : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_SELF_DIAG;
+
+typedef union {
+ struct ILI9341ParamBits_SET_GAMMA {
+ uint8_t gamma_curve; /* D[7:0] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_GAMMA;
+
+typedef union {
+ struct ILI9341ParamBits_SET_COL_ADDR {
+ uint8_t SC_15_8; /* D[ 7: 0] */
+ uint8_t SC_7_0; /* D[15: 8] */
+ uint8_t EC_15_8; /* D[23:16] */
+ uint8_t EC_7_0; /* D[31:24] */
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_SET_COL_ADDR;
+
+typedef union {
+ struct ILI9341ParamBits_SET_PAGE_ADDR {
+ uint8_t SP_15_8; /* D[ 7: 0] */
+ uint8_t SP_7_0; /* D[15: 8] */
+ uint8_t EP_15_8; /* D[23:16] */
+ uint8_t EP_7_0; /* D[31:24] */
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_SET_PAGE_ADDR;
+
+typedef union {
+ struct ILI9341ParamBits_SET_PARTIAL_AREA {
+ uint8_t SR_15_8; /* D[ 7: 0] */
+ uint8_t SR_7_0; /* D[15: 8] */
+ uint8_t ER_15_8; /* D[23:16] */
+ uint8_t ER_7_0; /* D[31:24] */
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_SET_PARTIAL_AREA;
+
+typedef union {
+ struct ILI9341ParamBits_SET_VSCROLL {
+ uint8_t TFA_15_8; /* D[ 7: 0] */
+ uint8_t TFA_7_0; /* D[15: 8] */
+ uint8_t VSA_15_8; /* D[23:16] */
+ uint8_t VSA_7_0; /* D[31:24] */
+ uint8_t BFA_15_8; /* D[39:32] */
+ uint8_t BFA_7_0; /* D[47:40] */
+ } bits;
+ uint8_t bytes[6];
+} ILI9341Params_SET_VSCROLL;
+
+typedef union {
+ struct ILI9341ParamBits_CMD_TEARING_ON {
+ unsigned M : 1; /* D[0] */
+ unsigned _reserved_1 : 7; /* D[7:1] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_CMD_TEARING_ON;
+
+typedef union {
+ struct ILI9341ParamBits_SET_MEM_ACS_CTL {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned MH : 1; /* D[2] */
+ unsigned BGR : 1; /* D[3] */
+ unsigned ML : 1; /* D[4] */
+ unsigned MV : 1; /* D[5] */
+ unsigned MX : 1; /* D[6] */
+ unsigned MY : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_MEM_ACS_CTL;
+
+typedef union {
+ struct ILI9341ParamBits_SET_VSCROLL_ADDR {
+ uint8_t VSP_15_8; /* D[ 7: 0] */
+ uint8_t VSP_7_0; /* D[15: 8] */
+ } bits;
+ uint8_t bytes[2];
+} ILI9341Params_SET_VSCROLL_ADDR;
+
+typedef union {
+ struct ILI9341ParamBits_SET_PIX_FMT {
+ unsigned DBI : 3; /* D[2:0] */
+ unsigned _reserved_1 : 1; /* D[3] */
+ unsigned DPI : 3; /* D[4:6] */
+ unsigned _reserved_2 : 1; /* D[7] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_PIX_FMT;
+
+typedef union {
+ struct ILI9341ParamBits_SET_TEAR_SCANLINE {
+ uint8_t STS_8; /* D[ 7: 0] */
+ uint8_t STS_7_0; /* D[15: 8] */
+ } bits;
+ uint8_t bytes[4];
+} ILI9341Params_SET_TEAR_SCANLINE;
+
+typedef union {
+ struct ILI9341ParamBits_GET_TEAR_SCANLINE {
+ uint8_t GTS_9_8; /* D[ 7: 0] */
+ uint8_t GTS_7_0; /* D[15: 8] */
+ } bits;
+ uint8_t bytes[2];
+} ILI9341Params_GET_TEAR_SCANLINE;
+
+typedef union {
+ struct ILI9341ParamBits_SET_BRIGHTNESS {
+ uint8_t DBV; /* D[7:0] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_BRIGHTNESS;
+
+typedef union {
+ struct ILI9341ParamBits_GET_BRIGHTNESS {
+ uint8_t DBV; /* D[7:0] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_BRIGHTNESS;
+
+typedef union {
+ struct ILI9341ParamBits_SET_DISPLAY_CTL {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned BL : 1; /* D[2] */
+ unsigned DD : 1; /* D[3] */
+ unsigned _reserved_2 : 1; /* D[4] */
+ unsigned BCTRL : 1; /* D[5] */
+ unsigned _reserved_3 : 1; /* D[7:6] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_DISPLAY_CTL;
+
+typedef union {
+ struct ILI9341ParamBits_GET_DISPLAY_CTL {
+ unsigned _reserved_1 : 2; /* D[1:0] */
+ unsigned BL : 1; /* D[2] */
+ unsigned DD : 1; /* D[3] */
+ unsigned _reserved_2 : 1; /* D[4] */
+ unsigned BCTRL : 1; /* D[5] */
+ unsigned _reserved_3 : 1; /* D[7:6] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_DISPLAY_CTL;
+
+typedef union {
+ struct ILI9341ParamBits_SET_CABC {
+ unsigned C : 2; /* D[1:0] */
+ unsigned _reserved_1 : 6; /* D[7:2] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_CABC;
+
+typedef union {
+ struct ILI9341ParamBits_GET_CABC {
+ unsigned C : 2; /* D[1:0] */
+ unsigned _reserved_1 : 6; /* D[7:2] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_CABC;
+
+typedef union {
+ struct ILI9341ParamBits_SET_CABC_MIN {
+ uint8_t CMB; /* D[7:0] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_SET_CABC_MIN;
+
+typedef union {
+ struct ILI9341ParamBits_GET_CABC_MIN {
+ uint8_t CMB; /* D[7:0] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_GET_CABC_MIN;
+
+#if 0 /* TODO: Extended command structs.*/
+
+typedef union {
+ struct ILI9341ParamBits {
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_;
+
+typedef union {
+ struct ILI9341ParamBits {
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ unsigned : 1; /* D[] */
+ } bits;
+ uint8_t bytes[1];
+} ILI9341Params_;
+
+#endif /*0*/
+
+#pragma pack(pop)
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+extern ILI9341Driver ILI9341D1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ void ili9341ObjectInit(ILI9341Driver *driverp);
+ void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp);
+ void ili9341Stop(ILI9341Driver *driverp);
+#if (ILI9341_USE_MUTUAL_EXCLUSION == TRUE)
+ void ili9341AcquireBusS(ILI9341Driver *driverp);
+ void ili9341AcquireBus(ILI9341Driver *driverp);
+ void ili9341ReleaseBusS(ILI9341Driver *driverp);
+ void ili9341ReleaseBus(ILI9341Driver *driverp);
+#endif /* (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) */
+ void ili9341SelectI(ILI9341Driver *driverp);
+ void ili9341Select(ILI9341Driver *driverp);
+ void ili9341UnselectI(ILI9341Driver *driverp);
+ void ili9341Unselect(ILI9341Driver *driverp);
+ void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd);
+ void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value);
+ uint8_t ili9341ReadByte(ILI9341Driver *driverp);
+ void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[],
+ size_t length);
+ void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[],
+ size_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* _ILI9341_H_ */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c new file mode 100644 index 0000000..e307cd0 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -0,0 +1,785 @@ +/*
+ Copyright (C) 2013-2015 Andrea Zoppi
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "chprintf.h"
+#include "shell.h"
+#if HAL_USE_SERIAL_USB
+#include "usbcfg.h"
+#endif
+
+#include "stmdrivers/stm32f429i_discovery_sdram.h"
+#include "stmdrivers/stm32f4xx_fmc.h"
+
+#include "ili9341.h"
+#include "stm32_ltdc.h"
+#include "stm32_dma2d.h"
+
+#include "res/wolf3d_vgagraph_chunk87.h"
+
+#define IS42S16400J_SIZE (8 * 1024 * 1024)
+
+/*
+ * Erases the whole SDRAM bank.
+ */
+static void sdram_bulk_erase(void) {
+
+ volatile uint8_t *p = (volatile uint8_t *)SDRAM_BANK_ADDR;
+ volatile uint8_t *end = p + IS42S16400J_SIZE;
+ while (p < end)
+ *p++ = 0;
+}
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker1");
+ while (true) {
+ palClearPad(GPIOG, GPIOG_LED4_RED);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOG, GPIOG_LED4_RED);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+/*
+ * Green LED blinker thread, times are in milliseconds.
+ */
+static THD_WORKING_AREA(waThread2, 128);
+static THD_FUNCTION(Thread2, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker2");
+ while (true) {
+ palClearPad(GPIOG, GPIOG_LED3_GREEN);
+ chThdSleepMilliseconds(250);
+ palSetPad(GPIOG, GPIOG_LED3_GREEN);
+ chThdSleepMilliseconds(250);
+ }
+}
+
+/*===========================================================================*/
+/* LTDC related. */
+/*===========================================================================*/
+
+static uint8_t frame_buffer[240 * 320 * 3] __attribute__((section(".ram7")));
+
+static uint8_t view_buffer[240 * 320];
+
+extern const ltdc_color_t wolf3d_palette[256];
+
+static const ltdc_window_t ltdc_fullscreen_wincfg = {
+ 0,
+ 240 - 1,
+ 0,
+ 320 - 1
+};
+
+static const ltdc_frame_t ltdc_view_frmcfg1 = {
+ view_buffer,
+ 240,
+ 320,
+ 240 * sizeof(uint8_t),
+ LTDC_FMT_L8
+};
+
+static const ltdc_laycfg_t ltdc_view_laycfg1 = {
+ <dc_view_frmcfg1,
+ <dc_fullscreen_wincfg,
+ LTDC_COLOR_FUCHSIA,
+ 0xFF,
+ 0x980088,
+ wolf3d_palette,
+ 256,
+ LTDC_BLEND_FIX1_FIX2,
+ LTDC_LEF_ENABLE | LTDC_LEF_PALETTE
+};
+
+static const ltdc_frame_t ltdc_screen_frmcfg1 = {
+ frame_buffer,
+ 240,
+ 320,
+ 240 * 3,
+ LTDC_FMT_RGB888
+};
+
+static const ltdc_laycfg_t ltdc_screen_laycfg1 = {
+ <dc_screen_frmcfg1,
+ <dc_fullscreen_wincfg,
+ LTDC_COLOR_FUCHSIA,
+ 0xFF,
+ 0x980088,
+ NULL,
+ 0,
+ LTDC_BLEND_FIX1_FIX2,
+ LTDC_LEF_ENABLE
+};
+
+static const LTDCConfig ltdc_cfg = {
+ /* Display specifications.*/
+ 240, /**< Screen pixel width.*/
+ 320, /**< Screen pixel height.*/
+ 10, /**< Horizontal sync pixel width.*/
+ 2, /**< Vertical sync pixel height.*/
+ 20, /**< Horizontal back porch pixel width.*/
+ 2, /**< Vertical back porch pixel height.*/
+ 10, /**< Horizontal front porch pixel width.*/
+ 4, /**< Vertical front porch pixel height.*/
+ 0, /**< Driver configuration flags.*/
+
+ /* ISR callbacks.*/
+ NULL, /**< Line Interrupt ISR, or @p NULL.*/
+ NULL, /**< Register Reload ISR, or @p NULL.*/
+ NULL, /**< FIFO Underrun ISR, or @p NULL.*/
+ NULL, /**< Transfer Error ISR, or @p NULL.*/
+
+ /* Color and layer settings.*/
+ LTDC_COLOR_TEAL,
+ <dc_view_laycfg1,
+ NULL
+};
+
+extern LTDCDriver LTDCD1;
+
+const SPIConfig spi_cfg5 = {
+ NULL,
+ GPIOC,
+ GPIOC_SPI5_LCD_CS,
+ ((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
+};
+
+extern SPIDriver SPID5;
+
+const ILI9341Config ili9341_cfg = {
+ &SPID5,
+ GPIOD,
+ GPIOD_LCD_WRX
+};
+
+static void initialize_lcd(void) {
+
+ static const uint8_t pgamma[15] = {
+ 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
+ 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00
+ };
+ static const uint8_t ngamma[15] = {
+ 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
+ 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F
+ };
+
+ ILI9341Driver *const lcdp = &ILI9341D1;
+
+ /* XOR-checkerboard texture.*/
+ unsigned x, y;
+ for (y = 0; y < 320; ++y)
+ for (x = 0; x < 240; ++x)
+ view_buffer[y * 240 + x] = (uint8_t)(x ^ y);
+
+ ili9341AcquireBus(lcdp);
+ ili9341Select(lcdp);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FRAME_CTL_NORMAL);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x1B);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
+ ili9341WriteByte(lcdp, 0x0A);
+ ili9341WriteByte(lcdp, 0xA2);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_1);
+ ili9341WriteByte(lcdp, 0x10);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_2);
+ ili9341WriteByte(lcdp, 0x10);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_1);
+ ili9341WriteByte(lcdp, 0x45);
+ ili9341WriteByte(lcdp, 0x15);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_2);
+ ili9341WriteByte(lcdp, 0x90);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_MEM_ACS_CTL);
+ ili9341WriteByte(lcdp, 0xC8);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_RGB_IF_SIG_CTL);
+ ili9341WriteByte(lcdp, 0xC2);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
+ ili9341WriteByte(lcdp, 0x0A);
+ ili9341WriteByte(lcdp, 0xA7);
+ ili9341WriteByte(lcdp, 0x27);
+ ili9341WriteByte(lcdp, 0x04);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_COL_ADDR);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0xEF);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_PAGE_ADDR);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x01);
+ ili9341WriteByte(lcdp, 0x3F);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_IF_CTL);
+ ili9341WriteByte(lcdp, 0x01);
+ ili9341WriteByte(lcdp, 0x00);
+ ili9341WriteByte(lcdp, 0x06);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_GAMMA);
+ ili9341WriteByte(lcdp, 0x01);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_PGAMMA);
+ ili9341WriteChunk(lcdp, pgamma, 15);
+
+ ili9341WriteCommand(lcdp, ILI9341_SET_NGAMMA);
+ ili9341WriteChunk(lcdp, ngamma, 15);
+
+ ili9341WriteCommand(lcdp, ILI9341_CMD_SLEEP_OFF);
+ chThdSleepMilliseconds(10);
+
+ ili9341WriteCommand(lcdp, ILI9341_CMD_DISPLAY_ON);
+ ili9341WriteCommand(lcdp, ILI9341_SET_MEM);
+ chThdSleepMilliseconds(10);
+
+ ili9341Unselect(lcdp);
+ ili9341ReleaseBus(lcdp);
+}
+
+static const DMA2DConfig dma2d_cfg = {
+ /* ISR callbacks.*/
+ NULL, /**< Configuration error, or @p NULL.*/
+ NULL, /**< Palette transfer done, or @p NULL.*/
+ NULL, /**< Palette access error, or @p NULL.*/
+ NULL, /**< Transfer watermark, or @p NULL.*/
+ NULL, /**< Transfer complete, or @p NULL.*/
+ NULL /**< Transfer error, or @p NULL.*/
+};
+
+static const dma2d_palcfg_t dma2d_palcfg = {
+ wolf3d_palette,
+ 256,
+ DMA2D_FMT_ARGB8888
+};
+
+static const dma2d_laycfg_t dma2d_bg_laycfg = {
+ view_buffer,
+ 0,
+ DMA2D_FMT_L8,
+ DMA2D_COLOR_RED,
+ 0xFF,
+ &dma2d_palcfg
+};
+
+static const dma2d_laycfg_t dma2d_fg_laycfg = {
+ (void *)wolf3d_vgagraph_chunk87,
+ 0,
+ DMA2D_FMT_L8,
+ DMA2D_COLOR_LIME,
+ 0xFF,
+ &dma2d_palcfg
+};
+
+static const dma2d_laycfg_t dma2d_frame_laycfg = {
+ frame_buffer,
+ 0,
+ DMA2D_FMT_RGB888,
+ DMA2D_COLOR_BLUE,
+ 0xFF,
+ NULL
+};
+
+static void dma2d_test(void) {
+
+ DMA2DDriver *const dma2dp = &DMA2DD1;
+ LTDCDriver *const ltdcp = <DCD1;
+
+ chThdSleepSeconds(1);
+
+ ltdcBgSetConfig(ltdcp, <dc_screen_laycfg1);
+ ltdcReload(ltdcp, TRUE);
+
+ dma2dAcquireBus(dma2dp);
+
+ /* Target the frame buffer by default.*/
+ dma2dBgSetConfig(dma2dp, &dma2d_frame_laycfg);
+ dma2dFgSetConfig(dma2dp, &dma2d_frame_laycfg);
+ dma2dOutSetConfig(dma2dp, &dma2d_frame_laycfg);
+
+ /* Copy the background.*/
+ dma2dFgSetConfig(dma2dp, &dma2d_bg_laycfg);
+ dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
+ dma2dJobSetSize(dma2dp, 240, 320);
+ dma2dJobExecute(dma2dp);
+
+ /* Draw the splashscren picture at (8, 0).*/
+ dma2dFgSetConfig(dma2dp, &dma2d_fg_laycfg);
+ dma2dOutSetAddress(dma2dp, dma2dComputeAddress(
+ frame_buffer, ltdc_screen_frmcfg1.pitch, DMA2D_FMT_RGB888, 8, 0
+ ));
+ dma2dOutSetWrapOffset(dma2dp, ltdc_screen_frmcfg1.width - 200);
+ dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
+ dma2dJobSetSize(dma2dp, 200, 320);
+ dma2dJobExecute(dma2dp);
+
+ dma2dReleaseBus(dma2dp);
+}
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define RTT2MS(ticks) ((ticks) / (STM32_HCLK / 1000UL))
+
+#if HAL_USE_SERIAL_USB
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU1;
+#endif
+
+#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
+#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
+
+static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
+ size_t n, size;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: mem\r\n");
+ return;
+ }
+ n = chHeapStatus(NULL, &size);
+ chprintf(chp, "core free memory : %u bytes\r\n", chCoreGetStatusX());
+ chprintf(chp, "heap fragments : %u\r\n", n);
+ chprintf(chp, "heap free total : %u bytes\r\n", size);
+}
+
+static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static const char *states[] = {CH_STATE_NAMES};
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: threads\r\n");
+ return;
+ }
+ chprintf(chp, " addr stack prio refs state time\r\n");
+ tp = chRegFirstThread();
+ do {
+ chprintf(chp, "%08lx %08lx %4lu %4lu %9s\r\n",
+ (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
+ (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
+ states[tp->p_state]);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+
+static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
+ thread_t *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: test\r\n");
+ return;
+ }
+ tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
+ TestThread, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory\r\n");
+ return;
+ }
+ chThdWait(tp);
+}
+
+static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: reset\r\n");
+ return;
+ }
+
+ chprintf(chp, "Will reset in 200ms\r\n");
+ chThdSleepMilliseconds(200);
+ NVIC_SystemReset();
+}
+
+static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
+ uint32_t counter = 0;
+ uint8_t ubWritedata_8b = 0x3C;
+ uint32_t uwReadwritestatus = 0;
+ time_measurement_t tm;
+
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: write\r\n");
+ return;
+ }
+
+ chTMObjectInit(&tm);
+
+ chTMStartMeasurementX(&tm);
+
+ /* Write data value to all SDRAM memory */
+ for (counter = 0; counter < IS42S16400J_SIZE; counter++)
+ {
+ *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
+ }
+
+ chTMStopMeasurementX(&tm);
+ uint32_t write_ms = RTT2MS(tm.last);
+
+ if (!uwReadwritestatus) {
+ chprintf(chp, "SDRAM written in %dms.\r\n", write_ms);
+ }
+
+}
+
+static void cmd_erase(BaseSequentialStream *chp, int argc, char *argv[]) {
+ uint32_t counter = 0;
+ uint32_t uwReadwritestatus = 0;
+ time_measurement_t tm;
+
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: erase\r\n");
+ return;
+ }
+
+ chTMObjectInit(&tm);
+
+ //XXX chTMStartMeasurement(&tm);
+
+ /* Write data value to all SDRAM memory */
+ /* Erase SDRAM memory */
+ for (counter = 0; counter < IS42S16400J_SIZE; counter++)
+ {
+ *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
+ }
+
+ //XXX chTMStopMeasurement(&tm);
+ uint32_t write_ms = 0;//XXX RTT2MS(tm.last);
+
+ if (!uwReadwritestatus) {
+ chprintf(chp, "SDRAM erased in %dms.\r\n", write_ms);
+ }
+
+}
+
+static void cmd_selfrefresh(BaseSequentialStream *chp, int argc, char *argv[]) {
+ (void)argv;
+
+ FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: selfrefresh\r\n");
+ return;
+ }
+
+ /* Program a self-refresh mode command */
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_Selfrefresh;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
+
+ /* Send the command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
+ }
+
+ /* Check the bank mode status */
+ if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_SelfRefreshMode_Status) {
+ chprintf(chp, "SDRAM is not in self refresh mode, command FAILED.\r\n");
+ } else {
+ chprintf(chp, "SDRAM is in self refresh mode.\r\n");
+ }
+
+}
+
+static void cmd_normal(BaseSequentialStream *chp, int argc, char *argv[]) {
+ (void)argv;
+
+ FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
+
+ if (argc > 0) {
+ chprintf(chp, "Usage: normal\r\n");
+ return;
+ }
+
+ /* Program a self-refresh mode command */
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_normal;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
+
+ /* Send the command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
+ }
+
+ /* Check the bank mode status */
+ if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_NormalMode_Status) {
+ chprintf(chp, "SDRAM is not in normal mode, command FAILED.\r\n");
+ } else {
+ chprintf(chp, "SDRAM is in normal mode.\r\n");
+ }
+
+}
+
+static void cmd_check(BaseSequentialStream *chp, int argc, char *argv[]) {
+ uint32_t counter = 0;
+ uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
+ uint32_t uwReadwritestatus = 0;
+ time_measurement_t tm;
+
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: check\r\n");
+ return;
+ }
+
+ chTMObjectInit(&tm);
+
+ chTMStartMeasurementX(&tm);
+
+ /* Read back SDRAM memory and check content correctness*/
+ counter = 0;
+ uwReadwritestatus = 0;
+ while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
+ {
+ ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
+ if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
+ {
+ uwReadwritestatus = 1;
+ chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
+ }
+ counter++;
+ }
+
+ chTMStopMeasurementX(&tm);
+ uint32_t check_ms = RTT2MS(tm.last);
+
+ //FIXME time this
+ if (!uwReadwritestatus) {
+ chprintf(chp, "SDRAM read and check completed successfully in %dms.\r\n", check_ms);
+ }
+
+}
+
+static void cmd_sdram(BaseSequentialStream *chp, int argc, char *argv[]) {
+ uint32_t counter = 0;
+ uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
+ uint32_t uwReadwritestatus = 0;
+ time_measurement_t tm;
+
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: sdram\r\n");
+ return;
+ }
+
+ chTMObjectInit(&tm);
+
+ chTMStartMeasurementX(&tm);
+
+// /* Erase SDRAM memory */
+// for (counter = 0; counter < IS42S16400J_SIZE; counter++)
+// {
+// *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
+// }
+
+ /* Write data value to all SDRAM memory */
+ for (counter = 0; counter < IS42S16400J_SIZE; counter++)
+ {
+ *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
+ }
+
+ chTMStopMeasurementX(&tm);
+ uint32_t write_ms = RTT2MS(tm.last);
+
+ chTMStartMeasurementX(&tm);
+
+ /* Read back SDRAM memory */
+ counter = 0;
+ while ((counter < IS42S16400J_SIZE))
+ {
+ ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
+ counter++;
+ }
+
+ chTMStopMeasurementX(&tm);
+ uint32_t read_ms = RTT2MS(tm.last);
+
+ /* Read back SDRAM memory and check content correctness*/
+ counter = 0;
+ uwReadwritestatus = 0;
+ while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
+ {
+ ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
+ if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
+ {
+ uwReadwritestatus = 1;
+ chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
+ }
+ counter++;
+ }
+
+ if (!uwReadwritestatus) {
+ chprintf(chp, "SDRAM test completed successfully, writing entire memory took %dms, reading it took %dms.\r\n", write_ms, read_ms);
+ }
+
+}
+
+static const ShellCommand commands[] = {
+ {"mem", cmd_mem},
+ {"threads", cmd_threads},
+ {"test", cmd_test},
+ {"sdram", cmd_sdram},
+ {"reset", cmd_reset},
+ {"write", cmd_write},
+ {"check", cmd_check},
+ {"erase", cmd_erase},
+ {"selfrefresh", cmd_selfrefresh},
+ {"normal", cmd_normal},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+#if HAL_USE_SERIAL_USB
+ (BaseSequentialStream *)&SDU1,
+#else
+ (BaseSequentialStream *)&SD1,
+#endif
+ commands
+};
+
+/*===========================================================================*/
+/* Initialization and main thread. */
+/*===========================================================================*/
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ thread_t *shelltp = NULL;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+#if HAL_USE_SERIAL_USB
+ /*
+ * Initializes a serial-over-USB CDC driver.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ * Note, a delay is inserted in order to not have to disconnect the cable
+ * after a reset.
+ */
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(1000);
+ usbStart(serusbcfg.usbp, &usbcfg);
+ usbConnectBus(serusbcfg.usbp);
+#else
+ /*
+ * Initializes serial port.
+ */
+ sdStart(&SD1, NULL);
+#endif /* HAL_USE_SERIAL_USB */
+
+ /*
+ * Initialise SDRAM, board.h has already configured GPIO correctly (except that ST example uses 50MHz not 100MHz?)
+ */
+ SDRAM_Init();
+ sdram_bulk_erase();
+
+ /*
+ * Activates the LCD-related drivers.
+ */
+ spiStart(&SPID5, &spi_cfg5);
+ ili9341Start(&ILI9341D1, &ili9341_cfg);
+ initialize_lcd();
+ ltdcStart(<DCD1, <dc_cfg);
+
+ /*
+ * Activates the DMA2D-related drivers.
+ */
+ dma2dStart(&DMA2DD1, &dma2d_cfg);
+ dma2d_test();
+
+ /*
+ * Creating the blinker threads.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1),
+ NORMALPRIO + 10, Thread1, NULL);
+ chThdCreateStatic(waThread2, sizeof(waThread2),
+ NORMALPRIO + 10, Thread2, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it just performs
+ * a shell respawn upon its termination.
+ */
+ while (true) {
+ if (!shelltp) {
+#if HAL_USE_SERIAL_USB
+ if (SDU1.config->usbp->state == USB_ACTIVE) {
+ /* Spawns a new shell.*/
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ }
+#else
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+#endif
+ }
+ else {
+ /* If the previous shell exited.*/
+ if (chThdTerminatedX(shelltp)) {
+ /* Recovers memory of the previous shell.*/
+ chThdRelease(shelltp);
+ shelltp = NULL;
+ }
+ }
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h new file mode 100644 index 0000000..bac6cad --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h @@ -0,0 +1,355 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+#define STM32_SAISRC STM32_SAISRC_PLL
+#define STM32_PLLSAIN_VALUE 192
+#define STM32_PLLSAIQ_VALUE 7
+#define STM32_PLLSAIR_VALUE 4
+#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 TRUE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 TRUE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * LTDC driver system settings.
+ */
+#define STM32_LTDC_USE_LTDC TRUE
+#define STM32_LTDC_EV_IRQ_PRIORITY 11
+#define STM32_LTDC_ER_IRQ_PRIORITY 11
+
+/*
+ * DMA2D driver system settings.
+ */
+#define STM32_DMA2D_USE_DMA2D TRUE
+#define STM32_DMA2D_IRQ_PRIORITY 11
+
+#endif /* _MCUCONF_H_ */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt new file mode 100644 index 0000000..3342a4c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt @@ -0,0 +1,29 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M4 STM32F429. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an ST STM32F429I-Discovery board.
+
+** The Demo **
+
+A simple command shell is activated on virtual serial port SD1.
+The demo makes use of FMC, LTDC, and DMA2D peripherals to show graphical
+contents on the display of the board, composed both on the on-chip SRAM
+and the on-board SDRAM.
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO. just modify the TRGT line in the makefile in order to use
+different GCC toolchains.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin Binary files differnew file mode 100644 index 0000000..aee3942 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp Binary files differnew file mode 100644 index 0000000..c50e16b --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif Binary files differnew file mode 100644 index 0000000..4cb7105 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c new file mode 100644 index 0000000..6439a45 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c @@ -0,0 +1,4005 @@ +/* Generated by bin2c, do not edit manually */
+
+/* Contents of file chunk87.bin */
+const unsigned char wolf3d_vgagraph_chunk87[64000] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9F, 0x9F, 0x9F, 0x9F,
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+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D,
+ 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h new file mode 100644 index 0000000..6c0a15f --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h @@ -0,0 +1,9 @@ +/* Generated by bin2c, do not edit manually */
+#ifndef __wolf3d_vgagraph_chunk87_h_included
+#define __wolf3d_vgagraph_chunk87_h_included
+
+/* Contents of file chunk87.bin */
+#define wolf3d_vgagraph_chunk87_size 64000
+extern const unsigned char wolf3d_vgagraph_chunk87[64000];
+
+#endif /* __wolf3d_vgagraph_chunk87_h_included */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c new file mode 100644 index 0000000..77d9a15 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c @@ -0,0 +1,332 @@ +#include "ch.h"
+#include "hal.h"
+#include "stm32f429i_discovery_sdram.h"
+#include "stm32f4xx_fmc.h"
+
+/**
+ * @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
+ * This function must be called before any read/write operation
+ * on the SDRAM.
+ * @param None
+ * @retval None
+ */
+void SDRAM_Init(void)
+{
+ FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
+ FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
+
+ /* Enable FMC clock */
+ rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
+
+/* FMC Configuration ---------------------------------------------------------*/
+/* FMC SDRAM Bank configuration */
+ /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
+ /* TMRD: 2 Clock cycles */
+ FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
+ /* TXSR: min=70ns (6x11.90ns) */
+ FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
+ /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
+ FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
+ /* TRC: min=63 (6x11.90ns) */
+ FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
+ /* TWR: 2 Clock cycles */
+ FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
+ /* TRP: 15ns => 2x11.90ns */
+ FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
+ /* TRCD: 15ns => 2x11.90ns */
+ FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
+
+/* FMC SDRAM control configuration */
+ FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
+ /* Row addressing: [7:0] */
+ FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
+ /* Column addressing: [11:0] */
+ FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
+ FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
+ FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
+ FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
+ FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
+ FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
+ FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
+ FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
+ FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
+
+ /* FMC SDRAM bank initialization */
+ FMC_SDRAMInit(&FMC_SDRAMInitStructure);
+
+ /* FMC SDRAM device initialization sequence */
+ SDRAM_InitSequence();
+
+}
+
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+--------------------+--------------------+
+ + SDRAM pins assignment +
+ +-------------------+--------------------+--------------------+--------------------+
+ | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
+ | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
+ | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
+ | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
+ | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
+ | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
+ | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
+ +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
+ | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
+ | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
+ | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
+ +-------------------+--------------------+--------------------+
+ | PB5 <-> FMC_SDCKE1|
+ | PB6 <-> FMC_SDNE1 |
+ | PC0 <-> FMC_SDNWE |
+ +-------------------+
+
+*/
+
+// /* Common GPIO configuration */
+// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+//
+// /* GPIOB configuration */
+// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
+//
+// GPIO_Init(GPIOB, &GPIO_InitStructure);
+//
+// /* GPIOC configuration */
+// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+//
+// GPIO_Init(GPIOC, &GPIO_InitStructure);
+//
+// /* GPIOD configuration */
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
+// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
+// GPIO_Pin_15;
+//
+// GPIO_Init(GPIOD, &GPIO_InitStructure);
+//
+// /* GPIOE configuration */
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
+// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
+// GPIO_Pin_14 | GPIO_Pin_15;
+//
+// GPIO_Init(GPIOE, &GPIO_InitStructure);
+//
+// /* GPIOF configuration */
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
+// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
+// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
+// GPIO_Pin_14 | GPIO_Pin_15;
+//
+// GPIO_Init(GPIOF, &GPIO_InitStructure);
+//
+// /* GPIOG configuration */
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
+// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
+//
+//
+// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
+// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
+//
+// GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+/**
+ * @brief Executes the SDRAM memory initialization sequence.
+ * @param None.
+ * @retval None.
+ */
+void SDRAM_InitSequence(void)
+{
+ FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
+ uint32_t tmpr = 0;
+
+/* Step 3 --------------------------------------------------------------------*/
+ /* Configure a clock configuration enable command */
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+ /* Send the command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
+ //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
+ //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
+ //mode
+/* Step 4 --------------------------------------------------------------------*/
+ /* Insert 1 ms delay */
+ chThdSleepMilliseconds(1);
+
+/* Step 5 --------------------------------------------------------------------*/
+ /* Configure a PALL (precharge all) command */
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+ /* Send the command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+/* Step 6 --------------------------------------------------------------------*/
+ /* Configure a Auto-Refresh command */
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+ /* Send the first command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+ /* Send the second command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+/* Step 7 --------------------------------------------------------------------*/
+ /* Program the external memory mode register */
+ tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
+ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
+ SDRAM_MODEREG_CAS_LATENCY_3 |
+ SDRAM_MODEREG_OPERATING_MODE_STANDARD |
+ SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+
+ /* Configure a load Mode register command*/
+ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
+ FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
+ FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
+ FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+ /* Send the command */
+ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+/* Step 8 --------------------------------------------------------------------*/
+
+ /* Set the refresh rate counter */
+ /* (7.81 us x Freq) - 20 */
+ /* Set the device refresh counter */
+ FMC_SetRefreshCount(683);
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+}
+
+
+/**
+ * @brief Writes a Entire-word buffer to the SDRAM memory.
+ * @param pBuffer: pointer to buffer.
+ * @param uwWriteAddress: SDRAM memory internal address from which the data will be
+ * written.
+ * @param uwBufferSize: number of words to write.
+ * @retval None.
+ */
+void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
+{
+ __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
+
+ /* Disable write protection */
+ FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
+
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+
+ /* While there is data to write */
+ for (; uwBufferSize != 0; uwBufferSize--)
+ {
+ /* Transfer data to the memory */
+ *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
+
+ /* Increment the address*/
+ write_pointer += 4;
+ }
+
+}
+
+/**
+ * @brief Reads data buffer from the SDRAM memory.
+ * @param pBuffer: pointer to buffer.
+ * @param ReadAddress: SDRAM memory internal address from which the data will be
+ * read.
+ * @param uwBufferSize: number of words to write.
+ * @retval None.
+ */
+void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
+{
+ __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
+
+
+ /* Wait until the SDRAM controller is ready */
+ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
+ {
+ }
+
+ /* Read data */
+ for(; uwBufferSize != 0x00; uwBufferSize--)
+ {
+ *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
+
+ /* Increment the address*/
+ write_pointer += 4;
+ }
+}
+
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h new file mode 100644 index 0000000..70688d9 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h @@ -0,0 +1,96 @@ +/**
+ ******************************************************************************
+ * @file stm32f429i_discovery_sdram.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 20-September-2013
+ * @brief This file contains all the functions prototypes for the
+ * stm324x9i_disco_sdram.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32429I_DISCO_SDRAM_H
+#define __STM32429I_DISCO_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//FIXME this should not be needed
+#define STM32F429_439xx
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/**
+ * @brief FMC SDRAM Bank address
+ */
+#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
+
+/**
+ * @brief FMC SDRAM Memory Width
+ */
+/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
+#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
+
+/**
+ * @brief FMC SDRAM CAS Latency
+ */
+/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
+#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
+
+/**
+ * @brief FMC SDRAM Memory clock period
+ */
+#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
+/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
+
+/**
+ * @brief FMC SDRAM Memory Read Burst feature
+ */
+#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
+/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
+
+/**
+ * @brief FMC SDRAM Mode definition register defines
+ */
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
+void SDRAM_Init(void);
+void SDRAM_InitSequence(void);
+void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
+void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c new file mode 100644 index 0000000..1f7ce5d --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c @@ -0,0 +1,1379 @@ +/**
+ ******************************************************************************
+ * @file stm32f4xx_fmc.c
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 19-September-2013
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the FMC peripheral:
+ * + Interface with SRAM, PSRAM, NOR and OneNAND memories
+ * + Interface with NAND memories
+ * + Interface with 16-bit PC Card compatible memories
+ * + Interface with SDRAM memories
+ * + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_fmc.h"
+#include "ch.h"
+//#include "stm32f4xx_rcc.h"
+
+#define FMC_Bank2 FMC_Bank2_3
+#define FMC_Bank3 FMC_Bank2_3
+
+#define assert_param(expr) chDbgAssert(expr, "STPeriph FMC")
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FMC
+ * @brief FMC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* --------------------- FMC registers bit mask ---------------------------- */
+/* FMC BCRx Mask */
+#define BCR_MBKEN_SET ((uint32_t)0x00000001)
+#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_SET ((uint32_t)0x00000040)
+
+/* FMC PCRx Mask */
+#define PCR_PBKEN_SET ((uint32_t)0x00000004)
+#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_SET ((uint32_t)0x00000040)
+#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
+#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
+
+/* FMC SDCRx write protection Mask*/
+#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF)
+
+/* FMC SDCMR Mask*/
+#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF)
+#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7)
+#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FMC_Private_Functions
+ * @{
+ */
+
+/** @defgroup FMC_Group1 NOR/SRAM Controller functions
+ * @brief NOR/SRAM Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### NOR and SRAM Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_NORSRAMInitTypeDef structure, for example:
+ FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure;
+ and fill the FMC_NORSRAMInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the NOR/SRAM Controller by calling the function
+ FMC_NORSRAMInit(&FMC_NORSRAMInitStructure);
+
+ (#) Then enable the NOR/SRAM Bank, for example:
+ FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
+ * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
+ * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
+ * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
+
+ /* FMC_Bank1_NORSRAM1 */
+ if(FMC_Bank == FMC_Bank1_NORSRAM1)
+ {
+ FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB;
+ }
+ /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */
+ else
+ {
+ FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2;
+ }
+ FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF;
+ FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Initializes the FMC NOR/SRAM Banks according to the specified
+ * parameters in the FMC_NORSRAMInitStruct.
+ * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure
+ * that contains the configuration information for the FMC NOR/SRAM
+ * specified Banks.
+ * @retval None
+ */
+void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
+ assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux));
+ assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity));
+ assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode));
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
+
+ /* NOR/SRAM Bank control register configuration */
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
+ (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
+ FMC_NORSRAMInitStruct->FMC_MemoryType |
+ FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
+ FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
+ FMC_NORSRAMInitStruct->FMC_WrapMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
+ FMC_NORSRAMInitStruct->FMC_WriteOperation |
+ FMC_NORSRAMInitStruct->FMC_WaitSignal |
+ FMC_NORSRAMInitStruct->FMC_ExtendedMode |
+ FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
+ FMC_NORSRAMInitStruct->FMC_WriteBurst |
+ FMC_NORSRAMInitStruct->FMC_ContinousClock;
+
+
+ if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
+ {
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
+ }
+
+ /* Configure Continuous clock feature when bank2..4 is used */
+ if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
+ {
+ tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20));
+
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
+ }
+
+ /* NOR/SRAM Bank timing register configuration */
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
+ (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
+ ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
+ ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
+
+ /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
+ if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
+ assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
+
+ FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
+ (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
+ ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
+ ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
+ }
+ else
+ {
+ FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF;
+ }
+
+}
+
+/**
+ * @brief Fills each FMC_NORSRAMInitStruct member with its default value.
+ * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1;
+ FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable;
+ FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM;
+ FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
+ FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
+ FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
+ FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable;
+ FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
+ FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
+
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
+ * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
+ * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
+ * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group2 NAND Controller functions
+ * @brief NAND Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### NAND Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with 8-bit or 16-bit NAND memory connected to the NAND Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_NANDInitTypeDef structure, for example:
+ FMC_NANDInitTypeDef FMC_NANDInitStructure;
+ and fill the FMC_NANDInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the NAND Controller by calling the function
+ FMC_NANDInit(&FMC_NANDInitStructure);
+
+ (#) Then enable the NAND Bank, for example:
+ FMC_NANDCmd(FMC_Bank3_NAND, ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
+
+ [..]
+ (@) To enable the Error Correction Code (ECC), you have to use the function
+ FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE);
+ [..]
+ (@) and to get the current ECC value you have to use the function
+ ECCval = FMC_GetECC(FMC_Bank3_NAND);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC NAND Banks registers to their default reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @retval None
+ */
+void FMC_NANDDeInit(uint32_t FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Set the FMC_Bank2 registers to their reset values */
+ FMC_Bank2->PCR2 = 0x00000018;
+ FMC_Bank2->SR2 = 0x00000040;
+ FMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FMC_Bank3_NAND */
+ else
+ {
+ /* Set the FMC_Bank3 registers to their reset values */
+ FMC_Bank3->PCR3 = 0x00000018;
+ FMC_Bank3->SR3 = 0x00000040;
+ FMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Initializes the FMC NAND Banks according to the specified parameters
+ * in the FMC_NANDInitStruct.
+ * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that
+ * contains the configuration information for the FMC NAND specified Banks.
+ * @retval None
+ */
+void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
+{
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
+ assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC));
+ assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
+ tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
+ PCR_MEMORYTYPE_NAND |
+ FMC_NANDInitStruct->FMC_MemoryDataWidth |
+ FMC_NANDInitStruct->FMC_ECC |
+ FMC_NANDInitStruct->FMC_ECCPageSize |
+ (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
+ (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* FMC_Bank2_NAND registers configuration */
+ FMC_Bank2->PCR2 = tmppcr;
+ FMC_Bank2->PMEM2 = tmppmem;
+ FMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FMC_Bank3_NAND registers configuration */
+ FMC_Bank3->PCR3 = tmppcr;
+ FMC_Bank3->PMEM3 = tmppmem;
+ FMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+
+/**
+ * @brief Fills each FMC_NANDInitStruct member with its default value.
+ * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND;
+ FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
+ FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b;
+ FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable;
+ FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes;
+ FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0;
+ FMC_NANDInitStruct->FMC_TARSetupTime = 0x0;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 |= PCR_PBKEN_SET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 |= PCR_PBKEN_SET;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
+ }
+ }
+}
+/**
+ * @brief Enables or disables the FMC NAND ECC feature.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @param NewState: new state of the FMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 |= PCR_ECCEN_SET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 |= PCR_ECCEN_SET;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+uint32_t FMC_GetECC(uint32_t FMC_Bank)
+{
+ uint32_t eccval = 0x00000000;
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group3 PCCARD Controller functions
+ * @brief PCCARD Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### PCCARD Controller functions #####
+ ===============================================================================
+
+ [..] he following sequence should be followed to configure the FMC to interface
+ with 16-bit PC Card compatible memory connected to the PCCARD Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_PCCARDInitTypeDef structure, for example:
+ FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure;
+ and fill the FMC_PCCARDInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the PCCARD Controller by calling the function
+ FMC_PCCARDInit(&FMC_PCCARDInitStructure);
+
+ (#) Then enable the PCCARD Bank:
+ FMC_PCCARDCmd(ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FMC_PCCARDDeInit(void)
+{
+ /* Set the FMC_Bank4 registers to their reset values */
+ FMC_Bank4->PCR4 = 0x00000018;
+ FMC_Bank4->SR4 = 0x00000000;
+ FMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FMC PCCARD Bank according to the specified parameters
+ * in the FMC_PCCARDInitStruct.
+ * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure
+ * that contains the configuration information for the FMC PCCARD Bank.
+ * @retval None
+ */
+void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
+ assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime));
+
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
+
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
+ FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
+ FMC_NAND_MemoryDataWidth_16b |
+ (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
+ (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
+ FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
+ FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
+ FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FMC_PCCARDInitStruct member with its default value.
+ * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
+ FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0;
+ FMC_PCCARDInitStruct->FMC_TARSetupTime = 0;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252;
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FMC_Bank4->PCR4 |= PCR_PBKEN_SET;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group4 SDRAM Controller functions
+ * @brief SDRAM Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### SDRAM Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_SDRAMInitTypeDef structure, for example:
+ FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
+ and fill the FMC_SDRAMInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the SDRAM Controller by calling the function
+ FMC_SDRAMInit(&FMC_SDRAMInitStructure);
+
+ (#) Declare a FMC_SDRAMCommandTypeDef structure, for example:
+ FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
+ and fill the FMC_SDRAMCommandStructure variable with the allowed values of
+ the structure member.
+
+ (#) Configure the SDCMR register with the desired command parameters by calling
+ the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ (#) At this stage, the SDRAM memory is ready for any valid command.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC SDRAM Banks registers to their default
+ * reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @retval None
+ */
+void FMC_SDRAMDeInit(uint32_t FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
+
+ FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0;
+ FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF;
+ FMC_Bank5_6->SDCMR = 0x00000000;
+ FMC_Bank5_6->SDRTR = 0x00000000;
+ FMC_Bank5_6->SDSR = 0x00000000;
+}
+
+/**
+ * @brief Initializes the FMC SDRAM Banks according to the specified
+ * parameters in the FMC_SDRAMInitStruct.
+ * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure
+ * that contains the configuration information for the FMC SDRAM
+ * specified Banks.
+ * @retval None
+ */
+void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
+{
+ /* temporary registers */
+ uint32_t tmpr1 = 0;
+ uint32_t tmpr2 = 0;
+ uint32_t tmpr3 = 0;
+ uint32_t tmpr4 = 0;
+
+ /* Check the parameters */
+
+ /* Control parameters */
+ assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank));
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber));
+ assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber));
+ assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth));
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber));
+ assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency));
+ assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection));
+ assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod));
+ assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst));
+ assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay));
+
+ /* Timing parameters */
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay));
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay));
+ assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime));
+ assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay));
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime));
+ assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
+ assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
+
+ /* SDRAM bank control register configuration */
+ tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
+ FMC_SDRAMInitStruct->FMC_RowBitsNumber |
+ FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
+ FMC_SDRAMInitStruct->FMC_InternalBankNumber |
+ FMC_SDRAMInitStruct->FMC_CASLatency |
+ FMC_SDRAMInitStruct->FMC_WriteProtection |
+ FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+
+ if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
+ {
+ FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
+ }
+ else /* SDCR2 "don't care" bits configuration */
+ {
+ tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+
+ FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
+ FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
+ }
+ /* SDRAM bank timing register configuration */
+ if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
+ {
+ tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
+
+ FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
+ }
+ else /* SDTR "don't care bits configuration */
+ {
+ tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
+
+ tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
+
+ FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
+ FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
+ }
+
+}
+
+/**
+ * @brief Fills each FMC_SDRAMInitStruct member with its default value.
+ * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
+{
+ /* Reset SDRAM Init structure parameters values */
+ FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM;
+ FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
+ FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b;
+ FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
+ FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4;
+ FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1;
+ FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable;
+ FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable;
+ FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable;
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
+
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16;
+
+}
+
+/**
+ * @brief Configures the SDRAM memory command issued when the device is accessed.
+ * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure
+ * which will be configured.
+ * @retval None
+ */
+void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
+{
+ uint32_t tmpr = 0x0;
+
+ /* check parameters */
+ assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
+ assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget));
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
+ assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
+
+ tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode |
+ FMC_SDRAMCommandStruct->FMC_CommandTarget |
+ (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
+ ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
+
+ FMC_Bank5_6->SDCMR = tmpr;
+
+}
+
+
+/**
+ * @brief Returns the indicated FMC SDRAM bank mode status.
+ * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+ * @retval The FMC SDRAM bank mode status
+ */
+uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameter */
+ assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
+
+ /* Get the busy flag status */
+ if(SDRAM_Bank == FMC_Bank1_SDRAM)
+ {
+ tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
+ }
+ else
+ {
+ tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
+ }
+
+ /* Return the mode status */
+ return tmpreg;
+}
+
+/**
+ * @brief defines the SDRAM Memory Refresh rate.
+ * @param FMC_Count: specifies the Refresh timer count.
+ * @retval None
+ */
+void FMC_SetRefreshCount(uint32_t FMC_Count)
+{
+ /* check the parameters */
+ assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
+
+ FMC_Bank5_6->SDRTR |= (FMC_Count<<1);
+
+}
+
+/**
+ * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+ * @param FMC_Number: specifies the auto Refresh number.
+ * @retval None
+ */
+void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
+{
+ /* check the parameters */
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
+
+ FMC_Bank5_6->SDCMR |= (FMC_Number << 5);
+}
+
+/**
+ * @brief Enables or disables write protection to the specified FMC SDRAM Bank.
+ * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+ * @param NewState: new state of the write protection flag.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState)
+{
+ /* Check the parameter */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
+
+ if (NewState != DISABLE)
+ {
+ FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable;
+ }
+ else
+ {
+ FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET;
+ }
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group5 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified FMC interrupts.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @param NewState: new state of the specified FMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_IT(FMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FMC_Bank2 interrupts */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank3 interrupts */
+ else if (FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank4 interrupts */
+ else if (FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank5_6 interrupt */
+ else
+ {
+ /* Enables the interrupt if the refresh error flag is set */
+ FMC_Bank5_6->SDRTR |= FMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FMC_Bank2 interrupts */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+
+ FMC_Bank2->SR2 &= (uint32_t)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank3 interrupts */
+ else if (FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= (uint32_t)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank4 interrupts */
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= (uint32_t)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank5_6 interrupt */
+ else
+ {
+ /* Disables the interrupt if the refresh error flag is not set */
+ FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FMC flag is set or not.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM
+ * @param FMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
+ * @arg FMC_FLAG_Level: Level detection Flag.
+ * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
+ * @arg FMC_FLAG_FEMPT: Fifo empty Flag.
+ * @arg FMC_FLAG_Refresh: Refresh error Flag.
+ * @arg FMC_FLAG_Busy: Busy status Flag.
+ * @retval The new state of FMC_FLAG (SET or RESET).
+ */
+FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
+ assert_param(IS_FMC_GET_FLAG(FMC_FLAG));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ tmpsr = FMC_Bank2->SR2;
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ tmpsr = FMC_Bank3->SR3;
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ tmpsr = FMC_Bank4->SR4;
+ }
+ else
+ {
+ tmpsr = FMC_Bank5_6->SDSR;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FMC_FLAG) != FMC_FLAG )
+ {
+ bitstatus = RESET;
+ }
+ else
+ {
+ bitstatus = SET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FMC's pending flags.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
+ * @arg FMC_FLAG_Level: Level detection Flag.
+ * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
+ * @arg FMC_FLAG_Refresh: Refresh error Flag.
+ * @retval None
+ */
+void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
+ assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ;
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 &= (~FMC_FLAG);
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= (~FMC_FLAG);
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= (~FMC_FLAG);
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ FMC_Bank5_6->SDRTR &= (~FMC_FLAG);
+ }
+
+}
+
+/**
+ * @brief Checks whether the specified FMC interrupt has occurred or not.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the FMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @retval The new state of FMC_IT (SET or RESET).
+ */
+ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x0;
+ uint32_t tmpsr2 = 0x0;
+ uint32_t itstatus = 0x0;
+ uint32_t itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_GET_IT(FMC_IT));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ tmpsr = FMC_Bank2->SR2;
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ tmpsr = FMC_Bank3->SR3;
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ tmpsr = FMC_Bank4->SR4;
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ tmpsr = FMC_Bank5_6->SDRTR;
+ tmpsr2 = FMC_Bank5_6->SDSR;
+ }
+
+ /* get the IT enable bit status*/
+ itenable = tmpsr & FMC_IT;
+
+ /* get the corresponding IT Flag status*/
+ if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM))
+ {
+ itstatus = tmpsr2 & FMC_SDSR_RE;
+ }
+ else
+ {
+ itstatus = tmpsr & (FMC_IT >> 3);
+ }
+
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FMC's interrupt pending bits.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @retval None
+ */
+void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_IT(FMC_IT));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 &= ~(FMC_IT >> 3);
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= ~(FMC_IT >> 3);
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= ~(FMC_IT >> 3);
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h new file mode 100644 index 0000000..319f53c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h @@ -0,0 +1,1144 @@ +/**
+ ******************************************************************************
+ * @file stm32f4xx_fmc.h
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 19-September-2013
+ * @brief This file contains all the functions prototypes for the FMC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FMC_H
+#define __STM32F4xx_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//FIXME this should not be needed
+#define STM32F429_439xx
+
+/* Includes ------------------------------------------------------------------*/
+#include "ch.h"
+#include "stm32f4xx.h"
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+typedef struct
+{
+ uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 1 and 15.
+ @note This parameter is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 1 and 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 15.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 15 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+}FMC_NORSRAMTimingInitTypeDef;
+
+/**
+ * @brief FMC NOR/SRAM Init structure definition
+ */
+typedef struct
+{
+ uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode */
+
+ uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+
+ FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
+
+ FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
+}FMC_NORSRAMInitTypeDef;
+
+/**
+ * @brief Timing parameters For FMC NAND and PCCARD Banks
+ */
+typedef struct
+{
+ uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between 0 and 255.*/
+
+ uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ databus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between 0 and 255 */
+}FMC_NAND_PCCARDTimingInitTypeDef;
+
+/**
+ * @brief FMC NAND Init structure definition
+ */
+typedef struct
+{
+ uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 255. */
+
+ uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0 and 255 */
+
+ FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
+
+ FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
+}FMC_NANDInitTypeDef;
+
+/**
+ * @brief FMC PCCARD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 255. */
+
+ uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0 and 255 */
+
+
+ FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
+
+ FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
+
+ FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
+}FMC_PCCARDInitTypeDef;
+
+/**
+ * @brief Timing parameters for FMC SDRAM Banks
+ */
+
+typedef struct
+{
+ uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
+ an active or Refresh command in number of memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
+ issuing the Activate command in number of memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
+ cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
+ and the delay between two consecutive Refresh commands in number of
+ memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command
+ in number of memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command
+ in number of memory clock cycles.
+ This parameter can be a value between 1 and 16. */
+
+}FMC_SDRAMTimingInitTypeDef;
+
+/**
+ * @brief Command parameters for FMC SDRAM Banks
+ */
+
+
+typedef struct
+{
+ uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device.
+ This parameter can be a value of @ref FMC_Command_Mode. */
+
+ uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to.
+ This parameter can be a value of @ref FMC_Command_Target. */
+
+ uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
+ in auto refresh mode.
+ This parameter can be a value between 1 and 16. */
+
+ uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
+
+}FMC_SDRAMCommandTypeDef;
+
+/**
+ * @brief FMC SDRAM Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used.
+ This parameter can be a value of @ref FMC_SDRAM_Bank */
+
+ uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_ColumnBits_Number. */
+
+ uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address..
+ This parameter can be a value of @ref FMC_RowBits_Number. */
+
+ uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width.
+ This parameter can be a value of @ref FMC_SDMemory_Data_Width. */
+
+ uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address.
+ This parameter can be of @ref FMC_InternalBank_Number. */
+
+ uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+ This parameter can be a value of @ref FMC_CAS_Latency. */
+
+ uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode.
+ This parameter can be a value of @ref FMC_Write_Protection. */
+
+ uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable
+ the clock before changing frequency.
+ This parameter can be a value of @ref FMC_SDClock_Period. */
+
+ uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands
+ during the CAS latency and stores data in the Read FIFO.
+ This parameter can be a value of @ref FMC_Read_Burst. */
+
+ uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
+ This parameter can be a value of @ref FMC_ReadPipe_Delay. */
+
+ FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/
+
+}FMC_SDRAMInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank
+ * @{
+ */
+#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
+ ((BANK) == FMC_Bank1_NORSRAM2) || \
+ ((BANK) == FMC_Bank1_NORSRAM3) || \
+ ((BANK) == FMC_Bank1_NORSRAM4))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Bank
+ * @{
+ */
+#define FMC_Bank2_NAND ((uint32_t)0x00000010)
+#define FMC_Bank3_NAND ((uint32_t)0x00000100)
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
+ ((BANK) == FMC_Bank3_NAND))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Bank
+ * @{
+ */
+#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Bank
+ * @{
+ */
+#define FMC_Bank1_SDRAM ((uint32_t)0x00000000)
+#define FMC_Bank2_SDRAM ((uint32_t)0x00000001)
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \
+ ((BANK) == FMC_Bank2_SDRAM))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+
+#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
+ ((MUX) == FMC_DataAddressMux_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type
+ * @{
+ */
+
+#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
+
+#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
+ ((MEMORY) == FMC_MemoryType_PSRAM)|| \
+ ((MEMORY) == FMC_MemoryType_NOR))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width
+ * @{
+ */
+
+#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
+#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020)
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
+ ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \
+ ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+
+#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
+ ((STATE) == FMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait
+ * @{
+ */
+#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
+#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
+
+#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
+ ((STATE) == FMC_AsynchronousWait_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+
+#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FMC_WaitSignalPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode
+ * @{
+ */
+#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
+
+#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
+ ((MODE) == FMC_WrapMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing
+ * @{
+ */
+#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation
+ * @{
+ */
+#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
+
+#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
+ ((OPERATION) == FMC_WriteOperation_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal
+ * @{
+ */
+#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
+
+#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FMC_WaitSignal_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode
+ * @{
+ */
+#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
+#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
+ ((MODE) == FMC_ExtendedMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst
+ * @{
+ */
+
+#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
+
+#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
+ ((BURST) == FMC_WriteBurst_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock
+ * @{
+ */
+
+#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
+#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
+ ((CCLOCK) == FMC_CClock_SyncAsync))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_CLK_Division
+ * @{
+ */
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode
+ * @{
+ */
+#define FMC_AccessMode_A ((uint32_t)0x00000000)
+#define FMC_AccessMode_B ((uint32_t)0x10000000)
+#define FMC_AccessMode_C ((uint32_t)0x20000000)
+#define FMC_AccessMode_D ((uint32_t)0x30000000)
+
+#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
+ ((MODE) == FMC_AccessMode_B) || \
+ ((MODE) == FMC_AccessMode_C) || \
+ ((MODE) == FMC_AccessMode_D))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_PCCARD_Controller
+ * @{
+ */
+
+/** @defgroup FMC_Wait_feature
+ * @{
+ */
+#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
+#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
+ ((FEATURE) == FMC_Waitfeature_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width
+ * @{
+ */
+#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
+ ((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC
+ * @{
+ */
+#define FMC_ECC_Disable ((uint32_t)0x00000000)
+#define FMC_ECC_Enable ((uint32_t)0x00000040)
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
+ ((STATE) == FMC_ECC_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size
+ * @{
+ */
+#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
+ ((SIZE) == FMC_ECCPageSize_512Bytes) || \
+ ((SIZE) == FMC_ECCPageSize_1024Bytes) || \
+ ((SIZE) == FMC_ECCPageSize_2048Bytes) || \
+ ((SIZE) == FMC_ECCPageSize_4096Bytes) || \
+ ((SIZE) == FMC_ECCPageSize_8192Bytes))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_ColumnBits_Number
+ * @{
+ */
+#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \
+ ((COLUMN) == FMC_ColumnBits_Number_9b) || \
+ ((COLUMN) == FMC_ColumnBits_Number_10b) || \
+ ((COLUMN) == FMC_ColumnBits_Number_11b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_RowBits_Number
+ * @{
+ */
+#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \
+ ((ROW) == FMC_RowBits_Number_12b) || \
+ ((ROW) == FMC_RowBits_Number_13b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDMemory_Data_Width
+ * @{
+ */
+#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \
+ ((WIDTH) == FMC_SDMemory_Width_16b) || \
+ ((WIDTH) == FMC_SDMemory_Width_32b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_InternalBank_Number
+ * @{
+ */
+#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \
+ ((NUMBER) == FMC_InternalBank_Number_4))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_CAS_Latency
+ * @{
+ */
+#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \
+ ((LATENCY) == FMC_CAS_Latency_2) || \
+ ((LATENCY) == FMC_CAS_Latency_3))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Protection
+ * @{
+ */
+#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \
+ ((WRITE) == FMC_Write_Protection_Enable))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_SDClock_Period
+ * @{
+ */
+#define FMC_SDClock_Disable ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \
+ ((PERIOD) == FMC_SDClock_Period_2) || \
+ ((PERIOD) == FMC_SDClock_Period_3))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Read_Burst
+ * @{
+ */
+#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \
+ ((RBURST) == FMC_Read_Burst_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ReadPipe_Delay
+ * @{
+ */
+#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \
+ ((DELAY) == FMC_ReadPipe_Delay_1) || \
+ ((DELAY) == FMC_ReadPipe_Delay_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LoadToActive_Delay
+ * @{
+ */
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ExitSelfRefresh_Delay
+ * @{
+ */
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SelfRefresh_Time
+ * @{
+ */
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_RowCycle_Delay
+ * @{
+ */
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Recovery_Time
+ * @{
+ */
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_RP_Delay
+ * @{
+ */
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_RCD_Delay
+ * @{
+ */
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Command_Mode
+ * @{
+ */
+#define FMC_Command_Mode_normal ((uint32_t)0x00000000)
+#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001)
+#define FMC_Command_Mode_PALL ((uint32_t)0x00000002)
+#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003)
+#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004)
+#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005)
+#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006)
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \
+ ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \
+ ((COMMAND) == FMC_Command_Mode_PALL) || \
+ ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \
+ ((COMMAND) == FMC_Command_Mode_LoadMode) || \
+ ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \
+ ((COMMAND) == FMC_Command_Mode_PowerDown))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Command_Target
+ * @{
+ */
+#define FMC_Command_Target_bank2 ((uint32_t)0x00000008)
+#define FMC_Command_Target_bank1 ((uint32_t)0x00000010)
+#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018)
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \
+ ((TARGET) == FMC_Command_Target_bank2) || \
+ ((TARGET) == FMC_Command_Target_bank1_2))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AutoRefresh_Number
+ * @{
+ */
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ModeRegister_Definition
+ * @{
+ */
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_Mode_Status
+ * @{
+ */
+#define FMC_NormalMode_Status ((uint32_t)0x00000000)
+#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0
+#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1
+
+#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \
+ ((STATUS) == FMC_SelfRefreshMode_Status) || \
+ ((STATUS) == FMC_PowerDownMode_Status))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt_sources
+ * @{
+ */
+#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
+#define FMC_IT_Level ((uint32_t)0x00000010)
+#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
+#define FMC_IT_Refresh ((uint32_t)0x00004000)
+
+#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
+ ((IT) == FMC_IT_Level) || \
+ ((IT) == FMC_IT_FallingEdge) || \
+ ((IT) == FMC_IT_Refresh))
+
+#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
+ ((BANK) == FMC_Bank3_NAND) || \
+ ((BANK) == FMC_Bank4_PCCARD) || \
+ ((BANK) == FMC_Bank1_SDRAM) || \
+ ((BANK) == FMC_Bank2_SDRAM))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Flags
+ * @{
+ */
+#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+#define FMC_FLAG_Level ((uint32_t)0x00000002)
+#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_FLAG_Refresh FMC_SDSR_RE
+#define FMC_FLAG_Busy FMC_SDSR_BUSY
+
+#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
+ ((FLAG) == FMC_FLAG_Level) || \
+ ((FLAG) == FMC_FLAG_FallingEdge) || \
+ ((FLAG) == FMC_FLAG_FEMPT) || \
+ ((FLAG) == FMC_FLAG_Refresh) || \
+ ((FLAG) == FMC_SDSR_BUSY))
+
+#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
+ ((BANK) == FMC_Bank3_NAND) || \
+ ((BANK) == FMC_Bank4_PCCARD) || \
+ ((BANK) == FMC_Bank1_SDRAM) || \
+ ((BANK) == FMC_Bank2_SDRAM) || \
+ ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM)))
+
+#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Refresh_count
+ * @{
+ */
+#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* NOR/SRAM Controller functions **********************************************/
+void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
+void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
+void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
+void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
+
+/* NAND Controller functions **************************************************/
+void FMC_NANDDeInit(uint32_t FMC_Bank);
+void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
+void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
+void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
+void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
+uint32_t FMC_GetECC(uint32_t FMC_Bank);
+
+/* PCCARD Controller functions ************************************************/
+void FMC_PCCARDDeInit(void);
+void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
+void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
+void FMC_PCCARDCmd(FunctionalState NewState);
+
+/* SDRAM Controller functions ************************************************/
+void FMC_SDRAMDeInit(uint32_t FMC_Bank);
+void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
+void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
+void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct);
+uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank);
+void FMC_SetRefreshCount(uint32_t FMC_Count);
+void FMC_SetAutoRefresh_Number(uint32_t FMC_Number);
+void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
+FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
+void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
+ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
+void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_FMC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c new file mode 100644 index 0000000..9f95a2a --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c @@ -0,0 +1,314 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Endpoints to be used for USBD2.
+ */
+#define USBD2_DATA_REQUEST_EP 1
+#define USBD2_DATA_AVAILABLE_EP 1
+#define USBD2_INTERRUPT_REQUEST_EP 2
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0483, /* idVendor (ST). */
+ 0x5740, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 3 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(38), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+ 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+ 'c', 0, 's', 0
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(56), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
+ 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
+ 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
+ 'o', 0, 'r', 0, 't', 0
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief IN EP1 state.
+ */
+static USBInEndpointState ep1instate;
+
+/**
+ * @brief OUT EP1 state.
+ */
+static USBOutEndpointState ep1outstate;
+
+/**
+ * @brief EP1 initialization structure (both IN and OUT).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK,
+ NULL,
+ sduDataTransmitted,
+ sduDataReceived,
+ 0x0040,
+ 0x0040,
+ &ep1instate,
+ &ep1outstate,
+ 2,
+ NULL
+};
+
+/**
+ * @brief IN EP2 state.
+ */
+static USBInEndpointState ep2instate;
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ &ep2instate,
+ NULL,
+ 1,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+ extern SerialUSBDriver SDU1;
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ chSysLockFromISR();
+
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
+
+ /* Resetting the state of the CDC subsystem.*/
+ sduConfigureHookI(&SDU1);
+
+ chSysUnlockFromISR();
+ return;
+ case USB_EVENT_SUSPEND:
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * USB driver configuration.
+ */
+const USBConfig usbcfg = {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ NULL
+};
+
+/*
+ * Serial over USB driver configuration.
+ */
+const SerialUSBConfig serusbcfg = {
+ &USBD2,
+ USBD2_DATA_REQUEST_EP,
+ USBD2_DATA_AVAILABLE_EP,
+ USBD2_INTERRUPT_REQUEST_EP
+};
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h new file mode 100644 index 0000000..2ffaa17 --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h @@ -0,0 +1,25 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _USBCFG_H_
+#define _USBCFG_H_
+
+extern const USBConfig usbcfg;
+extern SerialUSBConfig serusbcfg;
+
+#endif /* _USBCFG_H_ */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c new file mode 100644 index 0000000..666cbcb --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c @@ -0,0 +1,277 @@ +#include <ch.h>
+#include <hal.h>
+#include <stm32_ltdc.h>
+
+const ltdc_color_t wolf3d_palette[256] __attribute__((aligned(4))) = {
+ 0xFF000000, /* 0x00 */
+ 0xFF0000A8, /* 0x01 */
+ 0xFF00A800, /* 0x02 */
+ 0xFF00A8A8, /* 0x03 */
+ 0xFFA80000, /* 0x04 */
+ 0xFFA800A8, /* 0x05 */
+ 0xFFA85400, /* 0x06 */
+ 0xFFA8A8A8, /* 0x07 */
+ 0xFF545454, /* 0x08 */
+ 0xFF5454FC, /* 0x09 */
+ 0xFF54FC54, /* 0x0A */
+ 0xFF54FCFC, /* 0x0B */
+ 0xFFFC5454, /* 0x0C */
+ 0xFFFC54FC, /* 0x0D */
+ 0xFFFCFC54, /* 0x0E */
+ 0xFFFCFCFC, /* 0x0F */
+ 0xFFECECEC, /* 0x10 */
+
+ 0xFFDCDCDC, /* 0x11 */
+ 0xFFD0D0D0, /* 0x12 */
+ 0xFFC0C0C0, /* 0x13 */
+ 0xFFB4B4B4, /* 0x14 */
+ 0xFFA8A8A8, /* 0x15 */
+ 0xFF989898, /* 0x16 */
+ 0xFF8C8C8C, /* 0x17 */
+ 0xFF7C7C7C, /* 0x18 */
+ 0xFF707070, /* 0x19 */
+ 0xFF646464, /* 0x1A */
+ 0xFF545454, /* 0x1B */
+ 0xFF484848, /* 0x1C */
+ 0xFF383838, /* 0x1D */
+ 0xFF2C2C2C, /* 0x1E */
+ 0xFF202020, /* 0x1F */
+ 0xFFFC0000, /* 0x20 */
+
+ 0xFFEC0000, /* 0x21 */
+ 0xFFE00000, /* 0x22 */
+ 0xFFD40000, /* 0x23 */
+ 0xFFC80000, /* 0x24 */
+ 0xFFBC0000, /* 0x25 */
+ 0xFFB00000, /* 0x26 */
+ 0xFFA40000, /* 0x27 */
+ 0xFF980000, /* 0x28 */
+ 0xFF880000, /* 0x29 */
+ 0xFF7C0000, /* 0x2A */
+ 0xFF700000, /* 0x2B */
+ 0xFF640000, /* 0x2C */
+ 0xFF580000, /* 0x2D */
+ 0xFF4C0000, /* 0x2E */
+ 0xFF400000, /* 0x2F */
+ 0xFFFCD8D8, /* 0x30 */
+
+ 0xFFFCB8B8, /* 0x31 */
+ 0xFFFC9C9C, /* 0x32 */
+ 0xFFFC7C7C, /* 0x33 */
+ 0xFFFC5C5C, /* 0x34 */
+ 0xFFFC4040, /* 0x35 */
+ 0xFFFC2020, /* 0x36 */
+ 0xFFFC0000, /* 0x37 */
+ 0xFFFCA85C, /* 0x38 */
+ 0xFFFC9840, /* 0x39 */
+ 0xFFFC8820, /* 0x3A */
+ 0xFFFC7800, /* 0x3B */
+ 0xFFE46C00, /* 0x3C */
+ 0xFFCC6000, /* 0x3D */
+ 0xFFB45400, /* 0x3E */
+ 0xFF9C4C00, /* 0x3F */
+ 0xFFFCFCD8, /* 0x40 */
+
+ 0xFFFCFCB8, /* 0x41 */
+ 0xFFFCFC9C, /* 0x42 */
+ 0xFFFCFC7C, /* 0x43 */
+ 0xFFFCF85C, /* 0x44 */
+ 0xFFFCF440, /* 0x45 */
+ 0xFFFCF420, /* 0x46 */
+ 0xFFFCF400, /* 0x47 */
+ 0xFFE4D800, /* 0x48 */
+ 0xFFCCC400, /* 0x49 */
+ 0xFFB4AC00, /* 0x4A */
+ 0xFF9C9C00, /* 0x4B */
+ 0xFF848400, /* 0x4C */
+ 0xFF706C00, /* 0x4D */
+ 0xFF585400, /* 0x4E */
+ 0xFF404000, /* 0x4F */
+ 0xFFD0FC5C, /* 0x50 */
+
+ 0xFFC4FC40, /* 0x51 */
+ 0xFFB4FC20, /* 0x52 */
+ 0xFFA0FC00, /* 0x53 */
+ 0xFF90E400, /* 0x54 */
+ 0xFF80CC00, /* 0x55 */
+ 0xFF74B400, /* 0x56 */
+ 0xFF609C00, /* 0x57 */
+ 0xFFD8FCD8, /* 0x58 */
+ 0xFFBCFCB8, /* 0x59 */
+ 0xFF9CFC9C, /* 0x5A */
+ 0xFF80FC7C, /* 0x5B */
+ 0xFF60FC5C, /* 0x5C */
+ 0xFF40FC40, /* 0x5D */
+ 0xFF20FC20, /* 0x5E */
+ 0xFF00FC00, /* 0x5F */
+ 0xFF00FC00, /* 0x60 */
+
+ 0xFF00EC00, /* 0x61 */
+ 0xFF00E000, /* 0x62 */
+ 0xFF00D400, /* 0x63 */
+ 0xFF04C800, /* 0x64 */
+ 0xFF04BC00, /* 0x65 */
+ 0xFF04B000, /* 0x66 */
+ 0xFF04A400, /* 0x67 */
+ 0xFF049800, /* 0x68 */
+ 0xFF048800, /* 0x69 */
+ 0xFF047C00, /* 0x6A */
+ 0xFF047000, /* 0x6B */
+ 0xFF046400, /* 0x6C */
+ 0xFF045800, /* 0x6D */
+ 0xFF044C00, /* 0x6E */
+ 0xFF044000, /* 0x6F */
+ 0xFFD8FCFC, /* 0x70 */
+
+ 0xFFB8FCFC, /* 0x71 */
+ 0xFF9CFCFC, /* 0x72 */
+ 0xFF7CFCF8, /* 0x73 */
+ 0xFF5CFCFC, /* 0x74 */
+ 0xFF40FCFC, /* 0x75 */
+ 0xFF20FCFC, /* 0x76 */
+ 0xFF00FCFC, /* 0x77 */
+ 0xFF00E4E4, /* 0x78 */
+ 0xFF00CCCC, /* 0x79 */
+ 0xFF00B4B4, /* 0x7A */
+ 0xFF009C9C, /* 0x7B */
+ 0xFF008484, /* 0x7C */
+ 0xFF007070, /* 0x7D */
+ 0xFF005858, /* 0x7E */
+ 0xFF004040, /* 0x7F */
+ 0xFF5CBCFC, /* 0x80 */
+
+ 0xFF40B0FC, /* 0x81 */
+ 0xFF20A8FC, /* 0x82 */
+ 0xFF009CFC, /* 0x83 */
+ 0xFF008CE4, /* 0x84 */
+ 0xFF007CCC, /* 0x85 */
+ 0xFF006CB4, /* 0x86 */
+ 0xFF005C9C, /* 0x87 */
+ 0xFFD8D8FC, /* 0x88 */
+ 0xFFB8BCFC, /* 0x89 */
+ 0xFF9C9CFC, /* 0x8A */
+ 0xFF7C80FC, /* 0x8B */
+ 0xFF5C60FC, /* 0x8C */
+ 0xFF4040FC, /* 0x8D */
+ 0xFF2024FC, /* 0x8E */
+ 0xFF0004FC, /* 0x8F */
+ 0xFF0000FC, /* 0x90 */
+
+ 0xFF0000EC, /* 0x91 */
+ 0xFF0000E0, /* 0x92 */
+ 0xFF0000D4, /* 0x93 */
+ 0xFF0000C8, /* 0x94 */
+ 0xFF0000BC, /* 0x95 */
+ 0xFF0000B0, /* 0x96 */
+ 0xFF0000A4, /* 0x97 */
+ 0xFF000098, /* 0x98 */
+ 0xFF000088, /* 0x99 */
+ 0xFF00007C, /* 0x9A */
+ 0xFF000070, /* 0x9B */
+ 0xFF000064, /* 0x9C */
+ 0xFF000058, /* 0x9D */
+ 0xFF00004C, /* 0x9E */
+ 0xFF000040, /* 0x9F */
+ 0xFF282828, /* 0xA0 */
+
+ 0xFFFCE034, /* 0xA1 */
+ 0xFFFCD424, /* 0xA2 */
+ 0xFFFCCC18, /* 0xA3 */
+ 0xFFFCC008, /* 0xA4 */
+ 0xFFFCB400, /* 0xA5 */
+ 0xFFB420FC, /* 0xA6 */
+ 0xFFA800FC, /* 0xA7 */
+ 0xFF9800E4, /* 0xA8 */
+ 0xFF8000CC, /* 0xA9 */
+ 0xFF7400B4, /* 0xAA */
+ 0xFF60009C, /* 0xAB */
+ 0xFF500084, /* 0xAC */
+ 0xFF440070, /* 0xAD */
+ 0xFF340058, /* 0xAE */
+ 0xFF280040, /* 0xAF */
+ 0xFFFCD8FC, /* 0xB0 */
+
+ 0xFFFCB8FC, /* 0xB1 */
+ 0xFFFC9CFC, /* 0xB2 */
+ 0xFFFC7CFC, /* 0xB3 */
+ 0xFFFC5CFC, /* 0xB4 */
+ 0xFFFC40FC, /* 0xB5 */
+ 0xFFFC20FC, /* 0xB6 */
+ 0xFFFC00FC, /* 0xB7 */
+ 0xFFE000E4, /* 0xB8 */
+ 0xFFC800CC, /* 0xB9 */
+ 0xFFB400B4, /* 0xBA */
+ 0xFF9C009C, /* 0xBB */
+ 0xFF840084, /* 0xBC */
+ 0xFF6C0070, /* 0xBD */
+ 0xFF580058, /* 0xBE */
+ 0xFF400040, /* 0xBF */
+ 0xFFFCE8DC, /* 0xC0 */
+
+ 0xFFFCE0D0, /* 0xC1 */
+ 0xFFFCD8C4, /* 0xC2 */
+ 0xFFFCD4BC, /* 0xC3 */
+ 0xFFFCCCB0, /* 0xC4 */
+ 0xFFFCC4A4, /* 0xC5 */
+ 0xFFFCBC9C, /* 0xC6 */
+ 0xFFFCB890, /* 0xC7 */
+ 0xFFFCB080, /* 0xC8 */
+ 0xFFFCA470, /* 0xC9 */
+ 0xFFFC9C60, /* 0xCA */
+ 0xFFF0945C, /* 0xCB */
+ 0xFFE88C58, /* 0xCC */
+ 0xFFDC8854, /* 0xCD */
+ 0xFFD08050, /* 0xCE */
+ 0xFFC87C4C, /* 0xCF */
+ 0xFFBC7848, /* 0xD0 */
+
+ 0xFFB47044, /* 0xD1 */
+ 0xFFA86840, /* 0xD2 */
+ 0xFFA0643C, /* 0xD3 */
+ 0xFF9C6038, /* 0xD4 */
+ 0xFF905C34, /* 0xD5 */
+ 0xFF885830, /* 0xD6 */
+ 0xFF80502C, /* 0xD7 */
+ 0xFF744C28, /* 0xD8 */
+ 0xFF6C4824, /* 0xD9 */
+ 0xFF5C4020, /* 0xDA */
+ 0xFF543C1C, /* 0xDB */
+ 0xFF483818, /* 0xDC */
+ 0xFF403018, /* 0xDD */
+ 0xFF382C14, /* 0xDE */
+ 0xFF28200C, /* 0xDF */
+ 0xFF600064, /* 0xE0 */
+
+ 0xFF006464, /* 0xE1 */
+ 0xFF006060, /* 0xE2 */
+ 0xFF00001C, /* 0xE3 */
+ 0xFF00002C, /* 0xE4 */
+ 0xFF302410, /* 0xE5 */
+ 0xFF480048, /* 0xE6 */
+ 0xFF500050, /* 0xE7 */
+ 0xFF000034, /* 0xE8 */
+ 0xFF1C1C1C, /* 0xE9 */
+ 0xFF4C4C4C, /* 0xEA */
+ 0xFF5C5C5C, /* 0xEB */
+ 0xFF404040, /* 0xEC */
+ 0xFF303030, /* 0xED */
+ 0xFF343434, /* 0xEE */
+ 0xFFD8F4F4, /* 0xEF */
+ 0xFFB8E8E8, /* 0xF0 */
+
+ 0xFF9CDCDC, /* 0xF1 */
+ 0xFF74C8C8, /* 0xF2 */
+ 0xFF48C0C0, /* 0xF3 */
+ 0xFF20B4B4, /* 0xF4 */
+ 0xFF20B0B0, /* 0xF5 */
+ 0xFF00A4A4, /* 0xF6 */
+ 0xFF009898, /* 0xF7 */
+ 0xFF008C8C, /* 0xF8 */
+ 0xFF008484, /* 0xF9 */
+ 0xFF007C7C, /* 0xFA */
+ 0xFF007878, /* 0xFB */
+ 0xFF007474, /* 0xFC */
+ 0xFF007070, /* 0xFD */
+ 0xFF006C6C, /* 0xFE */
+ 0xFF980088, /* 0xFF */
+};
|
