[KINETIS] Update demos (for HAL changes).

2 files changed, 20 insertions, 9 deletions

diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile
index eb54d34..cb575fb 100644
--- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile
+++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/Makefile
@@ -84,7 +84,7 @@ PROJECT = ch
 CHIBIOS = ../../../../ChibiOS-RT

 CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib

 # Startup files.

-include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_kl2x.mk

+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk

 # HAL-OSAL files (optional).

 include $(CHIBIOS)/os/hal/hal.mk

 include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk

@@ -97,7 +97,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
 include $(CHIBIOS)/test/rt/test.mk

 

 # Define linker script file here

-LDSCRIPT= $(STARTUPLD)/KL25Z128.ld

+LDSCRIPT = $(STARTUPLD)/MKL2xZ128.ld

 

 # C sources that can be compiled in ARM or THUMB mode depending on the global

 # setting.

diff --git a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h
index da7ba95..9118e7b 100644
--- a/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h
+++ b/demos/KINETIS/RT-FREEDOM-KL25Z-EXT/mcuconf.h
@@ -24,11 +24,23 @@
  */

 

 /* Select the MCU clocking mode below by enabling the appropriate block. */

+/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */

 

-/* FEI mode */

+/* PEE mode - 48MHz system clock driven by external crystal. */

+#if 1

+#define KINETIS_MCG_MODE            KINETIS_MCG_MODE_PEE

+#define KINETIS_PLLCLK_FREQUENCY    96000000UL

+#define KINETIS_SYSCLK_FREQUENCY    48000000UL

+#endif

+

+/* FEI mode - ~24MHz */

 #if 0

 #define KINETIS_MCG_MODE            KINETIS_MCG_MODE_FEI

-#define KINETIS_SYSCLK_FREQUENCY    21000000UL

+#define KINETIS_MCG_FLL_DMX32       1           /* Fine-tune for 32.768 kHz */

+#define KINETIS_MCG_FLL_DRS         0           /* 732x FLL factor */

+#define KINETIS_SYSCLK_FREQUENCY    23986176UL  /* 32.768 kHz * 732 (~24 MHz) */

+#define KINETIS_CLKDIV1_OUTDIV1     1           /* Divide MCGCLKOUT (~24MHz) by 1 to SYSCLK */

+#define KINETIS_CLKDIV1_OUTDIV4     2           /* Divide by 2 for (~12MHz) bus/flash clock */

 #endif /* 0 */

 

 /* FEE mode - 24 MHz with external 32.768 kHz crystal */

@@ -36,12 +48,11 @@
 #define KINETIS_MCG_MODE            KINETIS_MCG_MODE_FEE

 #define KINETIS_MCG_FLL_DMX32       1           /* Fine-tune for 32.768 kHz */

 #define KINETIS_MCG_FLL_DRS         0           /* 732x FLL factor */

-#define KINETIS_MCG_FLL_OUTDIV1     1           /* Divide 48 MHz FLL by 1 => 24 MHz */

-#define KINETIS_MCG_FLL_OUTDIV4     2           /* Divide OUTDIV1 output by 2 => 12 MHz */

+#define KINETIS_CLKDIV1_OUTDIV1     1           /* Divide 48 MHz FLL by 1 => 24 MHz */

+#define KINETIS_CLKDIV1_OUTDIV4     2           /* Divide OUTDIV1 output by 2 => 12 MHz */

 #define KINETIS_SYSCLK_FREQUENCY    23986176UL  /* 32.768 kHz*732 (~24 MHz) */

 #define KINETIS_UART0_CLOCK_FREQ    (32768 * 732) /* FLL output */

 #define KINETIS_UART0_CLOCK_SRC     1           /* Select FLL clock */

-#define KINETIS_BUSCLK_FREQUENCY    (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)

 #endif /* 0 */

 

 /* FEE mode - 48 MHz */

@@ -49,8 +60,8 @@
 #define KINETIS_MCG_MODE            KINETIS_MCG_MODE_FEE

 #define KINETIS_MCG_FLL_DMX32       1           /* Fine-tune for 32.768 kHz */

 #define KINETIS_MCG_FLL_DRS         1           /* 1464x FLL factor */

-#define KINETIS_MCG_FLL_OUTDIV1     1           /* Divide 48 MHz FLL by 1 => 48 MHz */

-#define KINETIS_MCG_FLL_OUTDIV4     2           /* Divide OUTDIV1 output by 2 => 24 MHz */

+#define KINETIS_CLKDIV1_OUTDIV1     1           /* Divide 48 MHz FLL by 1 => 48 MHz */

+#define KINETIS_CLKDIV1_OUTDIV4     2           /* Divide OUTDIV1 output by 2 => 24 MHz */

 #define KINETIS_SYSCLK_FREQUENCY    47972352UL  /* 32.768 kHz * 1464 (~48 MHz) */

 #endif /* 0 */