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authorbarthess <barthess@yandex.ru>2014-10-25 15:46:31 +0300
committerbarthess <barthess@yandex.ru>2014-10-25 15:46:31 +0300
commite87406722421e216deb91fa32e08e36b3dd03c91 (patch)
tree7c8c4a96662c8d9d79e8ff38130b82ba854394d2
parent3af04b9ee56ae5f46efa0b1cdf5d76fb438b3463 (diff)
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FSMC. SDRAM. Fixed delay code
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
index d2c4f78..25da179 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
@@ -102,8 +102,8 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
- /* Step 4: Insert 1 ms delay (tipically 100uS).*/
- osalThreadSleepMilliseconds(1);
+ /* Step 4: Insert delay (tipically 100uS).*/
+ osalSysPolledDelayX(US2RTC(STM32_SYSCLK, 100));
/* Step 5: Configure a PALL (precharge all) command.*/
_sdram_wait_ready();