Add GPT driver for nRF51

9 files changed, 1839 insertions, 1 deletions

diff --git a/os/hal/ports/NRF51/NRF51822/gpt_lld.c b/os/hal/ports/NRF51/NRF51822/gpt_lld.c
new file mode 100644
index 0000000..f39470f
--- /dev/null
+++ b/os/hal/ports/NRF51/NRF51822/gpt_lld.c
@@ -0,0 +1,358 @@
+/*

+    ChibiOS - 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    NRF51x22/gpt_lld.c

+ * @brief   NRF51x22 GPT subsystem low level driver source.

+ *

+ * @addtogroup GPT

+ * @{

+ */

+

+#include "hal.h"

+

+#if HAL_USE_GPT || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+#define NRF51_TIMER_PRESCALER_NUM 10

+#define NRF51_TIMER_COMPARE_NUM   4

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   GPTD1 driver identifier.

+ * @note    The driver GPTD1 allocates the complex timer TIM1 when enabled.

+ */

+#if NRF51_GPT_USE_TIMER0 || defined(__DOXYGEN__)

+GPTDriver GPTD1;

+#endif

+

+/**

+ * @brief   GPTD2 driver identifier.

+ * @note    The driver GPTD2 allocates the timer TIM2 when enabled.

+ */

+#if NRF51_GPT_USE_TIMER1 || defined(__DOXYGEN__)

+GPTDriver GPTD2;

+#endif

+

+/**

+ * @brief   GPTD3 driver identifier.

+ * @note    The driver GPTD3 allocates the timer TIM3 when enabled.

+ */

+#if NRF51_GPT_USE_TIMER2 || defined(__DOXYGEN__)

+GPTDriver GPTD3;

+#endif

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+static uint8_t prescaler(uint16_t freq)

+{

+  uint8_t i;

+  static const gptfreq_t frequencies[] = {

+    NRF51_GPT_FREQ_16MHZ,

+    NRF51_GPT_FREQ_8MHZ,

+    NRF51_GPT_FREQ_4MHZ,

+    NRF51_GPT_FREQ_2MHZ,

+    NRF51_GPT_FREQ_1MHZ,

+    NRF51_GPT_FREQ_500KHZ,

+    NRF51_GPT_FREQ_250KHZ,

+    NRF51_GPT_FREQ_125KHZ,

+    NRF51_GPT_FREQ_62500HZ,

+    NRF51_GPT_FREQ_31250HZ,

+  };

+

+  for (i = 0; i < NRF51_TIMER_PRESCALER_NUM; i++)

+    if (freq == frequencies[i])

+      return i;

+

+  osalDbgAssert(FALSE, "invalid timer frequency");

+

+  return 0;

+}

+

+/**

+ * @brief   Shared IRQ handler.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ */

+static void gpt_lld_serve_interrupt(GPTDriver *gptp) {

+

+  gptp->tim->EVENTS_COMPARE[gptp->cc_int] = 0;

+  if (gptp->state == GPT_ONESHOT)

+    gptp->state = GPT_READY;                 /* Back in GPT_READY state.     */

+  gptp->config->callback(gptp);

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if NRF51_GPT_USE_TIMER0

+/**

+ * @brief   TIMER0 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(Vector60) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD1);

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* NRF51_GPT_USE_TIMER0 */

+

+#if NRF51_GPT_USE_TIMER1

+/**

+ * @brief   TIMER1 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(Vector64) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD2);

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* NRF51_GPT_USE_TIMER1 */

+

+#if NRF51_GPT_USE_TIMER2

+/**

+ * @brief   TIMER2 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(Vector68) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD3);

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* NRF51_GPT_USE_TIMER2 */

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level GPT driver initialization.

+ *

+ * @notapi

+ */

+void gpt_lld_init(void) {

+

+#if NRF51_GPT_USE_TIMER0

+  /* Driver initialization.*/

+  GPTD1.tim = NRF_TIMER0;

+  gptObjectInit(&GPTD1);

+#endif

+

+#if NRF51_GPT_USE_TIMER1

+  /* Driver initialization.*/

+  GPTD2.tim = NRF_TIMER1;

+  gptObjectInit(&GPTD2);

+#endif

+

+#if NRF51_GPT_USE_TIMER2

+  /* Driver initialization.*/

+  GPTD3.tim = NRF_TIMER2;

+  gptObjectInit(&GPTD3);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the GPT peripheral.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_start(GPTDriver *gptp) {

+

+  NRF_TIMER_Type *tim = gptp->tim;

+

+  if (gptp->state == GPT_STOP) {

+    osalDbgAssert(gptp->cc_int < NRF51_TIMER_COMPARE_NUM,

+        "invalid capture/compare index");

+

+    tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;

+#if NRF51_GPT_USE_TIMER0

+    if (&GPTD1 == gptp)

+      nvicEnableVector(TIMER0_IRQn, NRF51_GPT_TIMER0_IRQ_PRIORITY);

+#endif

+#if NRF51_GPT_USE_TIMER1

+    if (&GPTD2 == gptp)

+      nvicEnableVector(TIMER1_IRQn, NRF51_GPT_TIMER1_IRQ_PRIORITY);

+#endif

+#if NRF51_GPT_USE_TIMER2

+    if (&GPTD3 == gptp)

+      nvicEnableVector(TIMER2_IRQn, NRF51_GPT_TIMER2_IRQ_PRIORITY);

+#endif

+  }

+

+  /* Prescaler value calculation.*/

+  tim->PRESCALER = prescaler(gptp->config->frequency);

+

+  /* Timer configuration.*/

+  tim->MODE = TIMER_MODE_MODE_Timer << TIMER_MODE_MODE_Pos;

+

+  switch (gptp->config->resolution) {

+

+    case 8:

+      tim->BITMODE = TIMER_BITMODE_BITMODE_08Bit << TIMER_BITMODE_BITMODE_Pos;

+      break;

+

+    case 16:

+      tim->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;

+      break;

+

+#if NRF51_GPT_USE_TIMER0

+    case 24:

+      tim->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;

+      break;

+

+    case 32:

+      tim->BITMODE = TIMER_BITMODE_BITMODE_32Bit << TIMER_BITMODE_BITMODE_Pos;

+      break;

+#endif

+

+    default:

+      osalDbgAssert(FALSE, "invalid timer resolution");

+      break;

+  };

+}

+

+/**

+ * @brief   Deactivates the GPT peripheral.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_stop(GPTDriver *gptp) {

+

+  if (gptp->state == GPT_READY) {

+    gptp->tim->TASKS_SHUTDOWN = 1;

+

+#if NRF51_GPT_USE_TIMER0

+    if (&GPTD1 == gptp)

+      nvicDisableVector(TIMER0_IRQn);

+#endif

+#if NRF51_GPT_USE_TIMER1

+    if (&GPTD2 == gptp)

+      nvicDisableVector(TIMER1_IRQn);

+#endif

+#if NRF51_GPT_USE_TIMER2

+    if (&GPTD3 == gptp)

+      nvicDisableVector(TIMER2_IRQn);

+#endif

+    gptp->tim->INTENCLR = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;

+  }

+}

+

+/**

+ * @brief   Starts the timer in continuous mode.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ * @param[in] interval  period in ticks

+ *

+ * @notapi

+ */

+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {

+

+  NRF_TIMER_Type *tim = gptp->tim;

+

+  tim->TASKS_CLEAR = 1;

+  tim->CC[gptp->cc_int] = (uint32_t)(interval - 1);  /* Time constant.        */

+  if (gptp->state == GPT_ONESHOT)

+    gptp->tim->SHORTS = TIMER_SHORTS_COMPARE0_STOP_Msk << gptp->cc_int;

+  else if (gptp->state == GPT_CONTINUOUS)

+    gptp->tim->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk << gptp->cc_int;

+  tim->TASKS_START = 1;

+}

+

+/**

+ * @brief   Stops the timer.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_stop_timer(GPTDriver *gptp) {

+

+  gptp->tim->TASKS_STOP = 1;

+}

+

+/**

+ * @brief   Starts the timer in one shot mode and waits for completion.

+ * @details This function specifically polls the timer waiting for completion

+ *          in order to not have extra delays caused by interrupt servicing,

+ *          this function is only recommended for short delays.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ * @param[in] interval  time interval in ticks

+ *

+ * @notapi

+ */

+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {

+

+  NRF_TIMER_Type *tim = gptp->tim;

+

+  tim->INTENCLR = (1UL << gptp->cc_int) << TIMER_INTENSET_COMPARE0_Pos;

+  tim->TASKS_CLEAR = 1;

+  tim->CC[gptp->cc_int] = (uint32_t)(interval - 1);  /* Time constant.        */

+  tim->TASKS_START = 1;

+  while (!(tim->INTENSET & (TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int)))

+    ;

+  tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;

+}

+

+/**

+ * @brief   Returns the counter value of GPT peripheral.

+ * @pre     The GPT unit must be running in continuous mode.

+ * @note    The nature of the counter is not defined, it may count upward

+ *          or downward, it could be continuously running or not.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ * @return              The current counter value.

+ *

+ * @notapi

+ */

+gptcnt_t gpt_lld_get_counter(GPTDriver *gptp) {

+

+  gptp->tim->TASKS_CAPTURE[gptp->cc_get] = 1;

+  return gptp->tim->CC[gptp->cc_get];

+}

+

+#endif /* HAL_USE_GPT */

+

+/** @} */

diff --git a/os/hal/ports/NRF51/NRF51822/gpt_lld.h b/os/hal/ports/NRF51/NRF51822/gpt_lld.h
new file mode 100644
index 0000000..d707cda
--- /dev/null
+++ b/os/hal/ports/NRF51/NRF51822/gpt_lld.h
@@ -0,0 +1,266 @@
+/*

+    Copyright (C) 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    NRF51x22/gpt_lld.h

+ * @brief   NRF51x22 GPT subsystem low level driver header.

+ *

+ * @addtogroup GPT

+ * @{

+ */

+

+#ifndef _GPT_LLD_H_

+#define _GPT_LLD_H_

+

+#if HAL_USE_GPT || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   GPTD1 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD1 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(NRF51_GPT_USE_TIMER0) || defined(__DOXYGEN__)

+#define NRF51_GPT_USE_TIMER0                  FALSE

+#endif

+

+/**

+ * @brief   GPTD2 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD2 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(NRF51_GPT_USE_TIMER1) || defined(__DOXYGEN__)

+#define NRF51_GPT_USE_TIMER1                  FALSE

+#endif

+

+/**

+ * @brief   GPTD3 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD3 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(NRF51_GPT_USE_TIMER2) || defined(__DOXYGEN__)

+#define NRF51_GPT_USE_TIMER2                  FALSE

+#endif

+

+/**

+ * @brief   GPTD1 interrupt priority level setting.

+ */

+#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF51_GPT_TIMER0_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPTD2 interrupt priority level setting.

+ */

+#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF51_GPT_TIMER1_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPTD3 interrupt priority level setting.

+ */

+#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define NRF51_GPT_TIMER2_IRQ_PRIORITY         7

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if !NRF51_GPT_USE_TIMER0 && !NRF51_GPT_USE_TIMER1 &&                         \

+    !NRF51_GPT_USE_TIMER2

+#error "GPT driver activated but no TIM peripheral assigned"

+#endif

+

+#if 0

+#if NRF51_GPT_USE_TIMER0 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIMER0"

+#endif

+

+#if NRF51_GPT_USE_TIMER1 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER1_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIMER1"

+#endif

+

+#if NRF51_GPT_USE_TIMER2 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIMER2"

+#endif

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   GPT frequency type.

+ */

+typedef enum {

+  NRF51_GPT_FREQ_31250HZ = 31250,

+  NRF51_GPT_FREQ_62500HZ = 62500,

+  NRF51_GPT_FREQ_125KHZ = 125000,

+  NRF51_GPT_FREQ_250KHZ = 250000,

+  NRF51_GPT_FREQ_500KHZ = 500000,

+  NRF51_GPT_FREQ_1MHZ = 1000000,

+  NRF51_GPT_FREQ_2MHZ = 2000000,

+  NRF51_GPT_FREQ_4MHZ = 4000000,

+  NRF51_GPT_FREQ_8MHZ = 8000000,

+  NRF51_GPT_FREQ_16MHZ = 16000000,

+} gptfreq_t;

+

+/**

+ * @brief   GPT counter type.

+ */

+typedef uint32_t gptcnt_t;

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+  /**

+   * @brief   Timer clock in Hz.

+   * @note    The low level can use assertions in order to catch invalid

+   *          frequency specifications.

+   */

+  gptfreq_t                 frequency;

+  /**

+   * @brief   Timer callback pointer.

+   * @note    This callback is invoked on GPT counter events.

+   * @note    This callback can be set to @p NULL but in that case the

+   *          one-shot mode cannot be used.

+   */

+  gptcallback_t             callback;

+  /* End of the mandatory fields.*/

+  /**

+   * @brief The timer resolution in bits (8/16/24/32)

+   * @note  The default value of this field is 16 bits

+   * @note  The 24 and 32 bit modes are only valid for TIMER0

+   */

+  uint8_t                  resolution;

+} GPTConfig;

+

+/**

+ * @brief   Structure representing a GPT driver.

+ */

+struct GPTDriver {

+  /**

+   * @brief Driver state.

+   */

+  gptstate_t                state;

+  /**

+   * @brief Current configuration data.

+   */

+  const GPTConfig           *config;

+#if defined(GPT_DRIVER_EXT_FIELDS)

+  GPT_DRIVER_EXT_FIELDS

+#endif

+  /* End of the mandatory fields.*/

+  /**

+   * @brief Pointer to the TIMERx registers block.

+   */

+  NRF_TIMER_Type            *tim;

+  /**

+   * @brief Index of the TIMERx capture/compare register used for setting the

+   *        interval between compare events.

+   */

+  uint8_t                   cc_int;

+  /**

+   * @brief Index of the TIMERx capture/compare register used for getting the

+   *        current timer counter value.

+   */

+  uint8_t                   cc_get;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Changes the interval of GPT peripheral.

+ * @details This function changes the interval of a running GPT unit.

+ * @pre     The GPT unit must be running in continuous mode.

+ * @post    The GPT unit interval is changed to the new value.

+ * @note    The function has effect at the next cycle start.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ * @param[in] interval  new cycle time in timer ticks

+ *

+ * @notapi

+ */

+#define gpt_lld_change_interval(gptp, interval)                               \

+  ((gptp)->tim->CC[(gptp)->cc_int] = (uint32_t)((interval) - 1))

+

+/**

+ * @brief   Returns the interval of GPT peripheral.

+ * @pre     The GPT unit must be running in continuous mode.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ * @return              The current interval.

+ *

+ * @notapi

+ */

+#define gpt_lld_get_interval(gptp)                                            \

+  ((gptcnt_t)((gptp)->tim->CC[(gptp)->cc_int]) + 1)

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if NRF51_GPT_USE_TIMER0 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD1;

+#endif

+

+#if NRF51_GPT_USE_TIMER1 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD2;

+#endif

+

+#if NRF51_GPT_USE_TIMER2 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD3;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void gpt_lld_init(void);

+  void gpt_lld_start(GPTDriver *gptp);

+  void gpt_lld_stop(GPTDriver *gptp);

+  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);

+  void gpt_lld_stop_timer(GPTDriver *gptp);

+  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);

+  gptcnt_t gpt_lld_get_counter(GPTDriver *gptp);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_GPT */

+

+#endif /* _GPT_LLD_H_ */

+

+/** @} */

diff --git a/os/hal/ports/NRF51/NRF51822/platform.mk b/os/hal/ports/NRF51/NRF51822/platform.mk
index 3fc8342..244a0d1 100644
--- a/os/hal/ports/NRF51/NRF51822/platform.mk
+++ b/os/hal/ports/NRF51/NRF51822/platform.mk
@@ -8,7 +8,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/ext_lld_isr.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/ext_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/i2c_lld.c \
-              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/adc_lld.c
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/adc_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/gpt_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/testhal/NRF51/NRF51822/GPT/Makefile b/testhal/NRF51/NRF51822/GPT/Makefile
new file mode 100644
index 0000000..ec06536
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/Makefile
@@ -0,0 +1,211 @@
+##############################################################################

+# Build global options

+# NOTE: Can be overridden externally.

+#

+

+# Compiler options here.

+ifeq ($(USE_OPT),)

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16

+endif

+

+# C specific options here (added to USE_OPT).

+ifeq ($(USE_COPT),)

+  USE_COPT =

+endif

+

+# C++ specific options here (added to USE_OPT).

+ifeq ($(USE_CPPOPT),)

+  USE_CPPOPT = -fno-rtti

+endif

+

+# Enable this if you want the linker to remove unused code and data

+ifeq ($(USE_LINK_GC),)

+  USE_LINK_GC = yes

+endif

+

+# Linker extra options here.

+ifeq ($(USE_LDOPT),)

+  USE_LDOPT =

+endif

+

+# Enable this if you want link time optimizations (LTO)

+ifeq ($(USE_LTO),)

+  USE_LTO = yes

+endif

+

+# If enabled, this option allows to compile the application in THUMB mode.

+ifeq ($(USE_THUMB),)

+  USE_THUMB = yes

+endif

+

+# Enable this if you want to see the full log while compiling.

+ifeq ($(USE_VERBOSE_COMPILE),)

+  USE_VERBOSE_COMPILE = no

+endif

+

+# If enabled, this option makes the build process faster by not compiling

+# modules not used in the current configuration.

+ifeq ($(USE_SMART_BUILD),)

+  USE_SMART_BUILD = yes

+endif

+

+#

+# Build global options

+##############################################################################

+

+##############################################################################

+# Architecture or project specific options

+#

+

+# Stack size to be allocated to the Cortex-M process stack. This stack is

+# the stack used by the main() thread.

+ifeq ($(USE_PROCESS_STACKSIZE),)

+  USE_PROCESS_STACKSIZE = 0x200

+endif

+

+# Stack size to the allocated to the Cortex-M main/exceptions stack. This

+# stack is used for processing interrupts and exceptions.

+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)

+  USE_EXCEPTIONS_STACKSIZE = 0x400

+endif

+

+#

+# Architecture or project specific options

+##############################################################################

+

+##############################################################################

+# Project, sources and paths

+#

+

+# Define project name here

+PROJECT = ch

+

+# Imported source files and paths

+CHIBIOS = ../../../../../ChibiOS-RT

+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib

+# Startup files.

+include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_nrf51.mk

+# HAL-OSAL files (optional).

+include $(CHIBIOS)/os/hal/hal.mk

+include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF51/NRF51822/platform.mk

+include $(CHIBIOS_CONTRIB)/os/hal/boards/WVSHARE_BLE400/board.mk

+include $(CHIBIOS)/os/hal/osal/rt/osal.mk

+# RTOS files (optional).

+include $(CHIBIOS)/os/rt/rt.mk

+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk

+# Other files (optional).

+include $(CHIBIOS)/test/rt/test.mk

+

+# Define linker script file here

+LDSCRIPT= $(STARTUPLD)/NRF51822.ld

+

+# C sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CSRC = $(STARTUPSRC) \

+       $(KERNSRC) \

+       $(PORTSRC) \

+       $(OSALSRC) \

+       $(HALSRC) \

+       $(PLATFORMSRC) \

+       $(BOARDSRC) \

+       $(TESTSRC) \

+       main.c

+

+# C++ sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CPPSRC =

+

+# C sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACSRC =

+

+# C++ sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACPPSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCPPSRC =

+

+# List ASM source files here

+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)

+

+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \

+         $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \

+         $(CHIBIOS)/os/various

+

+#

+# Project, sources and paths

+##############################################################################

+

+##############################################################################

+# Compiler settings

+#

+

+MCU  = cortex-m0

+

+TRGT = arm-none-eabi-

+CC   = $(TRGT)gcc

+CPPC = $(TRGT)g++

+# Enable loading with g++ only if you need C++ runtime support.

+# NOTE: You can use C++ even without C++ support if you are careful. C++

+#       runtime support makes code size explode.

+LD   = $(TRGT)gcc

+#LD   = $(TRGT)g++

+CP   = $(TRGT)objcopy

+AS   = $(TRGT)gcc -x assembler-with-cpp

+AR   = $(TRGT)ar

+OD   = $(TRGT)objdump

+SZ   = $(TRGT)size

+HEX  = $(CP) -O ihex

+BIN  = $(CP) -O binary

+

+# ARM-specific options here

+AOPT =

+

+# THUMB-specific options here

+TOPT = -mthumb -DTHUMB

+

+# Define C warning options here

+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes

+

+# Define C++ warning options here

+CPPWARN = -Wall -Wextra -Wundef

+

+#

+# Compiler settings

+##############################################################################

+

+##############################################################################

+# Start of user section

+#

+

+# List all user C define here, like -D_DEBUG=1

+UDEFS =

+

+# Define ASM defines here

+UADEFS =

+

+# List all user directories here

+UINCDIR =

+

+# List the user directory to look for the libraries here

+ULIBDIR =

+

+# List all user libraries here

+ULIBS =

+

+#

+# End of user defines

+##############################################################################

+

+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC

+include $(RULESPATH)/rules.mk

diff --git a/testhal/NRF51/NRF51822/GPT/chconf.h b/testhal/NRF51/NRF51822/GPT/chconf.h
new file mode 100644
index 0000000..5b0630c
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/chconf.h
@@ -0,0 +1,499 @@
+/*

+    Copyright (C) 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/chconf.h

+ * @brief   Configuration file template.

+ * @details A copy of this file must be placed in each project directory, it

+ *          contains the application specific kernel settings.

+ *

+ * @addtogroup config

+ * @details Kernel related settings and hooks.

+ * @{

+ */

+

+#ifndef _CHCONF_H_

+#define _CHCONF_H_

+

+/*===========================================================================*/

+/**

+ * @name System timers settings

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   System time counter resolution.

+ * @note    Allowed values are 16 or 32 bits.

+ */

+#define CH_CFG_ST_RESOLUTION                32

+

+/**

+ * @brief   System tick frequency.

+ * @details Frequency of the system timer that drives the system ticks. This

+ *          setting also defines the system tick time unit.

+ */

+#define CH_CFG_ST_FREQUENCY                 1000

+

+/**

+ * @brief   Time delta constant for the tick-less mode.

+ * @note    If this value is zero then the system uses the classic

+ *          periodic tick. This value represents the minimum number

+ *          of ticks that is safe to specify in a timeout directive.

+ *          The value one is not valid, timeouts are rounded up to

+ *          this value.

+ */

+#define CH_CFG_ST_TIMEDELTA                 0

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel parameters and options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Round robin interval.

+ * @details This constant is the number of system ticks allowed for the

+ *          threads before preemption occurs. Setting this value to zero

+ *          disables the preemption for threads with equal priority and the

+ *          round robin becomes cooperative. Note that higher priority

+ *          threads can still preempt, the kernel is always preemptive.

+ * @note    Disabling the round robin preemption makes the kernel more compact

+ *          and generally faster.

+ * @note    The round robin preemption is not supported in tickless mode and

+ *          must be set to zero in that case.

+ */

+#define CH_CFG_TIME_QUANTUM                 20

+

+/**

+ * @brief   Managed RAM size.

+ * @details Size of the RAM area to be managed by the OS. If set to zero

+ *          then the whole available RAM is used. The core memory is made

+ *          available to the heap allocator and/or can be used directly through

+ *          the simplified core memory allocator.

+ *

+ * @note    In order to let the OS manage the whole RAM the linker script must

+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.

+ * @note    Requires @p CH_CFG_USE_MEMCORE.

+ */

+#define CH_CFG_MEMCORE_SIZE                 0

+

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread. The application @p main()

+ *          function becomes the idle thread and must implement an

+ *          infinite loop.

+ */

+#define CH_CFG_NO_IDLE_THREAD               FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Performance options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   OS optimization.

+ * @details If enabled then time efficient rather than space efficient code

+ *          is used when two possible implementations exist.

+ *

+ * @note    This is not related to the compiler optimization options.

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_OPTIMIZE_SPEED               TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Subsystem options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Time Measurement APIs.

+ * @details If enabled then the time measurement APIs are included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_TM                       FALSE

+

+/**

+ * @brief   Threads registry APIs.

+ * @details If enabled then the registry APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_REGISTRY                 TRUE

+

+/**

+ * @brief   Threads synchronization APIs.

+ * @details If enabled then the @p chThdWait() function is included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_WAITEXIT                 TRUE

+

+/**

+ * @brief   Semaphores APIs.

+ * @details If enabled then the Semaphores APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_SEMAPHORES               TRUE

+

+/**

+ * @brief   Semaphores queuing mode.

+ * @details If enabled then the threads are enqueued on semaphores by

+ *          priority rather than in FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE

+

+/**

+ * @brief   Mutexes APIs.

+ * @details If enabled then the mutexes APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MUTEXES                  TRUE

+

+/**

+ * @brief   Enables recursive behavior on mutexes.

+ * @note    Recursive mutexes are heavier and have an increased

+ *          memory footprint.

+ *

+ * @note    The default is @p FALSE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE

+

+/**

+ * @brief   Conditional Variables APIs.

+ * @details If enabled then the conditional variables APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_CONDVARS                 TRUE

+

+/**

+ * @brief   Conditional Variables APIs with timeout.

+ * @details If enabled then the conditional variables APIs with timeout

+ *          specification are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_CONDVARS.

+ */

+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE

+

+/**

+ * @brief   Events Flags APIs.

+ * @details If enabled then the event flags APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_EVENTS                   TRUE

+

+/**

+ * @brief   Events Flags APIs with timeout.

+ * @details If enabled then the events APIs with timeout specification

+ *          are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_EVENTS.

+ */

+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE

+

+/**

+ * @brief   Synchronous Messages APIs.

+ * @details If enabled then the synchronous messages APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MESSAGES                 TRUE

+

+/**

+ * @brief   Synchronous Messages queuing mode.

+ * @details If enabled then messages are served by priority rather than in

+ *          FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_MESSAGES.

+ */

+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE

+

+/**

+ * @brief   Mailboxes APIs.

+ * @details If enabled then the asynchronous messages (mailboxes) APIs are

+ *          included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_MAILBOXES                TRUE

+

+/**

+ * @brief   I/O Queues APIs.

+ * @details If enabled then the I/O queues APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_QUEUES                   TRUE

+

+/**

+ * @brief   Core Memory Manager APIs.

+ * @details If enabled then the core memory manager APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMCORE                  TRUE

+

+/**

+ * @brief   Heap Allocator APIs.

+ * @details If enabled then the memory heap allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or

+ *          @p CH_CFG_USE_SEMAPHORES.

+ * @note    Mutexes are recommended.

+ */

+#define CH_CFG_USE_HEAP                     TRUE

+

+/**

+ * @brief   Memory Pools Allocator APIs.

+ * @details If enabled then the memory pools allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMPOOLS                 TRUE

+

+/**

+ * @brief   Dynamic Threads APIs.

+ * @details If enabled then the dynamic threads creation APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_WAITEXIT.

+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.

+ */

+#define CH_CFG_USE_DYNAMIC                  TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Debug options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Debug option, kernel statistics.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_STATISTICS                   FALSE

+

+/**

+ * @brief   Debug option, system state check.

+ * @details If enabled the correct call protocol for system APIs is checked

+ *          at runtime.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE

+

+/**

+ * @brief   Debug option, parameters checks.

+ * @details If enabled then the checks on the API functions input

+ *          parameters are activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_CHECKS                TRUE

+

+/**

+ * @brief   Debug option, consistency checks.

+ * @details If enabled then all the assertions in the kernel code are

+ *          activated. This includes consistency checks inside the kernel,

+ *          runtime anomalies and port-defined checks.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_ASSERTS               TRUE

+

+/**

+ * @brief   Debug option, trace buffer.

+ * @details If enabled then the context switch circular trace buffer is

+ *          activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_TRACE                 TRUE

+

+/**

+ * @brief   Debug option, stack checks.

+ * @details If enabled then a runtime stack check is performed.

+ *

+ * @note    The default is @p FALSE.

+ * @note    The stack check is performed in a architecture/port dependent way.

+ *          It may not be implemented or some ports.

+ * @note    The default failure mode is to halt the system with the global

+ *          @p panic_msg variable set to @p NULL.

+ */

+#define CH_DBG_ENABLE_STACK_CHECK           TRUE

+

+/**

+ * @brief   Debug option, stacks initialization.

+ * @details If enabled then the threads working area is filled with a byte

+ *          value when a thread is created. This can be useful for the

+ *          runtime measurement of the used stack.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_FILL_THREADS                 TRUE

+

+/**

+ * @brief   Debug option, threads profiling.

+ * @details If enabled then a field is added to the @p thread_t structure that

+ *          counts the system ticks occurred while executing the thread.

+ *

+ * @note    The default is @p FALSE.

+ * @note    This debug option is not currently compatible with the

+ *          tickless mode.

+ */

+#define CH_DBG_THREADS_PROFILING            FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel hooks

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Threads descriptor structure extension.

+ * @details User fields added to the end of the @p thread_t structure.

+ */

+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \

+  /* Add threads custom fields here.*/

+

+/**

+ * @brief   Threads initialization hook.

+ * @details User initialization code added to the @p chThdInit() API.

+ *

+ * @note    It is invoked from within @p chThdInit() and implicitly from all

+ *          the threads creation APIs.

+ */

+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \

+  /* Add threads initialization code here.*/                                \

+}

+

+/**

+ * @brief   Threads finalization hook.

+ * @details User finalization code added to the @p chThdExit() API.

+ *

+ * @note    It is inserted into lock zone.

+ * @note    It is also invoked when the threads simply return in order to

+ *          terminate.

+ */

+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \

+  /* Add threads finalization code here.*/                                  \

+}

+

+/**

+ * @brief   Context switch hook.

+ * @details This hook is invoked just before switching between threads.

+ */

+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \

+  /* Context switch code here.*/                                            \

+}

+

+/**

+ * @brief   Idle thread enter hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to activate a power saving mode.

+ */

+#define CH_CFG_IDLE_ENTER_HOOK() {                                          \

+}

+

+/**

+ * @brief   Idle thread leave hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to deactivate a power saving mode.

+ */

+#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \

+}

+

+/**

+ * @brief   Idle Loop hook.

+ * @details This hook is continuously invoked by the idle thread loop.

+ */

+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \

+  /* Idle loop code here.*/                                                 \

+}

+

+/**

+ * @brief   System tick event hook.

+ * @details This hook is invoked in the system tick handler immediately

+ *          after processing the virtual timers queue.

+ */

+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \

+  /* System tick event code here.*/                                         \

+}

+

+/**

+ * @brief   System halt hook.

+ * @details This hook is invoked in case to a system halting error before

+ *          the system is halted.

+ */

+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \

+  /* System halt code here.*/                                               \

+}

+

+/** @} */

+

+/*===========================================================================*/

+/* Port-specific settings (override port settings defaulted in chcore.h).    */

+/*===========================================================================*/

+

+#endif  /* _CHCONF_H_ */

+

+/** @} */

diff --git a/testhal/NRF51/NRF51822/GPT/halconf.h b/testhal/NRF51/NRF51822/GPT/halconf.h
new file mode 100644
index 0000000..bf63566
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/halconf.h
@@ -0,0 +1,334 @@
+/*

+    Copyright (C) 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/halconf.h

+ * @brief   HAL configuration header.

+ * @details HAL configuration file, this file allows to enable or disable the

+ *          various device drivers from your application. You may also use

+ *          this file in order to override the device drivers default settings.

+ *

+ * @addtogroup HAL_CONF

+ * @{

+ */

+

+#ifndef _HALCONF_H_

+#define _HALCONF_H_

+

+#include "mcuconf.h"

+

+/**

+ * @brief   Enables the PAL subsystem.

+ */

+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

+#define HAL_USE_PAL                 TRUE

+#endif

+

+/**

+ * @brief   Enables the ADC subsystem.

+ */

+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

+#define HAL_USE_ADC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the CAN subsystem.

+ */

+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)

+#define HAL_USE_CAN                 FALSE

+#endif

+

+/**

+ * @brief   Enables the DAC subsystem.

+ */

+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)

+#define HAL_USE_DAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EXT subsystem.

+ */

+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)

+#define HAL_USE_EXT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                 TRUE

+#endif

+

+/**

+ * @brief   Enables the I2C subsystem.

+ */

+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

+#define HAL_USE_I2C                 FALSE

+#endif

+

+/**

+ * @brief   Enables the I2S subsystem.

+ */

+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)

+#define HAL_USE_I2S                 FALSE

+#endif

+

+/**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MAC subsystem.

+ */

+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

+#define HAL_USE_MAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MMC_SPI subsystem.

+ */

+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_MMC_SPI             FALSE

+#endif

+

+/**

+ * @brief   Enables the PWM subsystem.

+ */

+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

+#define HAL_USE_PWM                 FALSE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)

+#define HAL_USE_RTC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL subsystem.

+ */

+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL              FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB          FALSE

+#endif

+

+/**

+ * @brief   Enables the SPI subsystem.

+ */

+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_SPI                 FALSE

+#endif

+

+/**

+ * @brief   Enables the UART subsystem.

+ */

+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

+#define HAL_USE_UART                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                 FALSE

+#endif

+

+/*===========================================================================*/

+/* ADC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

+#define ADC_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define ADC_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* CAN driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Sleep mode related APIs inclusion switch.

+ */

+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)

+#define CAN_USE_SLEEP_MODE          TRUE

+#endif

+

+/*===========================================================================*/

+/* I2C driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* MAC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)

+#define MAC_USE_ZERO_COPY           FALSE

+#endif

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)

+#define MAC_USE_EVENTS              TRUE

+#endif

+

+/*===========================================================================*/

+/* MMC_SPI driver related settings.                                          */

+/*===========================================================================*/

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ *          This option is recommended also if the SPI driver does not

+ *          use a DMA channel and heavily loads the CPU.

+ */

+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)

+#define MMC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intervals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY              100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT             FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SERIAL driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Default bit rate.

+ * @details Configuration parameter, this is the baud rate selected for the

+ *          default configuration.

+ */

+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

+#define SERIAL_DEFAULT_BITRATE      38400

+#endif

+

+/**

+ * @brief   Serial buffers size.

+ * @details Configuration parameter, you can change the depth of the queue

+ *          buffers depending on the requirements of your application.

+ * @note    The default is 64 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_BUFFERS_SIZE         16

+#endif

+

+/*===========================================================================*/

+/* SERIAL_USB driver related setting.                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   Serial over USB buffers size.

+ * @details Configuration parameter, the buffer size must be a multiple of

+ *          the USB data endpoint maximum packet size.

+ * @note    The default is 64 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_SIZE     256

+#endif

+

+/*===========================================================================*/

+/* SPI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)

+#define SPI_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define SPI_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+#endif /* _HALCONF_H_ */

+

+/** @} */

diff --git a/testhal/NRF51/NRF51822/GPT/main.c b/testhal/NRF51/NRF51822/GPT/main.c
new file mode 100644
index 0000000..3531644
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/main.c
@@ -0,0 +1,124 @@
+/*

+    Copyright (C) 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#include "ch.h"

+#include "hal.h"

+

+/*

+ * GPT callback for GPTD2.

+ */

+static void gptcallback1(GPTDriver *gptp) {

+

+  (void)gptp;

+  palTogglePad(IOPORT1, LED1);

+

+  /*

+   * Start a one-shot timer (@ 250ms)

+   */

+  chSysLockFromISR();

+  gptStartOneShotI(&GPTD3, 15625);

+  chSysUnlockFromISR();

+}

+

+/*

+ * GPT callback for GPTD3.

+ */

+static void gptcallback2(GPTDriver *gptp) {

+

+  (void)gptp;

+  palTogglePad(IOPORT1, LED2);

+}

+

+/*

+ * GPT configuration

+ * Frequency: 31250Hz (32us period)

+ * Resolution: 16 bits

+ */

+static const GPTConfig gptcfg1 = {

+  31250,

+  gptcallback1,

+  16,

+};

+

+/*

+ * GPT configuration

+ * Frequency: 62500Hz (16us period)

+ * Resolution: 16 bits

+ */

+static const GPTConfig gptcfg2 = {

+  62500,

+  gptcallback2,

+  16,

+};

+

+/*

+ * LED blinker thread, times are in milliseconds.

+ */

+static THD_WORKING_AREA(waThread1, 128);

+static THD_FUNCTION(Thread1, arg) {

+

+  (void)arg;

+  chRegSetThreadName("blinker");

+  while (true) {

+    palTogglePad(IOPORT1, LED0);

+    chThdSleepMilliseconds(500);

+  }

+}

+

+/*

+ * Application entry point.

+ */

+int main(void) {

+

+  /*

+   * System initializations.

+   * - HAL initialization, this also initializes the configured device drivers

+   *   and performs the board-specific initializations.

+   * - Kernel initialization, the main() function becomes a thread and the

+   *   RTOS is active.

+   */

+  halInit();

+  chSysInit();

+

+  /*

+   * Creates the blinker thread.

+   */

+  chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);

+

+  /*

+   * Sets up the GPT timers

+   */

+  gptStart(&GPTD2, &gptcfg1);

+  gptStart(&GPTD3, &gptcfg2);

+

+  /*

+   * Start a continuous timer

+   */

+  gptStartContinuous(&GPTD2, 15625);

+

+  /*

+   * Normal main() thread activity, in this demo it does nothing.

+   */

+  while (true) {

+    if (palReadPad(IOPORT1, KEY1) == 0) {

+      gptStopTimer(&GPTD2);

+      gptStop(&GPTD2);

+      gptStopTimer(&GPTD3);

+      gptStop(&GPTD3);

+    }

+    chThdSleepMilliseconds(500);

+  }

+}

diff --git a/testhal/NRF51/NRF51822/GPT/mcuconf.h b/testhal/NRF51/NRF51822/GPT/mcuconf.h
new file mode 100644
index 0000000..7fd549f
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/mcuconf.h
@@ -0,0 +1,26 @@
+/*

+    Copyright (C) 2015 Stephen Caudle

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef _MCUCONF_H_

+#define _MCUCONF_H_

+

+/*

+ * NRF51 driver system settings.

+ */

+#define NRF51_GPT_USE_TIMER1                 TRUE

+#define NRF51_GPT_USE_TIMER2                 TRUE

+

+#endif /* _MCUCONF_H_ */

diff --git a/testhal/NRF51/NRF51822/GPT/readme.txt b/testhal/NRF51/NRF51822/GPT/readme.txt
new file mode 100644
index 0000000..da5f977
--- /dev/null
+++ b/testhal/NRF51/NRF51822/GPT/readme.txt
@@ -0,0 +1,19 @@
+*****************************************************************************

+** ChibiOS/HAL - GPT driver demo for NRF51x22.                             **

+*****************************************************************************

+

+** TARGET **

+

+The demo runs on an Waveshare BLE400 board.

+

+** The Demo **

+

+The application demonstrates the use of the NRF51x22 GPT driver.

+

+** Board Setup **

+

+** Build Procedure **

+

+The demo has been tested using the free Codesourcery GCC-based toolchain

+and YAGARTO.

+Just modify the TRGT line in the makefile in order to use different GCC ports.