EEPROM: Initial commit

15 files changed, 2852 insertions, 1 deletions

diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index 2802a09..0fcced7 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -11,6 +11,9 @@ HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_hub.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_msd.c \

           ${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_ftdi.c \

-          ${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_uvc.c 

+          ${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_uvc.c \

+	  ${CHIBIOS_CONTRIB}/os/hal/src/ee24xx.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/ee25xx.c \

+          ${CHIBIOS_CONTRIB}/os/hal/src/eeprom.c

 

 HALINC += ${CHIBIOS_CONTRIB}/os/hal/include

diff --git a/os/hal/include/ee24xx.h b/os/hal/include/ee24xx.h
new file mode 100644
index 0000000..ab12fd1
--- /dev/null
+++ b/os/hal/include/ee24xx.h
@@ -0,0 +1,64 @@
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+#ifndef EE24XX_H
+#define EE24XX_H
+
+#include "hal.h"
+
+#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX
+
+#define EEPROM_DEV_24XX 24
+
+/**
+ * @extends EepromFileConfig
+ */
+typedef struct {
+  _eeprom_file_config_data
+  /**
+   * Driver connected to IC.
+   */
+  I2CDriver     *i2cp;
+  /**
+   * Address of IC on I2C bus.
+   */
+  i2caddr_t     addr;
+  /**
+   * Pointer to write buffer. The safest size is (pagesize + 2)
+   */
+  uint8_t       *write_buf;
+} I2CEepromFileConfig;
+
+/**
+ * @brief   @p I2CEepromFileStream specific data.
+ */
+#define _eeprom_file_stream_data_i2c                                       \
+  _eeprom_file_stream_data
+
+/**
+ * @extends EepromFileStream
+ *
+ * @brief   EEPROM file stream driver class for I2C device.
+ */
+typedef struct {
+  const struct EepromFileStreamVMT *vmt;
+  _eeprom_file_stream_data_i2c
+  /* Overwritten parent data member. */
+  const I2CEepromFileConfig *cfg;
+} I2CEepromFileStream;
+
+
+/**
+ * Open I2C EEPROM IC as file and return pointer to the file stream object
+ * @note      Fucntion allways successfully open file. All checking makes
+ *            in read/write functions.
+ */
+#define I2CEepromFileOpen(efs, eepcfg, eepdev) \
+  EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev);
+
+#endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */
+
+#endif // EE24XX_H
diff --git a/os/hal/include/ee25xx.h b/os/hal/include/ee25xx.h
new file mode 100644
index 0000000..fc2ad6f
--- /dev/null
+++ b/os/hal/include/ee25xx.h
@@ -0,0 +1,63 @@
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+#ifndef EE25XX_H
+#define EE25XX_H
+
+#include "hal.h"
+
+#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX
+
+#define EEPROM_DEV_25XX 25
+
+/**
+ * @extends EepromFileConfig
+ */
+typedef struct {
+  _eeprom_file_config_data
+  /**
+   * Driver connected to IC.
+   */
+  SPIDriver       *spip;
+  /**
+   * Config associated with SPI driver.
+   */
+  const SPIConfig *spicfg;
+} SPIEepromFileConfig;
+
+/**
+ * @brief   @p SPIEepromFileStream specific data.
+ */
+#define _eeprom_file_stream_data_spi                                       \
+  _eeprom_file_stream_data
+
+/**
+ * @extends EepromFileStream
+ *
+ * @brief   EEPROM file stream driver class for SPI device.
+ */
+typedef struct {
+  const struct EepromFileStreamVMT *vmt;
+  _eeprom_file_stream_data_spi
+  /* Overwritten parent data member. */
+  const SPIEepromFileConfig *cfg;
+} SPIEepromFileStream;
+
+/**
+ * Open SPI EEPROM IC as file and return pointer to the file stream object
+ * @note      Fucntion allways successfully open file. All checking makes
+ *            in read/write functions.
+ */
+EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs,
+                                    const SPIEepromFileConfig *eepcfg,
+                                    const EepromDevice *eepdev);
+
+#define SPIEepromFileOpen(efs, eepcfg, eepdev) \
+  EepromFileOpen((EepromFileStream *)efs, (EepromFileConfig *)eepcfg, eepdev);
+
+#endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */
+
+#endif // EE25XX_H
diff --git a/os/hal/include/eeprom.h b/os/hal/include/eeprom.h
new file mode 100644
index 0000000..b0fd360
--- /dev/null
+++ b/os/hal/include/eeprom.h
@@ -0,0 +1,147 @@
+/*
+  Copyright (c) 2013 Timon Wong
+
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+
+  The above copyright notice and this permission notice shall be included in all
+  copies or substantial portions of the Software.
+
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+#ifndef __EEPROM_H__
+#define __EEPROM_H__
+
+#include "ch.h"
+#include "hal.h"
+
+#ifndef HAL_USE_EEPROM
+#define HAL_USE_EEPROM FALSE
+#endif
+
+#ifndef EEPROM_USE_EE25XX
+#define EEPROM_USE_EE25XX FALSE
+#endif
+
+#ifndef EEPROM_USE_EE24XX
+#define EEPROM_USE_EE24XX FALSE
+#endif
+
+#if HAL_USE_EEPROM
+
+#if EEPROM_USE_EE25XX && EEPROM_USE_EE24XX
+#define EEPROM_TABLE_SIZE 2
+#elif EEPROM_USE_EE25XX || EEPROM_USE_EE24XX
+#define EEPROM_TABLE_SIZE 1
+#else
+#error "No EEPROM device selected!"
+#endif
+
+#if EEPROM_USE_EE25XX && !HAL_USE_SPI
+#error "25xx enabled but SPI driver is disabled!"
+#endif
+
+#if EEPROM_USE_EE24XX && !HAL_USE_I2C
+#error "24xx enabled but I2C driver is disabled!"
+#endif
+
+#define _eeprom_file_config_data                                            \
+  /* Lower barrier of file in EEPROM memory array. */                       \
+  uint32_t        barrier_low;                                              \
+  /* Higher barrier of file in EEPROM memory array. */                      \
+  uint32_t        barrier_hi;                                               \
+  /* Size of memory array in bytes. */                                      \
+  uint32_t        size;                                                     \
+  /* Size of single page in bytes. */                                       \
+  uint16_t        pagesize;                                                 \
+  /* Time needed by IC for single byte/page writing. */                     \
+  systime_t       write_time;
+  
+typedef uint32_t fileoffset_t;
+
+typedef struct {
+  _eeprom_file_config_data
+} EepromFileConfig;
+
+/**
+ * @brief   @p EepromFileStream specific data.
+ */
+#define _eeprom_file_stream_data                                            \
+  _base_sequential_stream_data                                                    \
+  uint32_t                    errors;                                       \
+  uint32_t                    position;                                     \
+
+/**
+ * @extends BaseFileStreamVMT
+ *
+ * @brief   @p EepromFileStream virtual methods table.
+ */
+struct EepromFileStreamVMT {
+  _file_stream_methods
+};
+
+/**
+ * @extends BaseFileStream
+ *
+ * @brief   EEPROM file stream driver class.
+ * @details This class extends @p BaseFileStream by adding some fields.
+ */
+typedef struct {
+  /** @brief Virtual Methods Table.*/
+  const struct EepromFileStreamVMT *vmt;
+  _eeprom_file_stream_data
+  /** pointer to config object, must be overwritten by all derived classes.*/
+  const EepromFileConfig *cfg;
+} EepromFileStream;
+
+/**
+ * @brief   Low level device descriptor.
+ */
+typedef struct {
+  const uint8_t                       id;
+  const struct EepromFileStreamVMT   *efsvmt;
+} EepromDevice;
+
+const EepromDevice *EepromFindDevice(uint8_t id);
+
+EepromFileStream *EepromFileOpen(EepromFileStream *efs,
+                                 const EepromFileConfig *eepcfg,
+                                 const EepromDevice *eepdev);
+
+uint8_t  EepromReadByte(EepromFileStream *efs);
+uint16_t EepromReadHalfword(EepromFileStream *efs);
+uint32_t EepromReadWord(EepromFileStream *efs);
+size_t EepromWriteByte(EepromFileStream *efs, uint8_t data);
+size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data);
+size_t EepromWriteWord(EepromFileStream *efs, uint32_t data);
+
+msg_t eepfs_getsize(void *ip);
+msg_t eepfs_getposition(void *ip);
+msg_t eepfs_lseek(void *ip, fileoffset_t offset);
+msg_t eepfs_close(void *ip);
+msg_t eepfs_geterror(void *ip);
+msg_t eepfs_put(void *ip, uint8_t b);
+msg_t eepfs_get(void *ip);
+
+#include "ee24xx.h"
+#include "ee25xx.h"
+
+#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */
+#endif /* __EEPROM_H__ */
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index 8a17765..5ed561f 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -37,6 +37,7 @@
 /* Complex drivers.*/

 #include "onewire.h"

 #include "crc.h"

+#include "eeprom.h"

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

diff --git a/os/hal/src/ee24xx.c b/os/hal/src/ee24xx.c
new file mode 100644
index 0000000..c89635f
--- /dev/null
+++ b/os/hal/src/ee24xx.c
@@ -0,0 +1,353 @@
+/*
+  Copyright (c) 2013 Timon Wong
+
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+
+  The above copyright notice and this permission notice shall be included in all
+  copies or substantial portions of the Software.
+
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+/*****************************************************************************
+ * DATASHEET NOTES
+ *****************************************************************************
+Write cycle time (byte or page) - 5 ms
+
+Note:
+  Page write operations are limited to writing bytes within a single physical
+  page, regardless of the number of bytes actually being written. Physical page
+  boundaries start at addresses that are integer multiples of the page buffer
+  size (or page size and end at addresses that are integer multiples of
+  [page size]. If a Page Write command attempts to write across a physical
+  page boundary, the result is that the data wraps around to the beginning of
+  the current page (overwriting data previously stored there), instead of
+  being written to the next page as might be expected.
+*********************************************************************/
+
+#include "ee24xx.h"
+#include <string.h>
+
+#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE24XX) || defined(__DOXYGEN__)
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+/*
+#if defined(SAM7_PLATFORM)
+#define EEPROM_I2C_CLOCK (MCK / (((i2cp->config->cwgr & 0xFF) + ((i2cp->config->cwgr >> 8) & 0xFF)) * (1 << ((i2cp->config->cwgr >> 16) & 7)) + 6))
+#else
+#define EEPROM_I2C_CLOCK (i2cp->config->clock_speed)
+#endif
+*/
+#define EEPROM_I2C_CLOCK 400000
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+
+/*
+ *******************************************************************************
+ * LOCAL FUNCTIONS
+ *******************************************************************************
+ */
+/**
+ * @brief   Split one uint16_t address to two uint8_t.
+ *
+ * @param[in] txbuf pointer to driver transmit buffer
+ * @param[in] addr  uint16_t address
+ */
+#define eeprom_split_addr(txbuf, addr){                                       \
+    (txbuf)[0] = ((uint8_t)((addr >> 8) & 0xFF));                              \
+    (txbuf)[1] = ((uint8_t)(addr & 0xFF));                                     \
+  }
+
+/*
+ *******************************************************************************
+ * EXPORTED FUNCTIONS
+ *******************************************************************************
+ */
+
+/**
+ * @brief     Calculates requred timeout.
+ */
+static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) {
+  (void)i2cp;
+  const uint32_t bitsinbyte = 10;
+  uint32_t tmo;
+  tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000);
+  tmo /= EEPROM_I2C_CLOCK;
+  tmo += 10; /* some additional milliseconds to be safer */
+  return MS2ST(tmo);
+}
+
+/**
+ * @brief   EEPROM read routine.
+ *
+ * @param[in] eepcfg    pointer to configuration structure of eeprom file
+ * @param[in] offset    addres of 1-st byte to be read
+ * @param[in] data      pointer to buffer with data to be written
+ * @param[in] len       number of bytes to be red
+ */
+static msg_t eeprom_read(const I2CEepromFileConfig *eepcfg,
+                         uint32_t offset, uint8_t *data, size_t len) {
+
+  msg_t status = MSG_RESET;
+  systime_t tmo = calc_timeout(eepcfg->i2cp, 2, len);
+
+  osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)),
+             "out of device bounds");
+
+  eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low));
+
+#if I2C_USE_MUTUAL_EXCLUSION
+  i2cAcquireBus(eepcfg->i2cp);
+#endif
+
+  status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr,
+                                    eepcfg->write_buf, 2, data, len, tmo);
+
+#if I2C_USE_MUTUAL_EXCLUSION
+  i2cReleaseBus(eepcfg->i2cp);
+#endif
+
+  return status;
+}
+
+/**
+ * @brief   EEPROM write routine.
+ * @details Function writes data to EEPROM.
+ * @pre     Data must be fit to single EEPROM page.
+ *
+ * @param[in] eepcfg  pointer to configuration structure of eeprom file
+ * @param[in] offset  addres of 1-st byte to be write
+ * @param[in] data    pointer to buffer with data to be written
+ * @param[in] len     number of bytes to be written
+ */
+static msg_t eeprom_write(const I2CEepromFileConfig *eepcfg, uint32_t offset,
+                          const uint8_t *data, size_t len) {
+  msg_t status = MSG_RESET;
+  systime_t tmo = calc_timeout(eepcfg->i2cp, (len + 2), 0);
+
+  osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)),
+             "out of device bounds");
+  osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) ==
+              (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)),
+             "data can not be fitted in single page");
+
+  /* write address bytes */
+  eeprom_split_addr(eepcfg->write_buf, (offset + eepcfg->barrier_low));
+  /* write data bytes */
+  memcpy(&(eepcfg->write_buf[2]), data, len);
+
+#if I2C_USE_MUTUAL_EXCLUSION
+  i2cAcquireBus(eepcfg->i2cp);
+#endif
+
+  status = i2cMasterTransmitTimeout(eepcfg->i2cp, eepcfg->addr,
+                                    eepcfg->write_buf, (len + 2), NULL, 0, tmo);
+
+#if I2C_USE_MUTUAL_EXCLUSION
+  i2cReleaseBus(eepcfg->i2cp);
+#endif
+
+  /* wait until EEPROM process data */
+  chThdSleep(eepcfg->write_time);
+
+  return status;
+}
+
+/**
+ * @brief   Determines and returns size of data that can be processed
+ */
+static size_t __clamp_size(void *ip, size_t n) {
+
+  if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip))
+    return eepfs_getsize(ip) - eepfs_getposition(ip);
+  else
+    return n;
+}
+
+/**
+ * @brief   Write data that can be fitted in one page boundary
+ */
+static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) {
+
+  msg_t status = MSG_RESET;
+
+  osalDbgAssert(len != 0, "something broken in hi level part");
+
+  status = eeprom_write(((I2CEepromFileStream *)ip)->cfg,
+                        eepfs_getposition(ip), data, len);
+  if (status == MSG_OK) {
+    *written += len;
+    eepfs_lseek(ip, eepfs_getposition(ip) + len);
+  }
+}
+
+/**
+ * @brief     Write data to EEPROM.
+ * @details   Only one EEPROM page can be written at once. So fucntion
+ *            splits large data chunks in small EEPROM transactions if needed.
+ * @note      To achieve the maximum effectivity use write operations
+ *            aligned to EEPROM page boundaries.
+ */
+static size_t write(void *ip, const uint8_t *bp, size_t n) {
+
+  size_t   len = 0;     /* bytes to be written at one trasaction */
+  uint32_t written; /* total bytes successfully written */
+  uint16_t pagesize;
+  uint32_t firstpage;
+  uint32_t lastpage;
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  if (n == 0)
+    return 0;
+
+  n = __clamp_size(ip, n);
+  if (n == 0)
+    return 0;
+
+  pagesize  =  ((EepromFileStream *)ip)->cfg->pagesize;
+  firstpage = (((EepromFileStream *)ip)->cfg->barrier_low +
+               eepfs_getposition(ip)) / pagesize;
+  lastpage  = (((EepromFileStream *)ip)->cfg->barrier_low +
+               eepfs_getposition(ip) + n - 1) / pagesize;
+
+  written = 0;
+  /* data fitted in single page */
+  if (firstpage == lastpage) {
+    len = n;
+    __fitted_write(ip, bp, len, &written);
+    bp += len;
+    return written;
+  }
+
+  else {
+    /* write first piece of data to first page boundary */
+    len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
+    len -= ((EepromFileStream *)ip)->cfg->barrier_low;
+    __fitted_write(ip, bp, len, &written);
+    bp += len;
+
+    /* now writes blocks at a size of pages (may be no one) */
+    while ((n - written) > pagesize) {
+      len = pagesize;
+      __fitted_write(ip, bp, len, &written);
+      bp += len;
+    }
+
+    /* wrtie tail */
+    len = n - written;
+    if (len == 0)
+      return written;
+    else {
+      __fitted_write(ip, bp, len, &written);
+    }
+  }
+
+  return written;
+}
+
+/**
+ * Read some bytes from current position in file. After successful
+ * read operation the position pointer will be increased by the number
+ * of read bytes.
+ */
+static size_t read(void *ip, uint8_t *bp, size_t n) {
+  msg_t status = MSG_OK;
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  if (n == 0)
+    return 0;
+
+  n = __clamp_size(ip, n);
+  if (n == 0)
+    return 0;
+
+  /* Stupid I2C cell in STM32F1x does not allow to read single byte.
+     So we must read 2 bytes and return needed one. */
+#if defined(STM32F1XX_I2C)
+  if (n == 1) {
+    uint8_t __buf[2];
+    /* if NOT last byte of file requested */
+    if ((eepfs_getposition(ip) + 1) < eepfs_getsize(ip)) {
+      if (read(ip, __buf, 2) == 2) {
+        eepfs_lseek(ip, (eepfs_getposition(ip) + 1));
+        bp[0] = __buf[0];
+        return 1;
+      }
+      else
+        return 0;
+    }
+    else {
+      eepfs_lseek(ip, (eepfs_getposition(ip) - 1));
+      if (read(ip, __buf, 2) == 2) {
+        eepfs_lseek(ip, (eepfs_getposition(ip) + 2));
+        bp[0] = __buf[1];
+        return 1;
+      }
+      else
+        return 0;
+    }
+  }
+#endif /* defined(STM32F1XX_I2C) */
+
+  /* call low level function */
+  status  = eeprom_read(((I2CEepromFileStream *)ip)->cfg,
+                        eepfs_getposition(ip), bp, n);
+  if (status != MSG_OK)
+    return 0;
+  else {
+    eepfs_lseek(ip, (eepfs_getposition(ip) + n));
+    return n;
+  }
+}
+
+static const struct EepromFileStreamVMT vmt = {
+  write,
+  read,
+  eepfs_put,
+  eepfs_get,
+  eepfs_close,
+  eepfs_geterror,
+  eepfs_getsize,
+  eepfs_getposition,
+  eepfs_lseek,
+};
+
+EepromDevice eepdev_24xx = {
+  EEPROM_DEV_24XX,
+  &vmt
+};
+
+#endif /* EEPROM_USE_EE24XX */
diff --git a/os/hal/src/ee25xx.c b/os/hal/src/ee25xx.c
new file mode 100644
index 0000000..07f4373
--- /dev/null
+++ b/os/hal/src/ee25xx.c
@@ -0,0 +1,404 @@
+/*
+  Copyright (c) 2013 Timon Wong
+
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+
+  The above copyright notice and this permission notice shall be included in all
+  copies or substantial portions of the Software.
+
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+/*****************************************************************************
+ * DATASHEET NOTES
+ *****************************************************************************
+Write cycle time (byte or page) - 5 ms
+
+Note:
+  Page write operations are limited to writing bytes within a single physical
+  page, regardless of the number of bytes actually being written. Physical page
+  boundaries start at addresses that are integer multiples of the page buffer
+  size (or page size and end at addresses that are integer multiples of
+  [page size]. If a Page Write command attempts to write across a physical
+  page boundary, the result is that the data wraps around to the beginning of
+  the current page (overwriting data previously stored there), instead of
+  being written to the next page as might be expected.
+*********************************************************************/
+
+#include "ee25xx.h"
+#include <string.h>
+
+#if (defined(HAL_USE_EEPROM) && HAL_USE_EEPROM && EEPROM_USE_EE25XX) || defined(__DOXYGEN__)
+
+/**
+ * @name Commands of 25XX chip.
+ * @{
+ */
+#define CMD_READ    0x03  /**< @brief Read data from memory array beginning at
+                               selected address. */
+#define CMD_WRITE   0x02  /**< @brief Write data to memory array beginning at
+                               selected address. */
+#define CMD_WRDI    0x04  /**< Reset the write enable latch (disable write
+                               operations). */
+#define CMD_WREN    0x06  /**< Set the write enable latch (enable write
+                               operations). */
+#define CMD_RDSR    0x05  /**< Read STATUS register. */
+#define CMD_WRSR    0x01  /**< Write STATUS register. */
+
+/** @} */
+
+/**
+ * @name Status of 25XX chip.
+ * @{}
+ */
+#define STAT_BP1    0x08  /**< @brief Block protection (high). */
+#define STAT_BP0    0x04  /**< @brief Block protection (low). */
+#define STAT_WEL    0x02  /**< @brief Write enable latch. */
+#define STAT_WIP    0x01  /**< @brief Write-In-Progress. */
+
+/** @} */
+
+/**
+ * @brief 25XX low level write then read rountine.
+ *
+ * @param[in]  eepcfg pointer to configuration structure of eeprom file.
+ * @param[in]  txbuf  pointer to buffer to be transfered.
+ * @param[in]  txlen  number of bytes to be transfered.
+ * @param[out] rxbuf  pointer to buffer to be received.
+ * @param[in]  rxlen  number of bytes to be received.
+ */
+static void ll_25xx_transmit_receive(const SPIEepromFileConfig *eepcfg,
+                                     const uint8_t *txbuf, size_t txlen,
+                                     uint8_t *rxbuf, size_t rxlen) {
+
+#if SPI_USE_MUTUAL_EXCLUSION
+  spiAcquireBus(eepcfg->spip);
+#endif
+  spiSelect(eepcfg->spip);
+  spiSend(eepcfg->spip, txlen, txbuf);
+  if (rxlen) /* Check if receive is needed. */
+      spiReceive(eepcfg->spip, rxlen, rxbuf);
+  spiUnselect(eepcfg->spip);
+
+#if SPI_USE_MUTUAL_EXCLUSION
+  spiReleaseBus(eepcfg->spip);
+#endif
+}
+
+/**
+ * @brief Check whether the device is busy (writing in progress).
+ *
+ * @param[in] eepcfg   pointer to configuration structure of eeprom file.
+ * @return @p true on busy.
+ */
+static bool ll_eeprom_is_busy(const SPIEepromFileConfig *eepcfg) {
+
+  uint8_t cmd = CMD_RDSR;
+  uint8_t stat;
+  ll_25xx_transmit_receive(eepcfg, &cmd, 1, &stat, 1);
+  if (stat & STAT_WIP)
+    return TRUE;
+  return FALSE;
+}
+
+/**
+ * @brief Lock device.
+ *
+ * @param[in] eepcfg  pointer to configuration structure of eeprom file.
+ */
+static void ll_eeprom_lock(const SPIEepromFileConfig *eepcfg) {
+
+  uint8_t cmd = CMD_WRDI;
+  ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0);
+}
+
+/**
+ * @brief Unlock device.
+ *
+ * @param[in] eepcfg  pointer to configuration structure of eeprom file.
+ */
+static void ll_eeprom_unlock(const SPIEepromFileConfig *eepcfg) {
+
+  uint8_t cmd = CMD_WREN;
+  ll_25xx_transmit_receive(eepcfg, &cmd, 1, NULL, 0);
+}
+
+/**
+ * @brief   Prepare byte sequence for command and address
+ *
+ * @param[in] seq   pointer to first 3byte sequence
+ * @param[in] size  size of the eeprom device
+ * @param[in] cmd   command
+ * @param[in] addr  address
+ * @return number of bytes of this sequence
+ */
+static uint8_t ll_eeprom_prepare_seq(uint8_t *seq, uint32_t size, uint8_t cmd,
+                                     uint32_t addr) {
+
+  seq[0] = ((uint8_t)cmd & 0xff);
+
+  if (size > 0xffffUL) {
+    /* High density, 24bit address. */
+    seq[1] = (uint8_t)((addr >> 16) & 0xff);
+    seq[2] = (uint8_t)((addr >> 8) & 0xff);
+    seq[3] = (uint8_t)(addr & 0xff);
+    return 4;
+  }
+  else if (size > 0x00ffUL) {
+    /* Medium density, 16bit address. */
+    seq[1] = (uint8_t)((addr >> 8) & 0xff);
+    seq[2] = (uint8_t)(addr & 0xff);
+    return 3;
+  }
+
+  /* Low density, 8bit address. */
+  seq[1] = (uint8_t)(addr & 0xff);
+  return 2;
+}
+
+/**
+ * @brief   EEPROM read routine.
+ *
+ * @param[in]  eepcfg   pointer to configuration structure of eeprom file.
+ * @param[in]  offset   addres of 1-st byte to be read.
+ * @param[out] data     pointer to buffer with data to be written.
+ * @param[in]  len      number of bytes to be red.
+ */
+static msg_t ll_eeprom_read(const SPIEepromFileConfig *eepcfg, uint32_t offset,
+                            uint8_t *data, size_t len) {
+
+  uint8_t txbuff[4];
+  uint8_t txlen;
+
+  osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)),
+             "out of device bounds");
+
+  if (eepcfg->spip->state != SPI_READY)
+      return MSG_RESET;
+
+  txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_READ,
+                                (offset + eepcfg->barrier_low));
+  ll_25xx_transmit_receive(eepcfg, txbuff, txlen, data, len);
+
+  return MSG_OK;
+}
+
+/**
+ * @brief   EEPROM write routine.
+ * @details Function writes data to EEPROM.
+ * @pre     Data must be fit to single EEPROM page.
+ *
+ * @param[in] eepcfg  pointer to configuration structure of eeprom file.
+ * @param[in] offset  addres of 1-st byte to be writen.
+ * @param[in] data    pointer to buffer with data to be written.
+ * @param[in] len     number of bytes to be written.
+ */
+static msg_t ll_eeprom_write(const SPIEepromFileConfig *eepcfg, uint32_t offset,
+                             const uint8_t *data, size_t len) {
+
+  uint8_t txbuff[4];
+  uint8_t txlen;
+  systime_t now;
+
+  osalDbgAssert(((len <= eepcfg->size) && ((offset + len) <= eepcfg->size)),
+             "out of device bounds");
+  osalDbgAssert((((offset + eepcfg->barrier_low) / eepcfg->pagesize) ==
+              (((offset + eepcfg->barrier_low) + len - 1) / eepcfg->pagesize)),
+             "data can not be fitted in single page");
+
+  if (eepcfg->spip->state != SPI_READY)
+      return MSG_RESET;
+
+  /* Unlock array for writting. */
+  ll_eeprom_unlock(eepcfg);
+
+#if SPI_USE_MUTUAL_EXCLUSION
+  spiAcquireBus(eepcfg->spip);
+#endif
+
+  spiSelect(eepcfg->spip);
+  txlen = ll_eeprom_prepare_seq(txbuff, eepcfg->size, CMD_WRITE,
+                                (offset + eepcfg->barrier_low));
+  spiSend(eepcfg->spip, txlen, txbuff);
+  spiSend(eepcfg->spip, len, data);
+  spiUnselect(eepcfg->spip);
+
+#if SPI_USE_MUTUAL_EXCLUSION
+  spiReleaseBus(eepcfg->spip);
+#endif
+
+  /* Wait until EEPROM process data. */
+  now = chVTGetSystemTimeX();
+  while (ll_eeprom_is_busy(eepcfg)) {
+    if ((chVTGetSystemTimeX() - now) > eepcfg->write_time) {
+      return MSG_TIMEOUT;
+    }
+
+    chThdYield();
+  }
+
+  /* Lock array preventing unexpected access */
+  ll_eeprom_lock(eepcfg);
+  return MSG_OK;
+}
+
+/**
+ * @brief   Determines and returns size of data that can be processed
+ */
+static size_t __clamp_size(void *ip, size_t n) {
+
+  if (((size_t)eepfs_getposition(ip) + n) > (size_t)eepfs_getsize(ip))
+    return eepfs_getsize(ip) - eepfs_getposition(ip);
+  else
+    return n;
+}
+
+/**
+ * @brief   Write data that can be fitted in one page boundary
+ */
+static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *written) {
+
+  msg_t status = MSG_RESET;
+
+  osalDbgAssert(len != 0, "something broken in hi level part");
+
+  status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg,
+                           eepfs_getposition(ip), data, len);
+  if (status == MSG_OK) {
+    *written += len;
+    eepfs_lseek(ip, eepfs_getposition(ip) + len);
+  }
+  return status;
+}
+
+/**
+ * @brief     Write data to EEPROM.
+ * @details   Only one EEPROM page can be written at once. So fucntion
+ *            splits large data chunks in small EEPROM transactions if needed.
+ * @note      To achieve the maximum effectivity use write operations
+ *            aligned to EEPROM page boundaries.
+ */
+static size_t write(void *ip, const uint8_t *bp, size_t n) {
+
+  size_t   len = 0;     /* bytes to be written at one trasaction */
+  uint32_t written; /* total bytes successfully written */
+  uint16_t pagesize;
+  uint32_t firstpage;
+  uint32_t lastpage;
+
+  volatile const SPIEepromFileConfig *cfg = ((SPIEepromFileStream *)ip)->cfg;
+
+  osalDbgCheck((ip != NULL) && (((SPIEepromFileStream *)ip)->vmt != NULL));
+
+  if (n == 0)
+    return 0;
+
+  n = __clamp_size(ip, n);
+  if (n == 0)
+    return 0;
+
+  pagesize  = cfg->pagesize;
+  firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize;
+  lastpage  = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize;
+
+  written = 0;
+  /* data fitted in single page */
+  if (firstpage == lastpage) {
+    len = n;
+    __fitted_write(ip, bp, len, &written);
+    bp += len;
+    return written;
+  }
+  else {
+    /* write first piece of data to first page boundary */
+    len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
+    len -= cfg->barrier_low;
+    __fitted_write(ip, bp, len, &written);
+    bp += len;
+
+    /* now writes blocks at a size of pages (may be no one) */
+    while ((n - written) > pagesize) {
+      len = pagesize;
+      if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts...
+        return written;
+
+      bp += len;
+    }
+
+
+    /* wrtie tail */
+    len = n - written;
+    if (len == 0)
+      return written;
+    else {
+      __fitted_write(ip, bp, len, &written);
+    }
+  }
+
+  return written;
+}
+
+/**
+ * Read some bytes from current position in file. After successful
+ * read operation the position pointer will be increased by the number
+ * of read bytes.
+ */
+static size_t read(void *ip, uint8_t *bp, size_t n) {
+
+  msg_t status = MSG_OK;
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  if (n == 0)
+    return 0;
+
+  n = __clamp_size(ip, n);
+  if (n == 0)
+    return 0;
+
+  /* call low level function */
+  status = ll_eeprom_read(((SPIEepromFileStream *)ip)->cfg,
+                          eepfs_getposition(ip), bp, n);
+  if (status != MSG_OK)
+    return 0;
+  else {
+    eepfs_lseek(ip, (eepfs_getposition(ip) + n));
+    return n;
+  }
+}
+
+static const struct EepromFileStreamVMT vmt = {
+  write,
+  read,
+  eepfs_put,
+  eepfs_get,
+  eepfs_close,
+  eepfs_geterror,
+  eepfs_getsize,
+  eepfs_getposition,
+  eepfs_lseek,
+};
+
+EepromDevice eepdev_25xx = {
+  EEPROM_DEV_25XX,
+  &vmt
+};
+
+#endif /* EEPROM_USE_EE25XX */
diff --git a/os/hal/src/eeprom.c b/os/hal/src/eeprom.c
new file mode 100644
index 0000000..60d90ed
--- /dev/null
+++ b/os/hal/src/eeprom.c
@@ -0,0 +1,197 @@
+/*
+  Copyright (c) 2013 Timon Wong
+
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+
+  The above copyright notice and this permission notice shall be included in all
+  copies or substantial portions of the Software.
+
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+/*
+  Copyright 2012 Uladzimir Pylinski aka barthess.
+  You may use this work without restrictions, as long as this notice is included.
+  The work is provided "as is" without warranty of any kind, neither express nor implied.
+*/
+
+#include "eeprom.h"
+#include <string.h>
+
+#if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM
+
+extern EepromDevice eepdev_24xx;
+extern EepromDevice eepdev_25xx;
+
+EepromDevice *__eeprom_drv_table[] = {
+  /* I2C related. */
+#if HAL_USE_I2C
+
+# if EEPROM_USE_EE24XX
+  &eepdev_24xx,
+# endif
+
+#endif /* HAL_USE_I2C */
+
+  /* SPI related. */
+#if HAL_USE_SPI
+
+# if EEPROM_USE_EE25XX
+  &eepdev_25xx,
+# endif
+
+#endif /* HAL_USE_SPI */
+};
+
+
+/**
+ * @breif  Find low level EEPROM device by id.
+ */
+const EepromDevice *EepromFindDevice(uint8_t id) {
+
+  uint8_t i;
+  const EepromDevice *drv;
+
+  for (i = 0; i < EEPROM_TABLE_SIZE; i++) {
+    drv = __eeprom_drv_table[i];
+    if (drv->id == id) {
+      return drv;
+    }
+  }
+
+  return NULL;
+}
+
+/**
+ * Open EEPROM IC as file and return pointer to the file stream object
+ * @note      Fucntion allways successfully open file. All checking makes
+ *            in read/write functions.
+ */
+EepromFileStream *EepromFileOpen(EepromFileStream *efs,
+                                 const EepromFileConfig *eepcfg,
+                                 const EepromDevice *eepdev) {
+
+  osalDbgAssert((efs != NULL) && (eepcfg != NULL) && (eepdev != NULL) &&
+             (eepdev->efsvmt != NULL), "EepromFileOpen");
+  osalDbgAssert(efs->vmt != eepdev->efsvmt, "File allready opened");
+  osalDbgAssert(eepcfg->barrier_hi > eepcfg->barrier_low, "Low barrier exceeds High barrier");
+  osalDbgAssert(eepcfg->pagesize < eepcfg->size, "Pagesize cannot be lager than EEPROM size");
+  osalDbgAssert(eepcfg->barrier_hi <= eepcfg->size, "Barrier exceeds EEPROM size");
+
+  efs->vmt      = eepdev->efsvmt;
+  efs->cfg      = eepcfg;
+  efs->errors   = FILE_OK;
+  efs->position = 0;
+  return (EepromFileStream *)efs;
+}
+
+uint8_t EepromReadByte(EepromFileStream *efs) {
+
+  uint8_t buf;
+  fileStreamRead(efs, &buf, sizeof(buf));
+  return buf;
+}
+
+uint16_t EepromReadHalfword(EepromFileStream *efs) {
+
+  uint16_t buf;
+  fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf));
+  return buf;
+}
+
+uint32_t EepromReadWord(EepromFileStream *efs) {
+
+  uint32_t buf;
+  fileStreamRead(efs, (uint8_t *)&buf, sizeof(buf));
+  return buf;
+}
+
+size_t EepromWriteByte(EepromFileStream *efs, uint8_t data) {
+
+  return fileStreamWrite(efs, &data, sizeof(data));
+}
+
+size_t EepromWriteHalfword(EepromFileStream *efs, uint16_t data) {
+
+  return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data));
+}
+
+size_t EepromWriteWord(EepromFileStream *efs, uint32_t data) {
+
+  return fileStreamWrite(efs, (uint8_t *)&data, sizeof(data));
+}
+
+msg_t eepfs_getsize(void *ip) {
+
+  uint32_t h, l;
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL) &&
+             (((EepromFileStream *)ip)->cfg != NULL));
+
+  h = ((EepromFileStream *)ip)->cfg->barrier_hi;
+  l = ((EepromFileStream *)ip)->cfg->barrier_low;
+  return  h - l;
+}
+
+msg_t eepfs_getposition(void *ip) {
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  return ((EepromFileStream *)ip)->position;
+}
+
+msg_t eepfs_lseek(void *ip, fileoffset_t offset) {
+
+  uint32_t size;
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  size = eepfs_getsize(ip);
+  if (offset > size)
+    offset = size;
+  ((EepromFileStream *)ip)->position = offset;
+  return offset;
+}
+
+msg_t eepfs_close(void *ip) {
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+
+  ((EepromFileStream *)ip)->errors   = FILE_OK;
+  ((EepromFileStream *)ip)->position = 0;
+  ((EepromFileStream *)ip)->vmt      = NULL;
+  ((EepromFileStream *)ip)->cfg      = NULL;
+  return FILE_OK;
+}
+
+msg_t eepfs_geterror(void *ip) {
+
+  osalDbgCheck((ip != NULL) && (((EepromFileStream *)ip)->vmt != NULL));
+  return ((EepromFileStream *)ip)->errors;
+}
+
+msg_t eepfs_put(void *ip, uint8_t b) {
+
+  (void)ip;
+  (void)b;
+  return 0;
+}
+
+msg_t eepfs_get(void *ip) {
+
+  (void)ip;
+  return 0;
+}
+
+#endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */
diff --git a/testhal/STM32/STM32F3xx/EEProm/Makefile b/testhal/STM32/STM32F3xx/EEProm/Makefile
new file mode 100644
index 0000000..25030d8
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/Makefile
@@ -0,0 +1,217 @@
+##############################################################################

+# Build global options

+# NOTE: Can be overridden externally.

+#

+

+# Compiler options here.

+ifeq ($(USE_OPT),)

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16

+endif

+

+# C specific options here (added to USE_OPT).

+ifeq ($(USE_COPT),)

+  USE_COPT = 

+endif

+

+# C++ specific options here (added to USE_OPT).

+ifeq ($(USE_CPPOPT),)

+  USE_CPPOPT = -fno-rtti

+endif

+

+# Enable this if you want the linker to remove unused code and data

+ifeq ($(USE_LINK_GC),)

+  USE_LINK_GC = yes

+endif

+

+# Linker extra options here.

+ifeq ($(USE_LDOPT),)

+  USE_LDOPT = 

+endif

+

+# Enable this if you want link time optimizations (LTO)

+ifeq ($(USE_LTO),)

+  USE_LTO = yes

+endif

+

+# If enabled, this option allows to compile the application in THUMB mode.

+ifeq ($(USE_THUMB),)

+  USE_THUMB = yes

+endif

+

+# Enable this if you want to see the full log while compiling.

+ifeq ($(USE_VERBOSE_COMPILE),)

+  USE_VERBOSE_COMPILE = no

+endif

+

+# If enabled, this option makes the build process faster by not compiling

+# modules not used in the current configuration.

+ifeq ($(USE_SMART_BUILD),)

+  USE_SMART_BUILD = yes

+endif

+

+#

+# Build global options

+##############################################################################

+

+##############################################################################

+# Architecture or project specific options

+#

+

+# Stack size to be allocated to the Cortex-M process stack. This stack is

+# the stack used by the main() thread.

+ifeq ($(USE_PROCESS_STACKSIZE),)

+  USE_PROCESS_STACKSIZE = 0x400

+endif

+

+# Stack size to the allocated to the Cortex-M main/exceptions stack. This

+# stack is used for processing interrupts and exceptions.

+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)

+  USE_EXCEPTIONS_STACKSIZE = 0x400

+endif

+

+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).

+ifeq ($(USE_FPU),)

+  USE_FPU = no

+endif

+

+#

+# Architecture or project specific options

+##############################################################################

+

+##############################################################################

+# Project, sources and paths

+#

+

+# Define project name here

+PROJECT = ch

+

+# Imported source files and paths

+CHIBIOS = ../../../../../ChibiOS-RT

+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib

+# Startup files.

+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk

+# HAL-OSAL files (optional).

+include $(CHIBIOS_CONTRIB)/os/hal/hal.mk

+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk

+include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk

+include $(CHIBIOS)/os/hal/osal/rt/osal.mk

+# RTOS files (optional).

+include $(CHIBIOS)/os/rt/rt.mk

+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk

+# Other files (optional).

+#include $(CHIBIOS)/test/rt/test.mk

+

+# Define linker script file here

+LDSCRIPT= $(STARTUPLD)/STM32F303xC.ld

+

+# C sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CSRC = $(STARTUPSRC) \

+       $(KERNSRC) \

+       $(PORTSRC) \

+       $(OSALSRC) \

+       $(HALSRC) \

+       $(PLATFORMSRC) \

+       $(BOARDSRC) \

+       $(TESTSRC) \

+       main.c

+

+# C++ sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CPPSRC =

+

+# C sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACSRC =

+

+# C++ sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACPPSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCPPSRC =

+

+# List ASM source files here

+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)

+

+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \

+         $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \

+         $(CHIBIOS)/os/various

+

+#

+# Project, sources and paths

+##############################################################################

+

+##############################################################################

+# Compiler settings

+#

+

+MCU  = cortex-m4

+

+#TRGT = arm-elf-

+TRGT = arm-none-eabi-

+CC   = $(TRGT)gcc

+CPPC = $(TRGT)g++

+# Enable loading with g++ only if you need C++ runtime support.

+# NOTE: You can use C++ even without C++ support if you are careful. C++

+#       runtime support makes code size explode.

+LD   = $(TRGT)gcc

+#LD   = $(TRGT)g++

+CP   = $(TRGT)objcopy

+AS   = $(TRGT)gcc -x assembler-with-cpp

+AR   = $(TRGT)ar

+OD   = $(TRGT)objdump

+SZ   = $(TRGT)size

+HEX  = $(CP) -O ihex

+BIN  = $(CP) -O binary

+

+# ARM-specific options here

+AOPT =

+

+# THUMB-specific options here

+TOPT = -mthumb -DTHUMB

+

+# Define C warning options here

+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes

+

+# Define C++ warning options here

+CPPWARN = -Wall -Wextra -Wundef

+

+#

+# Compiler settings

+##############################################################################

+

+##############################################################################

+# Start of user section

+#

+

+# List all user C define here, like -D_DEBUG=1

+UDEFS =

+

+# Define ASM defines here

+UADEFS =

+

+# List all user directories here

+UINCDIR =

+

+# List the user directory to look for the libraries here

+ULIBDIR =

+

+# List all user libraries here

+ULIBS =

+

+#

+# End of user defines

+##############################################################################

+

+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC

+include $(RULESPATH)/rules.mk

diff --git a/testhal/STM32/STM32F3xx/EEProm/chconf.h b/testhal/STM32/STM32F3xx/EEProm/chconf.h
new file mode 100644
index 0000000..405149b
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/chconf.h
@@ -0,0 +1,499 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/chconf.h

+ * @brief   Configuration file template.

+ * @details A copy of this file must be placed in each project directory, it

+ *          contains the application specific kernel settings.

+ *

+ * @addtogroup config

+ * @details Kernel related settings and hooks.

+ * @{

+ */

+

+#ifndef _CHCONF_H_

+#define _CHCONF_H_

+

+/*===========================================================================*/

+/**

+ * @name System timers settings

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   System time counter resolution.

+ * @note    Allowed values are 16 or 32 bits.

+ */

+#define CH_CFG_ST_RESOLUTION                32

+

+/**

+ * @brief   System tick frequency.

+ * @details Frequency of the system timer that drives the system ticks. This

+ *          setting also defines the system tick time unit.

+ */

+#define CH_CFG_ST_FREQUENCY                 10000

+

+/**

+ * @brief   Time delta constant for the tick-less mode.

+ * @note    If this value is zero then the system uses the classic

+ *          periodic tick. This value represents the minimum number

+ *          of ticks that is safe to specify in a timeout directive.

+ *          The value one is not valid, timeouts are rounded up to

+ *          this value.

+ */

+#define CH_CFG_ST_TIMEDELTA                 2

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel parameters and options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Round robin interval.

+ * @details This constant is the number of system ticks allowed for the

+ *          threads before preemption occurs. Setting this value to zero

+ *          disables the preemption for threads with equal priority and the

+ *          round robin becomes cooperative. Note that higher priority

+ *          threads can still preempt, the kernel is always preemptive.

+ * @note    Disabling the round robin preemption makes the kernel more compact

+ *          and generally faster.

+ * @note    The round robin preemption is not supported in tickless mode and

+ *          must be set to zero in that case.

+ */

+#define CH_CFG_TIME_QUANTUM                 0

+

+/**

+ * @brief   Managed RAM size.

+ * @details Size of the RAM area to be managed by the OS. If set to zero

+ *          then the whole available RAM is used. The core memory is made

+ *          available to the heap allocator and/or can be used directly through

+ *          the simplified core memory allocator.

+ *

+ * @note    In order to let the OS manage the whole RAM the linker script must

+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.

+ * @note    Requires @p CH_CFG_USE_MEMCORE.

+ */

+#define CH_CFG_MEMCORE_SIZE                 0

+

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread. The application @p main()

+ *          function becomes the idle thread and must implement an

+ *          infinite loop.

+ */

+#define CH_CFG_NO_IDLE_THREAD               FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Performance options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   OS optimization.

+ * @details If enabled then time efficient rather than space efficient code

+ *          is used when two possible implementations exist.

+ *

+ * @note    This is not related to the compiler optimization options.

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_OPTIMIZE_SPEED               TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Subsystem options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Time Measurement APIs.

+ * @details If enabled then the time measurement APIs are included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_TM                       TRUE

+

+/**

+ * @brief   Threads registry APIs.

+ * @details If enabled then the registry APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_REGISTRY                 TRUE

+

+/**

+ * @brief   Threads synchronization APIs.

+ * @details If enabled then the @p chThdWait() function is included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_WAITEXIT                 TRUE

+

+/**

+ * @brief   Semaphores APIs.

+ * @details If enabled then the Semaphores APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_SEMAPHORES               TRUE

+

+/**

+ * @brief   Semaphores queuing mode.

+ * @details If enabled then the threads are enqueued on semaphores by

+ *          priority rather than in FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE

+

+/**

+ * @brief   Mutexes APIs.

+ * @details If enabled then the mutexes APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MUTEXES                  TRUE

+

+/**

+ * @brief   Enables recursive behavior on mutexes.

+ * @note    Recursive mutexes are heavier and have an increased

+ *          memory footprint.

+ *

+ * @note    The default is @p FALSE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE

+

+/**

+ * @brief   Conditional Variables APIs.

+ * @details If enabled then the conditional variables APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MUTEXES.

+ */

+#define CH_CFG_USE_CONDVARS                 TRUE

+

+/**

+ * @brief   Conditional Variables APIs with timeout.

+ * @details If enabled then the conditional variables APIs with timeout

+ *          specification are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_CONDVARS.

+ */

+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE

+

+/**

+ * @brief   Events Flags APIs.

+ * @details If enabled then the event flags APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_EVENTS                   TRUE

+

+/**

+ * @brief   Events Flags APIs with timeout.

+ * @details If enabled then the events APIs with timeout specification

+ *          are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_EVENTS.

+ */

+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE

+

+/**

+ * @brief   Synchronous Messages APIs.

+ * @details If enabled then the synchronous messages APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MESSAGES                 TRUE

+

+/**

+ * @brief   Synchronous Messages queuing mode.

+ * @details If enabled then messages are served by priority rather than in

+ *          FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special

+ *          requirements.

+ * @note    Requires @p CH_CFG_USE_MESSAGES.

+ */

+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE

+

+/**

+ * @brief   Mailboxes APIs.

+ * @details If enabled then the asynchronous messages (mailboxes) APIs are

+ *          included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.

+ */

+#define CH_CFG_USE_MAILBOXES                TRUE

+

+/**

+ * @brief   I/O Queues APIs.

+ * @details If enabled then the I/O queues APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_QUEUES                   TRUE

+

+/**

+ * @brief   Core Memory Manager APIs.

+ * @details If enabled then the core memory manager APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMCORE                  TRUE

+

+/**

+ * @brief   Heap Allocator APIs.

+ * @details If enabled then the memory heap allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or

+ *          @p CH_CFG_USE_SEMAPHORES.

+ * @note    Mutexes are recommended.

+ */

+#define CH_CFG_USE_HEAP                     TRUE

+

+/**

+ * @brief   Memory Pools Allocator APIs.

+ * @details If enabled then the memory pools allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#define CH_CFG_USE_MEMPOOLS                 TRUE

+

+/**

+ * @brief   Dynamic Threads APIs.

+ * @details If enabled then the dynamic threads creation APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_CFG_USE_WAITEXIT.

+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.

+ */

+#define CH_CFG_USE_DYNAMIC                  TRUE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Debug options

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Debug option, kernel statistics.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_STATISTICS                   TRUE

+

+/**

+ * @brief   Debug option, system state check.

+ * @details If enabled the correct call protocol for system APIs is checked

+ *          at runtime.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE

+

+/**

+ * @brief   Debug option, parameters checks.

+ * @details If enabled then the checks on the API functions input

+ *          parameters are activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_CHECKS                TRUE

+

+/**

+ * @brief   Debug option, consistency checks.

+ * @details If enabled then all the assertions in the kernel code are

+ *          activated. This includes consistency checks inside the kernel,

+ *          runtime anomalies and port-defined checks.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_ASSERTS               TRUE

+

+/**

+ * @brief   Debug option, trace buffer.

+ * @details If enabled then the context switch circular trace buffer is

+ *          activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_ENABLE_TRACE                 TRUE

+

+/**

+ * @brief   Debug option, stack checks.

+ * @details If enabled then a runtime stack check is performed.

+ *

+ * @note    The default is @p FALSE.

+ * @note    The stack check is performed in a architecture/port dependent way.

+ *          It may not be implemented or some ports.

+ * @note    The default failure mode is to halt the system with the global

+ *          @p panic_msg variable set to @p NULL.

+ */

+#define CH_DBG_ENABLE_STACK_CHECK           TRUE

+

+/**

+ * @brief   Debug option, stacks initialization.

+ * @details If enabled then the threads working area is filled with a byte

+ *          value when a thread is created. This can be useful for the

+ *          runtime measurement of the used stack.

+ *

+ * @note    The default is @p FALSE.

+ */

+#define CH_DBG_FILL_THREADS                 TRUE

+

+/**

+ * @brief   Debug option, threads profiling.

+ * @details If enabled then a field is added to the @p thread_t structure that

+ *          counts the system ticks occurred while executing the thread.

+ *

+ * @note    The default is @p FALSE.

+ * @note    This debug option is not currently compatible with the

+ *          tickless mode.

+ */

+#define CH_DBG_THREADS_PROFILING            FALSE

+

+/** @} */

+

+/*===========================================================================*/

+/**

+ * @name Kernel hooks

+ * @{

+ */

+/*===========================================================================*/

+

+/**

+ * @brief   Threads descriptor structure extension.

+ * @details User fields added to the end of the @p thread_t structure.

+ */

+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \

+  /* Add threads custom fields here.*/

+

+/**

+ * @brief   Threads initialization hook.

+ * @details User initialization code added to the @p chThdInit() API.

+ *

+ * @note    It is invoked from within @p chThdInit() and implicitly from all

+ *          the threads creation APIs.

+ */

+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \

+  /* Add threads initialization code here.*/                                \

+}

+

+/**

+ * @brief   Threads finalization hook.

+ * @details User finalization code added to the @p chThdExit() API.

+ *

+ * @note    It is inserted into lock zone.

+ * @note    It is also invoked when the threads simply return in order to

+ *          terminate.

+ */

+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \

+  /* Add threads finalization code here.*/                                  \

+}

+

+/**

+ * @brief   Context switch hook.

+ * @details This hook is invoked just before switching between threads.

+ */

+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \

+  /* Context switch code here.*/                                            \

+}

+

+/**

+ * @brief   Idle thread enter hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to activate a power saving mode.

+ */

+#define CH_CFG_IDLE_ENTER_HOOK() {                                          \

+}

+

+/**

+ * @brief   Idle thread leave hook.

+ * @note    This hook is invoked within a critical zone, no OS functions

+ *          should be invoked from here.

+ * @note    This macro can be used to deactivate a power saving mode.

+ */

+#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \

+}

+

+/**

+ * @brief   Idle Loop hook.

+ * @details This hook is continuously invoked by the idle thread loop.

+ */

+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \

+  /* Idle loop code here.*/                                                 \

+}

+

+/**

+ * @brief   System tick event hook.

+ * @details This hook is invoked in the system tick handler immediately

+ *          after processing the virtual timers queue.

+ */

+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \

+  /* System tick event code here.*/                                         \

+}

+

+/**

+ * @brief   System halt hook.

+ * @details This hook is invoked in case to a system halting error before

+ *          the system is halted.

+ */

+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \

+  /* System halt code here.*/                                               \

+}

+

+/** @} */

+

+/*===========================================================================*/

+/* Port-specific settings (override port settings defaulted in chcore.h).    */

+/*===========================================================================*/

+

+#endif  /* _CHCONF_H_ */

+

+/** @} */

diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf.h b/testhal/STM32/STM32F3xx/EEProm/halconf.h
new file mode 100644
index 0000000..42c228e
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/halconf.h
@@ -0,0 +1,387 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    templates/halconf.h

+ * @brief   HAL configuration header.

+ * @details HAL configuration file, this file allows to enable or disable the

+ *          various device drivers from your application. You may also use

+ *          this file in order to override the device drivers default settings.

+ *

+ * @addtogroup HAL_CONF

+ * @{

+ */

+

+#ifndef _HALCONF_H_

+#define _HALCONF_H_

+

+#include "mcuconf.h"

+

+/**

+ * @brief   Enables the PAL subsystem.

+ */

+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

+#define HAL_USE_PAL                 TRUE

+#endif

+

+/**

+ * @brief   Enables the ADC subsystem.

+ */

+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

+#define HAL_USE_ADC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the CAN subsystem.

+ */

+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)

+#define HAL_USE_CAN                 FALSE

+#endif

+

+/**

+ * @brief   Enables the DAC subsystem.

+ */

+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)

+#define HAL_USE_DAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EXT subsystem.

+ */

+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)

+#define HAL_USE_EXT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the I2C subsystem.

+ */

+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

+#define HAL_USE_I2C                 TRUE

+#endif

+

+/**

+ * @brief   Enables the I2S subsystem.

+ */

+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)

+#define HAL_USE_I2S                 FALSE

+#endif

+

+/**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MAC subsystem.

+ */

+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

+#define HAL_USE_MAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MMC_SPI subsystem.

+ */

+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_MMC_SPI             FALSE

+#endif

+

+/**

+ * @brief   Enables the PWM subsystem.

+ */

+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

+#define HAL_USE_PWM                 FALSE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)

+#define HAL_USE_RTC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL subsystem.

+ */

+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL              FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB          FALSE

+#endif

+

+/**

+ * @brief   Enables the SPI subsystem.

+ */

+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_SPI                 TRUE

+#endif

+

+/**

+ * @brief   Enables the UART subsystem.

+ */

+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

+#define HAL_USE_UART                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                 FALSE

+#endif

+

+/**

+ * @brief   Enables the WDG subsystem.

+ */

+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)

+#define HAL_USE_WDG                 TRUE

+#endif

+

+/*===========================================================================*/

+/* ADC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

+#define ADC_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define ADC_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* CAN driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Sleep mode related APIs inclusion switch.

+ */

+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)

+#define CAN_USE_SLEEP_MODE          TRUE

+#endif

+

+/*===========================================================================*/

+/* I2C driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* MAC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)

+#define MAC_USE_ZERO_COPY           FALSE

+#endif

+

+/**

+ * @brief   Enables an event sources for incoming packets.

+ */

+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)

+#define MAC_USE_EVENTS              TRUE

+#endif

+

+/*===========================================================================*/

+/* MMC_SPI driver related settings.                                          */

+/*===========================================================================*/

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ *          This option is recommended also if the SPI driver does not

+ *          use a DMA channel and heavily loads the CPU.

+ */

+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)

+#define MMC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intervals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY              100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT             FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SERIAL driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Default bit rate.

+ * @details Configuration parameter, this is the baud rate selected for the

+ *          default configuration.

+ */

+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

+#define SERIAL_DEFAULT_BITRATE      38400

+#endif

+

+/**

+ * @brief   Serial buffers size.

+ * @details Configuration parameter, you can change the depth of the queue

+ *          buffers depending on the requirements of your application.

+ * @note    The default is 16 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_BUFFERS_SIZE         16

+#endif

+

+/*===========================================================================*/

+/* SERIAL_USB driver related setting.                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   Serial over USB buffers size.

+ * @details Configuration parameter, the buffer size must be a multiple of

+ *          the USB data endpoint maximum packet size.

+ * @note    The default is 256 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_SIZE     256

+#endif

+

+/**

+ * @brief   Serial over USB number of buffers.

+ * @note    The default is 2 buffers.

+ */

+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)

+#define SERIAL_USB_BUFFERS_NUMBER   2

+#endif

+

+/*===========================================================================*/

+/* SPI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)

+#define SPI_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define SPI_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* UART driver related settings.                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)

+#define UART_USE_WAIT               FALSE

+#endif

+

+/**

+ * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define UART_USE_MUTUAL_EXCLUSION   FALSE

+#endif

+

+/*===========================================================================*/

+/* USB driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)

+#define USB_USE_WAIT                FALSE

+#endif

+

+/*===========================================================================*/

+/* Community drivers's includes                                              */

+/*===========================================================================*/

+

+#include "halconf_community.h"

+

+#endif /* _HALCONF_H_ */

+

+/** @} */

diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h
new file mode 100644
index 0000000..06f35b1
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h
@@ -0,0 +1,114 @@
+/*

+    ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef _HALCONF_COMMUNITY_H_

+#define _HALCONF_COMMUNITY_H_

+

+/**

+ * @brief   Enables the community overlay.

+ */

+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)

+#define HAL_USE_COMMUNITY           TRUE

+#endif

+

+/**

+ * @brief   Enables the FSMC subsystem.

+ */

+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)

+#define HAL_USE_FSMC                FALSE

+#endif

+

+/**

+ * @brief   Enables the NAND subsystem.

+ */

+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)

+#define HAL_USE_NAND                FALSE

+#endif

+

+/**

+ * @brief   Enables the 1-wire subsystem.

+ */

+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)

+#define HAL_USE_ONEWIRE             FALSE

+#endif

+

+/**

+ * @brief   Enables the EICU subsystem.

+ */

+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)

+#define HAL_USE_EICU                FALSE

+#endif

+

+/**

+ * @brief   Enables the community subsystem.

+ */

+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)

+#define HAL_USE_CRC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EEPROM subsystem.

+ */

+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)

+#define HAL_USE_EEPROM            TRUE

+#endif

+

+/*===========================================================================*/

+/* FSMCNAND driver related settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define NAND_USE_MUTUAL_EXCLUSION   TRUE

+#endif

+

+/*===========================================================================*/

+/* 1-wire driver related settings.                                           */

+/*===========================================================================*/

+/**

+ * @brief   Enables strong pull up feature.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define ONEWIRE_USE_STRONG_PULLUP   FALSE

+

+/**

+ * @brief   Enables search ROM feature.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define ONEWIRE_USE_SEARCH_ROM      TRUE

+

+ /*===========================================================================*/

+/* EEProm driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables 24xx series I2C eeprom device driver.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define EEPROM_USE_EE24XX TRUE

+ /**

+ * @brief   Enables 25xx series SPI eeprom device driver.

+ * @note    Disabling this option saves both code and data space.

+ */

+#define EEPROM_USE_EE25XX TRUE

+

+

+#endif /* _HALCONF_COMMUNITY_H_ */

+

+/** @} */

diff --git a/testhal/STM32/STM32F3xx/EEProm/main.c b/testhal/STM32/STM32F3xx/EEProm/main.c
new file mode 100644
index 0000000..130a600
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/main.c
@@ -0,0 +1,99 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#include "ch.h"

+#include "hal.h"

+

+#define EEPROM_SIZE 8192 // 64Kb, 8KB

+#define EEPROM_PAGE_SIZE 32

+#define EEPROM_WRITE_TIME_MS 10 // byte/page write time

+#define EEPROM_SPID SPID1

+#define EEPROM_SPIDCONFIG spi1cfg

+

+static const SPIConfig EEPROM_SPIDCONFIG = {

+  NULL,

+  GPIOA,

+  12,

+  0, // Up to 20Mhz

+  SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0

+};

+

+static SPIEepromFileConfig eeCfg = {

+  0,

+  EEPROM_SIZE,

+  EEPROM_SIZE,

+  EEPROM_PAGE_SIZE,

+  MS2ST(EEPROM_WRITE_TIME_MS),

+  &EEPROM_SPID,

+  &EEPROM_SPIDCONFIG,

+};

+

+static SPIEepromFileStream eeFile;

+static EepromFileStream *eeFS;

+

+static uint8_t buffer[64];

+

+THD_WORKING_AREA(waThreadEE, 256);

+static THD_FUNCTION(ThreadEE, arg)

+{

+  (void)arg;

+  uint8_t len = 64;

+

+  while (TRUE)

+  {

+

+    eeFS = SPIEepromFileOpen(&eeFile, &eeCfg, EepromFindDevice(EEPROM_DEV_25XX));

+    fileStreamSeek(eeFS, 0);

+

+    fileStreamWrite(eeFS, buffer, len);

+    fileStreamRead(eeFS, buffer, len);

+

+    fileStreamClose(eeFS);

+

+    chThdSleepMilliseconds(500);

+  }

+

+  return;

+}

+

+/*

+ * Application entry point.

+ */

+int main(void) {

+

+  /*

+   * System initializations.

+   * - HAL initialization, this also initializes the configured device drivers

+   *   and performs the board-specific initializations.

+   * - Kernel initialization, the main() function becomes a thread and the

+   *   RTOS is active.

+   */

+  halInit();

+  chSysInit();

+

+  spiStart(&EEPROM_SPID, &EEPROM_SPIDCONFIG);

+

+  chThdCreateStatic(waThreadEE, sizeof(waThreadEE), NORMALPRIO, ThreadEE, NULL);

+

+  /*

+   * Normal main() thread activity, it resets the watchdog.

+   */

+  while (true) {

+    palToggleLine(LINE_LED4_BLUE);

+    chThdSleepMilliseconds(500);

+  }

+  return 0;

+}

diff --git a/testhal/STM32/STM32F3xx/EEProm/mcuconf.h b/testhal/STM32/STM32F3xx/EEProm/mcuconf.h
new file mode 100644
index 0000000..60b9854
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/mcuconf.h
@@ -0,0 +1,258 @@
+/*

+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+#ifndef _MCUCONF_H_

+#define _MCUCONF_H_

+

+/*

+ * STM32F3xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+#define STM32F3xx_MCUCONF

+

+/*

+ * HAL driver system settings.

+ */

+#define STM32_NO_INIT                       FALSE

+#define STM32_PVD_ENABLE                    FALSE

+#define STM32_PLS                           STM32_PLS_LEV0

+#define STM32_HSI_ENABLED                   TRUE

+#define STM32_LSI_ENABLED                   TRUE

+#define STM32_HSE_ENABLED                   TRUE

+#define STM32_LSE_ENABLED                   FALSE

+#define STM32_SW                            STM32_SW_PLL

+#define STM32_PLLSRC                        STM32_PLLSRC_HSE

+#define STM32_PREDIV_VALUE                  1

+#define STM32_PLLMUL_VALUE                  9

+#define STM32_HPRE                          STM32_HPRE_DIV1

+#define STM32_PPRE1                         STM32_PPRE1_DIV2

+#define STM32_PPRE2                         STM32_PPRE2_DIV2

+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK

+#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1

+#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1

+#define STM32_USART1SW                      STM32_USART1SW_PCLK

+#define STM32_USART2SW                      STM32_USART2SW_PCLK

+#define STM32_USART3SW                      STM32_USART3SW_PCLK

+#define STM32_UART4SW                       STM32_UART4SW_PCLK

+#define STM32_UART5SW                       STM32_UART5SW_PCLK

+#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK

+#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK

+#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2

+#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2

+#define STM32_RTCSEL                        STM32_RTCSEL_LSI

+#define STM32_USB_CLOCK_REQUIRED            TRUE

+#define STM32_USBPRE                        STM32_USBPRE_DIV1P5

+

+/*

+ * ADC driver system settings.

+ */

+#define STM32_ADC_DUAL_MODE                 FALSE

+#define STM32_ADC_COMPACT_SAMPLES           FALSE

+#define STM32_ADC_USE_ADC1                  FALSE

+#define STM32_ADC_USE_ADC2                  FALSE

+#define STM32_ADC_USE_ADC3                  FALSE

+#define STM32_ADC_USE_ADC4                  FALSE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)

+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_ADC4_DMA_PRIORITY         2

+#define STM32_ADC_ADC12_IRQ_PRIORITY        5

+#define STM32_ADC_ADC3_IRQ_PRIORITY         5

+#define STM32_ADC_ADC4_IRQ_PRIORITY         5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

+#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1

+

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_CAN1                  TRUE

+#define STM32_CAN_CAN1_IRQ_PRIORITY         11

+

+/*

+ * DAC driver system settings.

+ */

+#define STM32_DAC_DUAL_MODE                 FALSE

+#define STM32_DAC_USE_DAC1_CH1              TRUE

+#define STM32_DAC_USE_DAC1_CH2              TRUE

+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

+

+/*

+ * EXT driver system settings.

+ */

+#define STM32_EXT_EXTI0_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI1_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI2_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI3_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI4_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6

+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6

+#define STM32_EXT_EXTI16_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI17_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI18_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI19_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI20_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6

+#define STM32_EXT_EXTI30_32_IRQ_PRIORITY    6

+#define STM32_EXT_EXTI33_IRQ_PRIORITY       6

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  FALSE

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_USE_TIM3                  FALSE

+#define STM32_GPT_USE_TIM4                  FALSE

+#define STM32_GPT_USE_TIM6                  FALSE

+#define STM32_GPT_USE_TIM7                  FALSE

+#define STM32_GPT_USE_TIM8                  FALSE

+#define STM32_GPT_TIM1_IRQ_PRIORITY         7

+#define STM32_GPT_TIM2_IRQ_PRIORITY         7

+#define STM32_GPT_TIM3_IRQ_PRIORITY         7

+#define STM32_GPT_TIM4_IRQ_PRIORITY         7

+#define STM32_GPT_TIM6_IRQ_PRIORITY         7

+#define STM32_GPT_TIM7_IRQ_PRIORITY         7

+#define STM32_GPT_TIM8_IRQ_PRIORITY         7

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  TRUE

+#define STM32_I2C_USE_I2C2                  FALSE

+#define STM32_I2C_BUSY_TIMEOUT              50

+#define STM32_I2C_I2C1_IRQ_PRIORITY         10

+#define STM32_I2C_I2C2_IRQ_PRIORITY         10

+#define STM32_I2C_USE_DMA                   TRUE

+#define STM32_I2C_I2C1_DMA_PRIORITY         1

+#define STM32_I2C_I2C2_DMA_PRIORITY         1

+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  FALSE

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_USE_TIM3                  FALSE

+#define STM32_ICU_USE_TIM4                  FALSE

+#define STM32_ICU_USE_TIM8                  FALSE

+#define STM32_ICU_TIM1_IRQ_PRIORITY         7

+#define STM32_ICU_TIM2_IRQ_PRIORITY         7

+#define STM32_ICU_TIM3_IRQ_PRIORITY         7

+#define STM32_ICU_TIM4_IRQ_PRIORITY         7

+#define STM32_ICU_TIM8_IRQ_PRIORITY         7

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              FALSE

+#define STM32_PWM_USE_TIM1                  FALSE

+#define STM32_PWM_USE_TIM2                  FALSE

+#define STM32_PWM_USE_TIM3                  FALSE

+#define STM32_PWM_USE_TIM4                  FALSE

+#define STM32_PWM_USE_TIM8                  FALSE

+#define STM32_PWM_TIM1_IRQ_PRIORITY         7

+#define STM32_PWM_TIM2_IRQ_PRIORITY         7

+#define STM32_PWM_TIM3_IRQ_PRIORITY         7

+#define STM32_PWM_TIM4_IRQ_PRIORITY         7

+#define STM32_PWM_TIM8_IRQ_PRIORITY         7

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART1             FALSE

+#define STM32_SERIAL_USE_USART2             FALSE

+#define STM32_SERIAL_USE_USART3             FALSE

+#define STM32_SERIAL_USE_UART4              FALSE

+#define STM32_SERIAL_USE_UART5              FALSE

+#define STM32_SERIAL_USART1_PRIORITY        12

+#define STM32_SERIAL_USART2_PRIORITY        12

+#define STM32_SERIAL_USART3_PRIORITY        12

+#define STM32_SERIAL_UART4_PRIORITY         12

+#define STM32_SERIAL_UART5_PRIORITY         12

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  TRUE

+#define STM32_SPI_USE_SPI2                  FALSE

+#define STM32_SPI_USE_SPI3                  FALSE

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI3_DMA_PRIORITY         1

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

+

+/*

+ * ST driver system settings.

+ */

+#define STM32_ST_IRQ_PRIORITY               8

+#define STM32_ST_USE_TIMER                  2

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USART1_IRQ_PRIORITY      12

+#define STM32_UART_USART2_IRQ_PRIORITY      12

+#define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

+

+/*

+ * USB driver system settings.

+ */

+#define STM32_USB_USE_USB1                  FALSE

+#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE

+#define STM32_USB_USB1_HP_IRQ_PRIORITY      13

+#define STM32_USB_USB1_LP_IRQ_PRIORITY      14

+

+/*

+ * WDG driver system settings.

+ */

+#define STM32_WDG_USE_IWDG                  TRUE

+

+/*

+ * header for community drivers.

+ */

+#include "mcuconf_community.h"

+

+#endif /* _MCUCONF_H_ */

diff --git a/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h
new file mode 100644
index 0000000..4a13b56
--- /dev/null
+++ b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h
@@ -0,0 +1,45 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * FSMC driver system settings.
+ */
+#define STM32_FSMC_USE_FSMC1                FALSE
+#define STM32_FSMC_FSMC1_IRQ_PRIORITY       10
+
+/*
+ * FSMC NAND driver system settings.
+ */
+#define STM32_NAND_USE_FSMC_NAND1           FALSE
+#define STM32_NAND_USE_FSMC_NAND2           FALSE
+#define STM32_NAND_USE_EXT_INT              FALSE
+#define STM32_NAND_DMA_STREAM               STM32_DMA_STREAM_ID(2, 7)
+#define STM32_NAND_DMA_PRIORITY             0
+#define STM32_NAND_DMA_ERROR_HOOK(nandp)    osalSysHalt("DMA failure")
+
+/*
+ * FSMC SRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SRAM                 FALSE
+#define STM32_SRAM_USE_FSMC_SRAM1           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM2           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM3           FLASE
+#define STM32_SRAM_USE_FSMC_SRAM4           FALSE
+
+/*
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM                FALSE