Merge branch 'tm4c129x_ethernet'

19 files changed, 5175 insertions, 87 deletions

diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject
new file mode 100644
index 0000000..efeab1b
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.114656749">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.114656749." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/>
+							<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.890534880" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/>
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/>
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.262251028" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/>
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/>
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.757265410" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/>
+									<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/>
+								</option>
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ARMCM4-STM32F407-DISCOVERY.null.1703860681" name="ARMCM4-STM32F407-DISCOVERY"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.114656749">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
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+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.project b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.project
new file mode 100644
index 0000000..a380601
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.project
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>RT-TM4C1294-LAUNCHPAD-LWIP</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>board</name>
+			<type>2</type>
+			<locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
+		</link>
+		<link>
+			<name>community_os</name>
+			<type>2</type>
+			<locationURI>CHIBIOS3/community</locationURI>
+		</link>
+		<link>
+			<name>os</name>
+			<type>2</type>
+			<locationURI>CHIBIOS3/os</locationURI>
+		</link>
+		<link>
+			<name>test</name>
+			<type>2</type>
+			<locationURI>CHIBIOS3/test</locationURI>
+		</link>
+	</linkedResources>
+	<variableList>
+		<variable>
+			<name>CHIBIOS3</name>
+			<value>file:/C:/ChibiStudio/chibios3</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile
new file mode 100644
index 0000000..2841644
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile
@@ -0,0 +1,202 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -lm
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+  USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+  USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+  USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+  USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4.
+ifeq ($(USE_FPU),)
+  USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
+include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk
+include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/TM4C129xNC.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(OSALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(LWSRC) \
+       $(CHIBIOS)/os/various/evtimer.c \
+       main.c \
+       web/web.c \
+       $(CHIBIOS)/os/various/chprintf.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \
+         $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU  = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+SZ   = $(TRGT)size
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS = -DLWIP_DEBUG=0
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/chconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/chconf.h
new file mode 100644
index 0000000..ad50207
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/chconf.h
@@ -0,0 +1,468 @@
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System time counter resolution.
+ * @note    Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION                32
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY                 10000
+
+/**
+ * @brief   Time delta constant for the tick-less mode.
+ * @note    If this value is zero then the system uses the classic
+ *          periodic tick. This value represents the minimum number
+ *          of ticks that is safe to specify in a timeout directive.
+ *          The value one is not valid, timeouts are rounded up to
+ *          this value.
+ */
+#define CH_CFG_ST_TIMEDELTA                 0
+
+/**
+ * @brief   Realtime Counter frequency.
+ * @details Frequency of the system counter used for realtime delays and
+ *          measurements.
+ */
+#define CH_CFG_RTC_FREQUENCY                80000000
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ * @note    The round robin preemption is not supported in tickless mode and
+ *          must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM                 0
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE                 0
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread. The application @p main()
+ *          function becomes the idle thread and must implement an
+ *          infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD               FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED               TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM                       TRUE
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY                 TRUE
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT                 TRUE
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES               TRUE
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES                  TRUE
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS                 TRUE
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS                   TRUE
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES                 TRUE
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special
+ *          requirements.
+ * @note    Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES                TRUE
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES                   TRUE
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE                  TRUE
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ *          @p CH_CFG_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP                     TRUE
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS                 TRUE
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_CFG_USE_WAITEXIT.
+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC                  TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, kernel statistics.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS                   TRUE
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS                TRUE
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS               TRUE
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE                 TRUE
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK           TRUE
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS                 TRUE
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p FALSE.
+ * @note    This debug option is not currently compatible with the
+ *          tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING            TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \
+  /* Add threads custom fields here.*/
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
+  /* Add threads initialization code here.*/                                \
+}
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
+  /* Add threads finalization code here.*/                                  \
+}
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+
+/**
+ * @brief   Idle thread enter hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle thread leave hook.
+ * @note    This hook is invoked within a critical zone, no OS functions
+ *          should be invoked from here.
+ * @note    This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() {                                         \
+}
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \
+  /* Idle loop code here.*/                                                 \
+}
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \
+  /* System tick event code here.*/                                         \
+}
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \
+  /* System halt code here.*/                                               \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch
new file mode 100644
index 0000000..c9016ed
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
+<stringAttribute key="bad_container_name" value="\TM4C129x-ETH\debu"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt&#13;&#10;monitor reset init&#13;&#10;cortex_m maskisr auto"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;dmaris-VectorE0-(format)&quot; val=&quot;2&quot;/&gt;&lt;/contentList&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-TM4C1294-LAUNCHPAD-LWIP"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/RT-TM4C1294-LAUNCHPAD-LWIP"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/halconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/halconf.h
new file mode 100644
index 0000000..72b887e
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/halconf.h
@@ -0,0 +1,278 @@
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 TRUE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              TRUE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         64
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/lwipopts.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/lwipopts.h
new file mode 100644
index 0000000..c4829fa
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/lwipopts.h
@@ -0,0 +1,2127 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIPOPT_H__
+#define __LWIPOPT_H__
+
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+/** 
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+
+/**
+ * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
+ * Mainly for compatibility to old versions.
+ */
+#ifndef NO_SYS_NO_TIMERS
+#define NO_SYS_NO_TIMERS                0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC                 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   4
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array.
+ * This can be used to individually change the location of each pool.
+ * Default is one big array for all pools
+ */
+#ifndef MEMP_SEPARATE_POOLS
+#define MEMP_SEPARATE_POOLS             0
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
+#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your 
+ * inlude path somewhere. 
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with IP_FRAG_USES_STATIC_BUF==0 and
+ * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs
+ * where the packet is not yet sent when netif->output returns.
+ */
+#ifndef MEMP_NUM_FRAG_PBUF
+#define MEMP_NUM_FRAG_PBUF              15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members et the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ * The default number of timeouts is calculated here for all enabled modules.
+ * The formula expects settings to be either '0' or '1'.
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree.
+ */
+#ifndef MEMP_NUM_SNMP_NODE
+#define MEMP_NUM_SNMP_NODE              50
+#endif
+
+/**
+ * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree.
+ * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least!
+ */
+#ifndef MEMP_NUM_SNMP_ROOTNODE
+#define MEMP_NUM_SNMP_ROOTNODE          30
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to
+ * be changed normally) - 2 of these are used per request (1 for input,
+ * 1 for output)
+ */
+#ifndef MEMP_NUM_SNMP_VARBIND
+#define MEMP_NUM_SNMP_VARBIND           2
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used
+ * (does not have to be changed normally) - 3 of these are used per request
+ * (1 for the value read and 2 for OIDs - input and output)
+ */
+#ifndef MEMP_NUM_SNMP_VALUE
+#define MEMP_NUM_SNMP_VALUE             3
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#ifndef MEMP_NUM_NETDB
+#define MEMP_NUM_NETDB                  1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#ifndef MEMP_NUM_LOCALHOSTLIST
+#define MEMP_NUM_LOCALHOSTLIST          1
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES       1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. 
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    0
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ * The peer *is* in the ARP table if it requested our address before.
+ * Also notice that this slows down input processing of every IP packet!
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC             0
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
+ * that returns 1 to accept a packet or 0 to drop a packet.
+ */
+#ifndef ETHARP_SUPPORT_VLAN
+#define ETHARP_SUPPORT_VLAN             0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP
+ * might be disabled
+ */
+#ifndef LWIP_ETHERNET
+#define LWIP_ETHERNET                   (LWIP_ARP || PPPOE_SUPPORT)
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE                    0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#ifndef ETHARP_SUPPORT_STATIC_ENTRIES
+#define ETHARP_SUPPORT_STATIC_ENTRIES   0
+#endif
+
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE                 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1,
+ * new PBUF_RAM pbufs are used for fragments).
+ * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs!
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF         0
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU                 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#ifndef IP_SOF_BROADCAST
+#define IP_SOF_BROADCAST                0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#ifndef IP_SOF_BROADCAST_RECV
+#define IP_SOF_BROADCAST_RECV           0
+#endif
+
+/**
+ * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back
+ * out on the netif where it was received. This should only be used for
+ * wireless networks.
+ * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming
+ * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags!
+ */
+#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF
+#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0
+#endif
+
+/**
+ * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first
+ * local TCP/UDP pcb (default==0). This can prevent creating predictable port
+ * numbers after booting a device.
+ */
+#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS
+#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0
+#endif
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL                       (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#ifndef LWIP_BROADCAST_PING
+#define LWIP_BROADCAST_PING             0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#ifndef LWIP_MULTICAST_PING
+#define LWIP_MULTICAST_PING             0
+#endif
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP. This can be set
+ * as low as 1 to get an AutoIP address very quickly, but you should
+ * be prepared to handle a changing IP address when DHCP overrides
+ * AutoIP.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
+#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
+#endif
+
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
+ * transport.
+ */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/**
+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
+ * allow. At least one request buffer is required.
+ * Does not have to be changed unless external MIBs answer request asynchronously
+ */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+/**
+ * SNMP_PRIVATE_MIB: 
+ * When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB.
+ */
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#ifndef SNMP_SAFE_REQUESTS
+#define SNMP_SAFE_REQUESTS              1
+#endif
+
+/**
+ * The maximum length of strings used. This affects the size of
+ * MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_OCTET_STRING_LEN
+#define SNMP_MAX_OCTET_STRING_LEN       127
+#endif
+
+/**
+ * The maximum depth of the SNMP tree.
+ * With private MIBs enabled, this depends on your MIB!
+ * This affects the size of MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_TREE_DEPTH
+#define SNMP_MAX_TREE_DEPTH             15
+#endif
+
+/**
+ * The size of the MEMP_SNMP_VALUE elements, normally calculated from
+ * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH.
+ */
+#ifndef SNMP_MAX_VALUE_SIZE
+#define SNMP_MAX_VALUE_SIZE             LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH))
+#endif
+
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module. 
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** DNS message max. size. Default value is RFC compliant. */
+#ifndef DNS_MSG_SIZE
+#define DNS_MSG_SIZE                    512
+#endif
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
+ *  you have to define
+ *    #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
+ *  (an array of structs name/address, where address is an u32_t in network
+ *  byte order).
+ *
+ *  Instead, you can also use an external function:
+ *  #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
+ *  that returns the IP address or INADDR_NONE if not found.
+ */
+#ifndef DNS_LOCAL_HOSTLIST
+#define DNS_LOCAL_HOSTLIST              0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ *  at runtime. */
+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#ifndef LWIP_NETBUF_RECVINFO
+#define LWIP_NETBUF_RECVINFO            0
+#endif
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least 
+ * (2 * TCP_MSS) for things to work well
+ */
+#ifndef TCP_WND
+#define TCP_WND                         (4 * TCP_MSS)
+#endif 
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 (LWIP_TCP)
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS                         536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ * To achieve good performance, this should be at least 2 * TCP_MSS.
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#ifndef TCP_SNDQUEUELOWAT
+#define TCP_SNDQUEUELOWAT               LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5)
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb.
+ * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0.
+ */
+#ifndef TCP_OOSEQ_MAX_BYTES
+#define TCP_OOSEQ_MAX_BYTES             0
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb.
+ * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0.
+ */
+#ifndef TCP_OOSEQ_MAX_PBUFS
+#define TCP_OOSEQ_MAX_PBUFS             0
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0:         Disable oversized allocation. Each tcp_write() allocates a new
+              pbuf (old behaviour).
+ * 1:         Allocate size-aligned pbufs with minimal excess. Use this if your
+ *            scatter-gather DMA requires aligned fragments.
+ * 128:       Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS:   Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#ifndef TCP_OVERSIZE
+#define TCP_OVERSIZE                    TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ */
+#ifndef LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_TIMESTAMPS             0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#ifndef TCP_WND_UPDATE_THRESHOLD
+#define TCP_WND_UPDATE_THRESHOLD   (TCP_WND / 4)
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event. This is the default.
+ */
+#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API)
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#endif
+
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  (14 + ETH_PAD_SIZE)
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquistion)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called
+ * when a netif has been removed
+ */
+#ifndef LWIP_NETIF_REMOVE_CALLBACK
+#define LWIP_NETIF_REMOVE_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#ifndef LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK             0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#ifndef LWIP_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS         0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and netif_poll() must be called in
+ *       the main application loop.
+ */
+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
+#define LWIP_NETIF_TX_SINGLE_PBUF             0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
+ */
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME              "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE          1024
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               (LOWPRIO + 1)
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE                 MEMP_NUM_PBUF
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME             "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE         1024
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              (LOWPRIO + 1)
+#endif
+
+/**
+ * PPP_THREAD_NAME: The name assigned to the pppInputThread.
+ */
+#ifndef PPP_THREAD_NAME
+#define PPP_THREAD_NAME                "pppInputThread"
+#endif
+
+/**
+ * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_STACKSIZE
+#define PPP_THREAD_STACKSIZE            1024
+#endif
+
+/**
+ * PPP_THREAD_PRIO: The priority assigned to the pppInputThread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 (LOWPRIO + 1)
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME            "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE        1024
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             (LOWPRIO + 1)
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE       4
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE       4
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE       40
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE         4
+#endif
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING         0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT
+#define LWIP_TCPIP_CORE_LOCKING_INPUT   0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN                    1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create
+ * timers running in tcpip_thread from another thread.
+ */
+#ifndef LWIP_TCPIP_TIMEOUT
+#define LWIP_TCPIP_TIMEOUT              1
+#endif
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET                     1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#ifndef LWIP_SO_SNDTIMEO
+#define LWIP_SO_SNDTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#ifndef RECV_BUFSIZE_DEFAULT
+#define RECV_BUFSIZE_DEFAULT            INT_MAX
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#ifndef SO_REUSE
+#define SO_REUSE                        0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#ifndef SO_REUSE_RXTOALL
+#define SO_REUSE_RXTOALL                0
+#endif
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS                       (NO_SYS == 0)
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+
+#endif /* LWIP_STATS */
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * NUM_PPP: Max PPP sessions.
+ */
+#ifndef NUM_PPP
+#define NUM_PPP                         1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif
+
+/**
+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
+ */
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0
+#endif
+
+/*
+ * Timeouts
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#endif
+
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+#endif
+
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#endif
+
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+#endif
+
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#endif
+
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+#endif
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#ifndef PPP_MAXMTU
+/* #define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN) */
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      296             /* Try for this */
+#endif
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+#ifndef MAXNAMELEN
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#endif
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+#endif
+
+#endif /* PPP_SUPPORT */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets.
+ */
+#ifndef CHECKSUM_GEN_ICMP
+#define CHECKSUM_GEN_ICMP               1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#ifndef LWIP_CHECKSUM_ON_COPY
+#define LWIP_CHECKSUM_ON_COPY           0
+#endif
+
+/*
+   ---------------------------------------
+   ---------- Hook options ---------------
+   ---------------------------------------
+*/
+
+/* Hooks are undefined by default, define them to a function if you need them. */
+
+/**
+ * LWIP_HOOK_IP4_INPUT(pbuf, input_netif):
+ * - called from ip_input() (IPv4)
+ * - pbuf: received struct pbuf passed to ip_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+
+/**
+ * LWIP_HOOK_IP4_ROUTE(dest):
+ * - called from ip_route() (IPv4)
+ * - dest: destination IPv4 address
+ * Returns the destination netif or NULL if no destination netif is found. In
+ * that case, ip_route() continues as normal.
+ */
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_OFF
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#ifndef TIMERS_DEBUG
+#define TIMERS_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
+ */
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+#endif /* __LWIPOPT_H__ */
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/main.c b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/main.c
new file mode 100644
index 0000000..141579a
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/main.c
@@ -0,0 +1,60 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "lwipthread.h"
+#include "web/web.h"
+
+/*
+ * Application entry point.
+ */
+int main(void)
+{
+  /*
+   * System initializations.
+   * - HAL initialization, this also initializes the configured device drivers
+   *   and performs the board-specific initializations.
+   * - Kernel initialization, the main() function becomes a thread and the
+   *   RTOS is active.
+   */
+  halInit();
+  chSysInit();
+
+  /*
+   * Start the serial driver with the default configuration.
+   * Used for debug output of LwIP.
+   */
+  sdStart(&SD1, NULL);
+
+  /*
+   * Creates the LWIP threads (it changes priority internally).
+   */
+  chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 2,
+                    lwip_thread, NULL);
+
+  /*
+   * Creates the HTTP thread (it changes priority internally).
+   */
+  chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
+                    http_server, NULL);
+
+  while (1) {
+    osalThreadSleepMilliseconds(500);
+  }
+
+  return 0;
+}
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h
new file mode 100644
index 0000000..a3c6b3b
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h
@@ -0,0 +1,100 @@
+/*
+ * TM4C129x drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 7...0       Lowest...Highest.
+ */
+
+#define TM4C129x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define TIVA_MOSC_SINGLE_ENDED              FALSE
+#define TIVA_RSCLKCFG_OSCSRC                RSCLKCFG_OSCSRC_MOSC
+
+/*
+ * GPT driver system settings.
+ */
+#define TIVA_GPT_USE_GPT0                   FALSE
+#define TIVA_GPT_USE_GPT1                   FALSE
+#define TIVA_GPT_USE_GPT2                   FALSE
+#define TIVA_GPT_USE_GPT3                   FALSE
+#define TIVA_GPT_USE_GPT4                   FALSE
+#define TIVA_GPT_USE_GPT5                   FALSE
+#define TIVA_GPT_USE_GPT6                   FALSE
+#define TIVA_GPT_USE_GPT7                   FALSE
+#define TIVA_GPT_GPT0A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT1A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT2A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT3A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT4A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT5A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT6A_IRQ_PRIORITY         7
+#define TIVA_GPT_GPT7A_IRQ_PRIORITY         7
+
+/*
+ * I2C driver system settings.
+ */
+#define TIVA_I2C_USE_I2C0                   FALSE
+#define TIVA_I2C_USE_I2C1                   FALSE
+#define TIVA_I2C_USE_I2C2                   FALSE
+#define TIVA_I2C_USE_I2C3                   FALSE
+#define TIVA_I2C_USE_I2C4                   FALSE
+#define TIVA_I2C_USE_I2C5                   FALSE
+#define TIVA_I2C_USE_I2C6                   FALSE
+#define TIVA_I2C_USE_I2C7                   FALSE
+#define TIVA_I2C_USE_I2C8                   FALSE
+#define TIVA_I2C_USE_I2C9                   FALSE
+#define TIVA_I2C_I2C0_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C1_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C2_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C3_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C4_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C5_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C6_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C7_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C8_IRQ_PRIORITY          4
+#define TIVA_I2C_I2C9_IRQ_PRIORITY          4
+
+/*
+ * PWM driver system settings.
+ */
+#define TIVA_PWM_USE_PWM0                   FALSE
+#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY    4
+#define TIVA_PWM_PWM0_0_IRQ_PRIORITY        4
+#define TIVA_PWM_PWM0_1_IRQ_PRIORITY        4
+#define TIVA_PWM_PWM0_2_IRQ_PRIORITY        4
+#define TIVA_PWM_PWM0_3_IRQ_PRIORITY        4
+
+/*
+ * SERIAL driver system settings.
+ */
+#define TIVA_SERIAL_USE_UART0               TRUE
+#define TIVA_SERIAL_USE_UART1               FALSE
+#define TIVA_SERIAL_USE_UART2               FALSE
+#define TIVA_SERIAL_USE_UART3               FALSE
+#define TIVA_SERIAL_USE_UART4               FALSE
+#define TIVA_SERIAL_USE_UART5               FALSE
+#define TIVA_SERIAL_USE_UART6               FALSE
+#define TIVA_SERIAL_USE_UART7               FALSE
+#define TIVA_SERIAL_UART0_PRIORITY          5
+#define TIVA_SERIAL_UART1_PRIORITY          5
+#define TIVA_SERIAL_UART2_PRIORITY          5
+#define TIVA_SERIAL_UART3_PRIORITY          5
+#define TIVA_SERIAL_UART4_PRIORITY          5
+#define TIVA_SERIAL_UART5_PRIORITY          5
+#define TIVA_SERIAL_UART6_PRIORITY          5
+#define TIVA_SERIAL_UART7_PRIORITY          5
+
+/*
+ * ST driver system settings.
+ */
+#define TIVA_ST_IRQ_PRIORITY                2
+#define TIVA_ST_USE_WIDE_TIMER              TRUE
+#define TIVA_ST_TIMER_NUMBER                5
+#define TIVA_ST_TIMER_LETTER                A
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.c b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.c
new file mode 100644
index 0000000..dfc9d0d
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.c
@@ -0,0 +1,121 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * This file is a modified version of the lwIP web server demo. The original
+ * author is unknown because the file didn't contain any license information.
+ */
+
+/**
+ * @file web.c
+ * @brief HTTP server wrapper thread code.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#include "ch.h"
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api.h"
+
+#include "web.h"
+
+#if LWIP_NETCONN
+
+static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
+static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
+
+static void http_server_serve(struct netconn *conn) {
+  struct netbuf *inbuf;
+  char *buf;
+  u16_t buflen;
+  err_t err;
+
+  /* Read the data from the port, blocking if nothing yet there.
+   We assume the request (the part we care about) is in one netbuf */
+  err = netconn_recv(conn, &inbuf);
+
+  if (err == ERR_OK) {
+    netbuf_data(inbuf, (void **)&buf, &buflen);
+
+    /* Is this an HTTP GET command? (only check the first 5 chars, since
+    there are other formats for GET, and we're keeping it very simple )*/
+    if (buflen>=5 &&
+        buf[0]=='G' &&
+        buf[1]=='E' &&
+        buf[2]=='T' &&
+        buf[3]==' ' &&
+        buf[4]=='/' ) {
+
+      /* Send the HTML header
+             * subtract 1 from the size, since we dont send the \0 in the string
+             * NETCONN_NOCOPY: our data is const static, so no need to copy it
+       */
+      netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
+
+      /* Send our HTML page */
+      netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
+    }
+  }
+  /* Close the connection (server closes in HTTP) */
+  netconn_close(conn);
+
+  /* Delete the buffer (netconn_recv gives us ownership,
+   so we have to make sure to deallocate the buffer) */
+  netbuf_delete(inbuf);
+}
+
+/**
+ * Stack area for the http thread.
+ */
+THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+/**
+ * HTTP server thread.
+ */
+msg_t http_server(void *p) {
+  struct netconn *conn, *newconn;
+  err_t err;
+
+  (void)p;
+
+  /* Create a new TCP connection handle */
+  conn = netconn_new(NETCONN_TCP);
+  LWIP_ERROR("http_server: invalid conn", (conn != NULL), return MSG_RESET;);
+
+  /* Bind to port 80 (HTTP) with default IP address */
+  netconn_bind(conn, NULL, WEB_THREAD_PORT);
+
+  /* Put the connection into LISTEN state */
+  netconn_listen(conn);
+
+  /* Goes to the final priority after initialization.*/
+  chThdSetPriority(WEB_THREAD_PRIORITY);
+
+  while(1) {
+    err = netconn_accept(conn, &newconn);
+    if (err != ERR_OK)
+      continue;
+    http_server_serve(newconn);
+    netconn_delete(newconn);
+  }
+  return MSG_OK;
+}
+
+#endif /* LWIP_NETCONN */
+
+/** @} */
diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.h
new file mode 100644
index 0000000..2764242
--- /dev/null
+++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.h
@@ -0,0 +1,51 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file web.h
+ * @brief HTTP server wrapper thread macros and structures.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#ifndef _WEB_H_
+#define _WEB_H_
+
+#ifndef WEB_THREAD_STACK_SIZE
+#define WEB_THREAD_STACK_SIZE   1024
+#endif
+
+#ifndef WEB_THREAD_PORT
+#define WEB_THREAD_PORT         80
+#endif
+
+#ifndef WEB_THREAD_PRIORITY
+#define WEB_THREAD_PRIORITY     (LOWPRIO + 2)
+#endif
+
+extern THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  msg_t http_server(void *p);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WEB_H_ */
+
+/** @} */
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
index 37590d2..0ef06ef 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
@@ -28,6 +28,14 @@
 #define BOARD_NAME              "Texas Instruments TM4C1294 Launchpad"
 
 /*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ADDR                  0   /* 0 is internal PHY */
+#define BOARD_PHY_ID                    0x2000A221  /* internal PHY ID */
+/* uncomment when using RMII */
+//#define BOARD_PHY_RMII
+
+/*
  * MCU type
  */
 //#define TM4C1290NCPDT
@@ -269,18 +277,18 @@
 #define VAL_GPIOE_PCTL          0x00000000
 
 #define VAL_GPIOF_DATA          0b00000000
-#define VAL_GPIOF_DIR           0b00010001
-#define VAL_GPIOF_AFSEL         0b00000000
+#define VAL_GPIOF_DIR           0b00010011
+#define VAL_GPIOF_AFSEL         0b00010011
 #define VAL_GPIOF_DR2R          0b11111111
 #define VAL_GPIOF_DR4R          0b00000000
 #define VAL_GPIOF_DR8R          0b00000000
 #define VAL_GPIOF_ODR           0b00000000
-#define VAL_GPIOF_PUR           0b00010001
+#define VAL_GPIOF_PUR           0b00000000
 #define VAL_GPIOF_PDR           0b00000000
 #define VAL_GPIOF_SLR           0b00000000
 #define VAL_GPIOF_DEN           0b11111111
 #define VAL_GPIOF_AMSEL         0b0000
-#define VAL_GPIOF_PCTL          0x00000000
+#define VAL_GPIOF_PCTL          0x00050055
 
 #define VAL_GPIOG_DATA          0b00000000
 #define VAL_GPIOG_DIR           0b00000000
diff --git a/os/hal/ports/TIVA/LLD/mac_lld.c b/os/hal/ports/TIVA/LLD/mac_lld.c
new file mode 100644
index 0000000..226695e
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/mac_lld.c
@@ -0,0 +1,823 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/mac_lld.c
+ * @brief   MAC Driver subsystem low level driver source.
+ *
+ * @addtogroup MAC
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_MAC || defined(__DOXYGEN__)
+
+#include "mii.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
+
+/* MII divider optimal value.*/
+#if (TIVA_SYSCLK >= 100000000)
+#define MACMIIADDR_CR   (0x01 << 2)
+#elif (TIVA_SYSCLK >= 60000000)
+#define MACMIIADDR_CR   (0x00 << 2)
+#elif (TIVA_SYSCLK >= 35000000)
+#define MACMIIADDR_CR   (0x03 << 2)
+#elif (TIVA_SYSCLK >= 20000000)
+#define MACMIIADDR_CR   (0x02 << 2)
+#else
+#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)"
+#endif
+
+#define EMAC_MIIADDR_MIIW       0x00000002  /* MII Write */
+#define EMAC_MIIADDR_MIIB       0x00000001  /* MII Busy */
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief Ethernet driver 1.
+ */
+MACDriver ETHD1;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
+                                              0x37, 0x01, 0x10};
+
+static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS];
+static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS];
+
+static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
+static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Writes a PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ * @param[in] value     new register value
+ *
+ * @notapi
+ */
+static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
+{
+  ETH->MIIDATA = value;
+  ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
+
+  while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+    ;
+}
+
+/**
+ * @brief   Writes an extended PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ * @param[in] value     new register value
+ *
+ * @notapi
+ */
+static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
+{
+  mii_write(macp, TIVA_REGCTL, 0x001F);
+  mii_write(macp, TIVA_ADDAR, reg);
+
+  mii_write(macp, TIVA_REGCTL, 0x401F);
+  mii_write(macp, TIVA_ADDAR, value);
+}
+
+/**
+ * @brief   Reads a PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ *
+ * @return              The PHY register content.
+ *
+ * @notapi
+ */
+static uint32_t mii_read(MACDriver *macp, uint32_t reg)
+{
+  ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
+
+  while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
+    ;
+
+  return ETH->MIIDATA;
+}
+
+/**
+ * @brief   Reads an extended PHY register.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[in] reg       register number
+ *
+ * @return              The extended PHY register content.
+ *
+ * @notapi
+ */
+static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg)
+{
+  mii_write(macp, TIVA_REGCTL, 0x001F);
+  mii_write(macp, TIVA_ADDAR, reg);
+
+  mii_write(macp, TIVA_REGCTL, 0x401F);
+  return mii_read(macp, TIVA_ADDAR);
+}
+
+#if !defined(BOARD_PHY_ADDRESS)
+/**
+ * @brief   PHY address detection.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ */
+static void mii_find_phy(MACDriver *macp)
+{
+  uint32_t i;
+
+#if TIVA_MAC_PHY_TIMEOUT > 0
+  rtcnt_t start = chSysGetRealtimeCounterX();
+  rtcnt_t timeout  = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT);
+  rtcnt_t time = start;
+  while (chSysIsCounterWithinX(time, start, timeout)) {
+#endif
+    for (i = 0; i < 31; i++) {
+      macp->phyaddr = i << 11;
+      ETH->MIIDATA = (i << 6) | MACMIIADDR_CR;
+      if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
+          ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
+        return;
+      }
+    }
+#if TIVA_MAC_PHY_TIMEOUT > 0
+    time = chSysGetRealtimeCounterX();
+  }
+#endif
+  /* Wrong or defective board.*/
+  osalSysHalt("MAC failure");
+}
+#endif
+
+/**
+ * @brief   MAC address setup.
+ *
+ * @param[in] p         pointer to a six bytes buffer containing the MAC
+ *                      address
+ */
+static void mac_lld_set_address(const uint8_t *p)
+{
+  /* MAC address configuration, only a single address comparator is used,
+     hash table not used.*/
+  ETH->ADDR0H   = ((uint32_t)p[5] << 8) |
+                  ((uint32_t)p[4] << 0);
+  ETH->ADDR0L   = ((uint32_t)p[3] << 24) |
+                  ((uint32_t)p[2] << 16) |
+                  ((uint32_t)p[1] << 8) |
+                  ((uint32_t)p[0] << 0);
+  ETH->ADDR1H   = 0x0000FFFF;
+  ETH->ADDR1L   = 0xFFFFFFFF;
+  ETH->ADDR2H   = 0x0000FFFF;
+  ETH->ADDR2L   = 0xFFFFFFFF;
+  ETH->ADDR3H   = 0x0000FFFF;
+  ETH->ADDR3L   = 0xFFFFFFFF;
+  ETH->HASHTBLH = 0;
+  ETH->HASHTBLL = 0;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
+{
+  uint32_t dmaris;
+
+  CH_IRQ_PROLOGUE();
+
+  dmaris = ETH->DMARIS;
+  ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/
+
+  if (dmaris & (1 << 6)) {
+    /* Data Received.*/
+    osalSysLockFromISR();
+    osalThreadDequeueAllI(&ETHD1.rdqueue, MSG_RESET);
+#if MAC_USE_EVENTS
+    osalEventBroadcastFlagsI(&ETHD1.rdevent, 0);
+#endif
+    osalSysUnlockFromISR();
+  }
+
+  if (dmaris & (1 << 0)) {
+    /* Data Transmitted.*/
+    osalSysLockFromISR();
+    osalThreadDequeueAllI(&ETHD1.tdqueue, MSG_RESET);
+    osalSysUnlockFromISR();
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level MAC initialization.
+ *
+ * @notapi
+ */
+void mac_lld_init(void)
+{
+  uint8_t i;
+
+  macObjectInit(&ETHD1);
+  ETHD1.link_up = false;
+
+  /* Descriptor tables are initialized in chained mode, note that the first
+     word is not initialized here but in mac_lld_start().*/
+  for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
+    rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE);
+    rd[i].rdes2 = (uint32_t)rb[i];
+    rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS];
+  }
+  for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
+    td[i].tdes1 = 0;
+    td[i].tdes2 = (uint32_t)tb[i];
+    td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS];
+  }
+
+  /* Enable MAC clock */
+  SYSCTL->RCGCEMAC = 1;
+  while (SYSCTL->PREMAC != 0x01)
+    ;
+
+  /* Set PHYHOLD bit */
+  ETH->PC |= 1;
+
+  /* Enable PHY clock */
+  SYSCTL->RCGCEPHY = 1;
+  while (SYSCTL->PREPHY != 0x01)
+    ;
+
+  /* Enable power to PHY */
+  SYSCTL->PCEPHY |= 1;
+  while (SYSCTL->PREPHY != 0x01)
+    ;
+#if BOARD_PHY_RMII
+  ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28);
+#else
+  ETH->PC = EMAC_PHY_CONFIG;
+#endif
+
+  /*
+   * Write OHY led configuration.
+   * 0: link ok
+   * 1: tx activity
+   * 2: link ok
+   * blink rate: 20Hz
+   */
+  mii_write_extended(&ETHD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0));
+  mii_write(&ETHD1, TIVA_LEDCR, (0 << 9));
+
+  /* Set done bit after writing EMACPC register */
+  mii_write(&ETHD1, TIVA_CFG1, (1 << 15) | mii_read(&ETHD1, TIVA_CFG1));
+
+  while(ETH->DMABUSMOD & 1)
+    ;
+
+  /* Reset MAC */
+  ETH->DMABUSMOD |= 1;
+  while (ETH->DMABUSMOD & 1)
+    ;
+
+  /* PHY address setup.*/
+#if defined(BOARD_PHY_ADDRESS)
+  ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
+#else
+  mii_find_phy(&ETHD1);
+#endif
+
+#if defined(BOARD_PHY_RESET)
+  /* PHY board-specific reset procedure.*/
+  BOARD_PHY_RESET();
+#else
+  /* PHY soft reset procedure.*/
+  mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
+#if defined(BOARD_PHY_RESET_DELAY)
+  chSysPolledDelayX(BOARD_PHY_RESET_DELAY);
+#endif
+  while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
+    ;
+#endif
+
+#if TIVA_MAC_CHANGE_PHY_STATE
+  /* PHY in power down mode until the driver will be started.*/
+  mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
+#endif
+
+  /* Disable MAC clock */
+  SYSCTL->RCGCEMAC = 0;
+
+  /* Disable PHY clock */
+  SYSCTL->RCGCEPHY = 0;
+}
+
+/**
+ * @brief   Configures and activates the MAC peripheral.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ *
+ * @notapi
+ */
+void mac_lld_start(MACDriver *macp)
+{
+  uint8_t i;
+
+  /* Resets the state of all descriptors.*/
+  for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
+    rd[i].rdes0 = TIVA_RDES0_OWN;
+  }
+  macp->rxptr = (tiva_eth_rx_descriptor_t *)rd;
+
+  for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
+    td[i].tdes0 = TIVA_TDES0_TCH;
+    td[i].locked = 0;
+  }
+  macp->txptr = (tiva_eth_tx_descriptor_t *)td;
+
+  /* Enable MAC clock */
+  SYSCTL->RCGCEMAC = 1;
+  while (SYSCTL->PREMAC != 0x01)
+    ;
+
+  /* Enable PHY clock */
+  SYSCTL->RCGCEPHY = 1;
+  while (!SYSCTL->PREPHY)
+    ;
+
+  /* ISR vector enabled.*/
+  nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY);
+
+#if TIVA_MAC_CHANGE_PHY_STATE
+  /* PHY in power up mode.*/
+  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
+#endif
+
+  /* MAC configuration.*/
+  ETH->FRAMEFLTR = 0;
+  ETH->FLOWCTL = 0;
+  ETH->VLANTG = 0;
+
+  /* MAC address setup.*/
+  if (macp->config->mac_address == NULL)
+    mac_lld_set_address(default_mac_address);
+  else
+    mac_lld_set_address(macp->config->mac_address);
+
+  /* Transmitter and receiver enabled.
+     Note that the complete setup of the MAC is performed when the link
+     status is detected.*/
+#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
+  ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2);
+#else
+  ETH->CFG =             (1 << 3) | (1 << 2);
+#endif
+
+  /* DMA configuration:
+     Descriptor chains pointers.*/
+  ETH->RXDLADDR = (uint32_t)rd;
+  ETH->TXDLADDR = (uint32_t)td;
+
+  /* Enabling required interrupt sources.*/
+  ETH->DMARIS &= 0xFFFF;
+  ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0);
+
+  /* DMA general settings.*/
+  ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8);
+
+  /* Transmit FIFO flush.*/
+  ETH->DMAOPMODE = (1 << 20);
+  while (ETH->DMAOPMODE & (1 << 20))
+    ;
+
+  /* DMA final configuration and start.*/
+  ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) |
+                        (1 << 13) | (1 << 1);
+}
+
+/**
+ * @brief   Deactivates the MAC peripheral.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ *
+ * @notapi
+ */
+void mac_lld_stop(MACDriver *macp)
+{
+  if (macp->state != MAC_STOP) {
+#if TIVA_MAC_CHANGE_PHY_STATE
+    /* PHY in power down mode until the driver will be restarted.*/
+    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
+#endif
+
+    /* MAC and DMA stopped.*/
+    ETH->CFG = 0;
+    ETH->DMAOPMODE = 0;
+    ETH->DMAIM = 0;
+    ETH->DMARIS &= 0xFFFF;
+
+    /* MAC clocks stopped.*/
+    SYSCTL->RCGCEMAC = 0;
+
+    /* PHY clock stopped.*/
+    SYSCTL->RCGCEPHY = 0;
+
+    /* ISR vector disabled.*/
+    nvicDisableVector(TIVA_MAC_NUMBER);
+  }
+}
+
+/**
+ * @brief   Returns a transmission descriptor.
+ * @details One of the available transmission descriptors is locked and
+ *          returned.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[out] tdp      pointer to a @p MACTransmitDescriptor structure
+ * @return              The operation status.
+ * @retval RDY_OK       the descriptor has been obtained.
+ * @retval RDY_TIMEOUT  descriptor not available.
+ *
+ * @notapi
+ */
+msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
+                                      MACTransmitDescriptor *tdp)
+{
+  tiva_eth_tx_descriptor_t *tdes;
+
+  if (!macp->link_up)
+    return MSG_TIMEOUT;
+
+  osalSysLock();
+
+  /* Get Current TX descriptor.*/
+  tdes = macp->txptr;
+
+  /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
+     another thread.*/
+  if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) {
+    osalSysUnlock();
+    return MSG_TIMEOUT;
+  }
+
+  /* Marks the current descriptor as locked.*/
+  tdes->locked = 1;
+
+  /* Next TX descriptor to use.*/
+  macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3;
+
+  osalSysUnlock();
+
+  /* Set the buffer size and configuration.*/
+  tdp->offset   = 0;
+  tdp->size     = TIVA_MAC_BUFFERS_SIZE;
+  tdp->physdesc = tdes;
+
+  return MSG_OK;
+}
+
+/**
+ * @brief   Releases a transmit descriptor and starts the transmission of the
+ *          enqueued data as a single frame.
+ *
+ * @param[in] tdp       the pointer to the @p MACTransmitDescriptor structure
+ *
+ * @notapi
+ */
+void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
+{
+  osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
+              "attempt to release descriptor already owned by DMA");
+
+  osalSysLock();
+
+  /* Unlocks the descriptor and returns it to the DMA engine.*/
+  tdp->physdesc->tdes1 = tdp->offset;
+  tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) |
+                         TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS |
+                         TIVA_TDES0_TCH | TIVA_TDES0_OWN;
+  tdp->physdesc->locked = 0;
+
+  /* If the DMA engine is stalled then a restart request is issued.*/
+  if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) {
+    ETH->DMARIS   = (1 << 2);
+    ETH->TXPOLLD = 1; /* Any value is OK.*/
+  }
+
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Returns a receive descriptor.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @param[out] rdp      pointer to a @p MACReceiveDescriptor structure
+ * @return              The operation status.
+ * @retval RDY_OK       the descriptor has been obtained.
+ * @retval RDY_TIMEOUT  descriptor not available.
+ *
+ * @notapi
+ */
+msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
+                                     MACReceiveDescriptor *rdp)
+{
+  tiva_eth_rx_descriptor_t *rdes;
+
+  osalSysLock();
+
+  /* Get Current RX descriptor.*/
+  rdes = macp->rxptr;
+
+  /* Iterates through received frames until a valid one is found, invalid
+     frames are discarded.*/
+  while (!(rdes->rdes0 & TIVA_RDES0_OWN)) {
+    if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES))
+#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
+        && (rdes->rdes0 & TIVA_RDES0_FT)
+        && !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE))
+#endif
+        && (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) {
+      /* Found a valid one.*/
+      rdp->offset   = 0;
+      rdp->size     = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4;
+      rdp->physdesc = rdes;
+      macp->rxptr   = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
+
+      osalSysUnlock();
+      return MSG_OK;
+    }
+    /* Invalid frame found, purging.*/
+    rdes->rdes0 = TIVA_RDES0_OWN;
+    rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
+  }
+
+  /* Next descriptor to check.*/
+  macp->rxptr = rdes;
+
+  osalSysUnlock();
+  return MSG_TIMEOUT;
+}
+
+/**
+ * @brief   Releases a receive descriptor.
+ * @details The descriptor and its buffer are made available for more incoming
+ *          frames.
+ *
+ * @param[in] rdp       the pointer to the @p MACReceiveDescriptor structure
+ *
+ * @notapi
+ */
+void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
+{
+  osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
+              "attempt to release descriptor already owned by DMA");
+
+  osalSysLock();
+
+  /* Give buffer back to the Ethernet DMA.*/
+  rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
+
+  /* If the DMA engine is stalled then a restart request is issued.*/
+  if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) {
+    ETH->DMARIS   = (1 << 7);
+    ETH->TXPOLLD = 1; /* Any value is OK.*/
+  }
+
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Updates and returns the link status.
+ *
+ * @param[in] macp      pointer to the @p MACDriver object
+ * @return              The link status.
+ * @retval TRUE         if the link is active.
+ * @retval FALSE        if the link is down.
+ *
+ * @notapi
+ */
+bool mac_lld_poll_link_status(MACDriver *macp)
+{
+  uint32_t maccfg, bmsr, bmcr;
+
+  maccfg = ETH->CFG;
+
+  /* PHY CR and SR registers read.*/
+  (void)mii_read(macp, MII_BMSR);
+  bmsr = mii_read(macp, MII_BMSR);
+  bmcr = mii_read(macp, MII_BMCR);
+
+  /* Check on auto-negotiation mode.*/
+  if (bmcr & BMCR_ANENABLE) {
+    uint32_t lpa;
+
+    /* Auto-negotiation must be finished without faults and link established.*/
+    if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
+        (BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
+      return macp->link_up = false;
+
+    /* Auto-negotiation enabled, checks the LPA register.*/
+    lpa = mii_read(macp, MII_LPA);
+
+    /* Check on link speed.*/
+    if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
+      maccfg |= (1 << 14);
+    else
+      maccfg &= ~(1 << 14);
+
+    /* Check on link mode.*/
+    if (lpa & (LPA_10FULL | LPA_100FULL))
+      maccfg |= (1 << 11);
+    else
+      maccfg &= ~(1 << 11);
+  }
+  else {
+    /* Link must be established.*/
+    if (!(bmsr & BMSR_LSTATUS))
+      return macp->link_up = false;
+
+    /* Check on link speed.*/
+    if (bmcr & BMCR_SPEED100)
+      maccfg |= (1 << 14);
+    else
+      maccfg &= ~(1 << 14);
+
+    /* Check on link mode.*/
+    if (bmcr & BMCR_FULLDPLX)
+      maccfg |= (1 << 11);
+    else
+      maccfg &= ~(1 << 11);
+  }
+
+  /* Changes the mode in the MAC.*/
+  ETH->CFG = maccfg;
+
+  /* Returns the link status.*/
+  return macp->link_up = true;
+}
+
+/**
+ * @brief   Writes to a transmit descriptor's stream.
+ *
+ * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
+ * @param[in] buf       pointer to the buffer containing the data to be
+ *                      written
+ * @param[in] size      number of bytes to be written
+ * @return              The number of bytes written into the descriptor's
+ *                      stream, this value can be less than the amount
+ *                      specified in the parameter @p size if the maximum
+ *                      frame size is reached.
+ *
+ * @notapi
+ */
+size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
+                                         uint8_t *buf,
+                                         size_t size)
+{
+  osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
+              "attempt to write descriptor already owned by DMA");
+
+  if (size > tdp->size - tdp->offset)
+    size = tdp->size - tdp->offset;
+
+  if (size > 0) {
+    memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
+    tdp->offset += size;
+  }
+  return size;
+}
+
+/**
+ * @brief   Reads from a receive descriptor's stream.
+ *
+ * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
+ * @param[in] buf       pointer to the buffer that will receive the read data
+ * @param[in] size      number of bytes to be read
+ * @return              The number of bytes read from the descriptor's
+ *                      stream, this value can be less than the amount
+ *                      specified in the parameter @p size if there are
+ *                      no more bytes to read.
+ *
+ * @notapi
+ */
+size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
+                                       uint8_t *buf,
+                                       size_t size)
+{
+  osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
+              "attempt to read descriptor already owned by DMA");
+
+  if (size > rdp->size - rdp->offset)
+    size = rdp->size - rdp->offset;
+
+  if (size > 0) {
+    memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
+    rdp->offset += size;
+  }
+  return size;
+}
+
+#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
+/**
+ * @brief   Returns a pointer to the next transmit buffer in the descriptor
+ *          chain.
+ * @note    The API guarantees that enough buffers can be requested to fill
+ *          a whole frame.
+ *
+ * @param[in] tdp       pointer to a @p MACTransmitDescriptor structure
+ * @param[in] size      size of the requested buffer. Specify the frame size
+ *                      on the first call then scale the value down subtracting
+ *                      the amount of data already copied into the previous
+ *                      buffers.
+ * @param[out] sizep    pointer to variable receiving the buffer size, it is
+ *                      zero when the last buffer has already been returned.
+ *                      Note that a returned size lower than the amount
+ *                      requested means that more buffers must be requested
+ *                      in order to fill the frame data entirely.
+ * @return              Pointer to the returned buffer.
+ * @retval NULL         if the buffer chain has been entirely scanned.
+ *
+ * @notapi
+ */
+uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
+                                          size_t size,
+                                          size_t *sizep)
+{
+  if (tdp->offset == 0) {
+    *sizep      = tdp->size;
+    tdp->offset = size;
+    return (uint8_t *)tdp->physdesc->tdes2;
+  }
+  *sizep = 0;
+  return NULL;
+}
+
+/**
+ * @brief   Returns a pointer to the next receive buffer in the descriptor
+ *          chain.
+ * @note    The API guarantees that the descriptor chain contains a whole
+ *          frame.
+ *
+ * @param[in] rdp       pointer to a @p MACReceiveDescriptor structure
+ * @param[out] sizep    pointer to variable receiving the buffer size, it is
+ *                      zero when the last buffer has already been returned.
+ * @return              Pointer to the returned buffer.
+ * @retval NULL         if the buffer chain has been entirely scanned.
+ *
+ * @notapi
+ */
+const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
+                                               size_t *sizep)
+{
+  if (rdp->size > 0) {
+    *sizep      = rdp->size;
+    rdp->offset = rdp->size;
+    rdp->size   = 0;
+    return (uint8_t *)rdp->physdesc->rdes2;
+  }
+  *sizep = 0;
+  return NULL;
+}
+#endif /* MAC_USE_ZERO_COPY */
+
+#endif /* HAL_USE_MAC */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/mac_lld.h b/os/hal/ports/TIVA/LLD/mac_lld.h
new file mode 100644
index 0000000..7c86dbd
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/mac_lld.h
@@ -0,0 +1,434 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/mac_lld.h
+ * @brief   MAC Driver subsystem low level driver header.
+ *
+ * @addtogroup MAC
+ * @{
+ */
+
+#ifndef _MAC_LLD_H_
+#define _MAC_LLD_H_
+
+#if HAL_USE_MAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   This implementation supports the zero-copy mode API.
+ */
+#define MAC_SUPPORTS_ZERO_COPY      TRUE
+
+/**
+ * @name    RDES0 constants
+ * @{
+ */
+#define TIVA_RDES0_OWN              0x80000000
+#define TIVA_RDES0_AFM              0x40000000
+
+#define TIVA_RDES0_FL_MASK          0x3FFF0000
+#define TIVA_RDES0_FL(n)            ((n) << 16)
+
+#define TIVA_RDES0_ES               0x00008000
+#define TIVA_RDES0_DESERR           0x00004000
+#define TIVA_RDES0_SAF              0x00002000
+#define TIVA_RDES0_LE               0x00001000
+#define TIVA_RDES0_OE               0x00000800
+#define TIVA_RDES0_VLAN             0x00000400
+#define TIVA_RDES0_FS               0x00000200
+#define TIVA_RDES0_LS               0x00000100
+#define TIVA_RDES0_TAGF             0x00000080
+#define TIVA_RDES0_LC               0x00000040
+#define TIVA_RDES0_FT               0x00000020
+#define TIVA_RDES0_RWT              0x00000010
+#define TIVA_RDES0_RE               0x00000008
+#define TIVA_RDES0_DE               0x00000004
+#define TIVA_RDES0_CE               0x00000002
+#define TIVA_RDES0_ESA              0x00000001
+/** @} */
+
+/**
+ * @name    RDES1 constants
+ * @{
+ */
+#define TIVA_RDES1_DIC              0x80000000
+
+#define TIVA_RDES1_RBS2_MASK        0x1FFF0000
+#define TIVA_RDES1_RBS2(n)          ((n) << 16)
+
+#define TIVA_RDES1_RER              0x00008000
+#define TIVA_RDES1_RCH              0x00004000
+
+#define TIVA_RDES1_RBS1_MASK        0x00001FFF
+#define TIVA_RDES1_RBS1(n)          ((n) << 0)
+
+/** @} */
+
+/**
+ * @name    TDES0 constants
+ * @{
+ */
+#define TIVA_TDES0_OWN              0x80000000
+#define TIVA_TDES0_IC               0x40000000
+#define TIVA_TDES0_LS               0x20000000
+#define TIVA_TDES0_FS               0x10000000
+#define TIVA_TDES0_DC               0x08000000
+#define TIVA_TDES0_DP               0x04000000
+#define TIVA_TDES0_TTSE             0x02000000
+#define TIVA_TDES0_CRCR             0x01000000
+
+#define TIVA_TDES0_CIC_MASK         0x00C00000
+#define TIVA_TDES0_CIC(n)           ((n) << 22)
+
+#define TIVA_TDES0_TER              0x00200000
+#define TIVA_TDES0_TCH              0x00100000
+#define TIVA_TDES0_VLIC             0x000C0000
+#define TIVA_TDES0_TTSS             0x00020000
+#define TIVA_TDES0_IHE              0x00010000
+#define TIVA_TDES0_ES               0x00008000
+#define TIVA_TDES0_JT               0x00004000
+#define TIVA_TDES0_FF               0x00002000
+#define TIVA_TDES0_IPE              0x00001000
+#define TIVA_TDES0_LC               0x00000800
+#define TIVA_TDES0_NC               0x00000400
+#define TIVA_TDES0_LCO              0x00000200
+#define TIVA_TDES0_EC               0x00000100
+#define TIVA_TDES0_VF               0x00000080
+
+#define TIVA_TDES0_CC_MASK          0x00000078
+#define TIVA_TDES0_CC(n)            ((n) << 3)
+
+#define TIVA_TDES0_ED               0x00000004
+#define TIVA_TDES0_UF               0x00000002
+#define TIVA_TDES0_DB               0x00000001
+/** @} */
+
+/**
+ * @name    TDES1 constants
+ * @{
+ */
+#define TIVA_TDES1_SAIC_MASK        0xE0000000
+#define TIVA_TDES1_SAIC(n)          ((n) << 29)
+
+#define TIVA_TDES1_TBS2_MASK        0x1FFF0000
+#define TIVA_TDES1_TBS2(n)          ((n) << 16)
+
+#define TIVA_TDES1_TBS1_MASK        0x00001FFF
+#define TIVA_TDES1_TBS1(n)          ((n) << 0)
+/** @} */
+
+
+
+
+/**
+ * @name    Ethernet PHY registers
+ */
+#define TIVA_BMCR                   0x00000000  /* MR0  - Basic Mode Control     */
+#define TIVA_BMSR                   0x00000001  /* MR1  - Basic Mode Status      */
+#define TIVA_ID1                    0x00000002  /* MR2  - Identifier Register 1  */
+#define TIVA_ID2                    0x00000003  /* MR3  - Identifier Register 2  */
+#define TIVA_ANA                    0x00000004  /* MR4  - Auto-Negotiation Advertisement */
+#define TIVA_ANLPA                  0x00000005  /* MR5  - Auto-Negotiation Link Partner Ability */
+#define TIVA_ANER                   0x00000006  /* MR6  - Auto-Negotiation Expansion */
+#define TIVA_ANNPTR                 0x00000007  /* MR7  - Auto-Negotiation Next Page TX */
+#define TIVA_ANLNPTR                0x00000008  /* MR8  - Auto-Negotiation Link Partner Ability Next Page */
+#define TIVA_CFG1                   0x00000009  /* MR9  - Configuration 1        */
+#define TIVA_CFG2                   0x0000000A  /* MR10 - Configuration 2        */
+#define TIVA_CFG3                   0x0000000B  /* MR11 - Configuration 3        */
+#define TIVA_REGCTL                 0x0000000D  /* MR13 - Register Control       */
+#define TIVA_ADDAR                  0x0000000E  /* MR14 - Address or Data        */
+#define TIVA_STS                    0x00000010  /* MR16 - Status                 */
+#define TIVA_SCR                    0x00000011  /* MR17 - Specific Control       */
+#define TIVA_MISR1                  0x00000012  /* MR18 - MII Interrupt Status 1 */
+#define TIVA_MISR2                  0x00000013  /* MR19 - MII Interrupt Status 2 */
+#define TIVA_FCSCR                  0x00000014  /* MR20 - False Carrier Sense Counter */
+#define TIVA_RXERCNT                0x00000015  /* MR21 - Receive Error Count    */
+#define TIVA_BISTCR                 0x00000016  /* MR22 - BIST Control           */
+#define TIVA_LEDCR                  0x00000018  /* MR24 - LED Control            */
+#define TIVA_CTL                    0x00000019  /* MR25 - Control                */
+#define TIVA_10BTSC                 0x0000001A  /* MR26 - 10Base-T Status/Control - MR26 */
+#define TIVA_BICSR1                 0x0000001B  /* MR27 - BIST Control and Status 1 */
+#define TIVA_BICSR2                 0x0000001C  /* MR28 - BIST Control and Status 2 */
+#define TIVA_CDCR                   0x0000001E  /* MR30 - Cable Diagnostic Control */
+#define TIVA_RCR                    0x0000001F  /* MR31 - Reset Control          */
+#define TIVA_LEDCFG                 0x00000025  /* MR37 - LED Configuration      */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Number of available transmit buffers.
+ */
+#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
+#define TIVA_MAC_TRANSMIT_BUFFERS           2
+#endif
+
+/**
+ * @brief   Number of available receive buffers.
+ */
+#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
+#define TIVA_MAC_RECEIVE_BUFFERS            4
+#endif
+
+/**
+ * @brief   Maximum supported frame size.
+ */
+#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define TIVA_MAC_BUFFERS_SIZE               1522
+#endif
+
+/**
+ * @brief   PHY detection timeout.
+ * @details Timeout, in milliseconds, for PHY address detection, if a PHY
+ *          is not detected within the timeout then the driver halts during
+ *          initialization. This setting applies only if the PHY address is
+ *          not explicitly set in the board header file using
+ *          @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
+ *          single search path is performed.
+ */
+#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
+#define TIVA_MAC_PHY_TIMEOUT                0
+#endif
+
+/**
+ * @brief   Change the PHY power state inside the driver.
+ */
+#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
+#define TIVA_MAC_CHANGE_PHY_STATE           TRUE
+#endif
+
+/**
+ * @brief   ETHD1 interrupt priority level setting.
+ */
+#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_MAC_IRQ_PRIORITY               5
+#endif
+
+/**
+ * @brief   IP checksum offload.
+ * @details The following modes are available:
+ *          - 0 Function disabled.
+ *          - 1 Only IP header checksum calculation and insertion are enabled.
+ *          - 2 IP header checksum and payload checksum calculation and
+ *              insertion are enabled, but pseudo-header checksum is not
+ *              calculated in hardware.
+ *          - 3 IP Header checksum and payload checksum calculation and
+ *              insertion are enabled, and pseudo-header checksum is
+ *              calculated in hardware.
+ *          .
+ */
+#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
+#define TIVA_MAC_IP_CHECKSUM_OFFLOAD        0
+#endif
+/** @} */
+
+#ifndef EMAC_PHY_CONFIG
+#define EMAC_PHY_CONFIG         ((0 << 31) | \
+                                 (1 << 23) | \
+                                 (1 << 10) | \
+                                 (1 << 3)  | \
+                                 (3 << 1)  | \
+                                 (1 << 0))
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
+#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of an Tiva Ethernet receive descriptor.
+ */
+typedef struct
+{
+  volatile uint32_t     rdes0;
+  volatile uint32_t     rdes1;
+  volatile uint32_t     rdes2;
+  volatile uint32_t     rdes3;
+} tiva_eth_rx_descriptor_t;
+
+/**
+ * @brief   Type of an Tiva Ethernet transmit descriptor.
+ */
+typedef struct
+{
+  volatile uint32_t     tdes0;
+  volatile uint32_t     tdes1;
+  volatile uint32_t     tdes2;
+  volatile uint32_t     tdes3;
+  volatile uint32_t     locked;
+} tiva_eth_tx_descriptor_t;
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct
+{
+  /**
+   * @brief MAC address.
+   */
+  uint8_t               *mac_address;
+  /* End of the mandatory fields.*/
+} MACConfig;
+
+/**
+ * @brief   Structure representing a MAC driver.
+ */
+struct MACDriver
+{
+  /**
+   * @brief Driver state.
+   */
+  macstate_t            state;
+  /**
+   * @brief Current configuration data.
+   */
+  const MACConfig       *config;
+  /**
+   * @brief Transmit semaphore.
+   */
+  threads_queue_t       tdqueue;
+  /**
+   * @brief Receive semaphore.
+   */
+  threads_queue_t       rdqueue;
+#if MAC_USE_EVENTS || defined(__DOXYGEN__)
+  /**
+   * @brief Receive event.
+   */
+  event_source_t        rdevent;
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Link status flag.
+   */
+  bool                  link_up;
+  /**
+   * @brief PHY address (pre shifted).
+   */
+  uint32_t              phyaddr;
+  /**
+   * @brief Receive next frame pointer.
+   */
+  tiva_eth_rx_descriptor_t *rxptr;
+  /**
+   * @brief Transmit next frame pointer.
+   */
+  tiva_eth_tx_descriptor_t *txptr;
+};
+
+/**
+ * @brief   Structure representing a transmit descriptor.
+ */
+typedef struct
+{
+  /**
+   * @brief Current write offset.
+   */
+  size_t                    offset;
+  /**
+   * @brief Available space size.
+   */
+  size_t                    size;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the physical descriptor.
+   */
+  tiva_eth_tx_descriptor_t *physdesc;
+} MACTransmitDescriptor;
+
+/**
+ * @brief   Structure representing a receive descriptor.
+ */
+typedef struct
+{
+  /**
+   * @brief Current read offset.
+   */
+  size_t                offset;
+  /**
+   * @brief Available data size.
+   */
+  size_t                size;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the physical descriptor.
+   */
+  tiva_eth_rx_descriptor_t *physdesc;
+} MACReceiveDescriptor;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+extern MACDriver ETHD1;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void mac_lld_init(void);
+  void mac_lld_start(MACDriver *macp);
+  void mac_lld_stop(MACDriver *macp);
+  msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
+                                        MACTransmitDescriptor *tdp);
+  void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
+  msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
+                                       MACReceiveDescriptor *rdp);
+  void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
+  bool mac_lld_poll_link_status(MACDriver *macp);
+  size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
+                                           uint8_t *buf,
+                                           size_t size);
+  size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
+                                         uint8_t *buf,
+                                         size_t size);
+#if MAC_USE_ZERO_COPY
+  uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
+                                            size_t size,
+                                            size_t *sizep);
+  const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
+                                                 size_t *sizep);
+#endif /* MAC_USE_ZERO_COPY */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_MAC */
+
+#endif /* _MAC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/pal_lld.c b/os/hal/ports/TIVA/LLD/pal_lld.c
index 9939331..657f982 100644
--- a/os/hal/ports/TIVA/LLD/pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/pal_lld.c
@@ -165,7 +165,7 @@ void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
  */
 void _pal_lld_init(const PALConfig *config)
 {
-  SYSCTL->RCGC.GPIO = RCGCGPIO_VALUE;
+  SYSCTL->RCGCGPIO = RCGCGPIO_VALUE;
 
   __NOP();
   __NOP();
diff --git a/os/hal/ports/TIVA/LLD/serial_lld.c b/os/hal/ports/TIVA/LLD/serial_lld.c
index 9238942..92761dc 100644
--- a/os/hal/ports/TIVA/LLD/serial_lld.c
+++ b/os/hal/ports/TIVA/LLD/serial_lld.c
@@ -507,7 +507,7 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
   if (sdp->state == SD_STOP) {
 #if TIVA_SERIAL_USE_UART0
     if (&SD1 == sdp) {
-      SYSCTL->RCGC.UART |= (1 << 0);
+      SYSCTL->RCGCUART |= (1 << 0);
       nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY);
     }
 #endif
@@ -570,7 +570,7 @@ void sd_lld_stop(SerialDriver *sdp)
     uart_deinit(sdp->uart);
 #if TIVA_SERIAL_USE_UART0
     if (&SD1 == sdp) {
-      SYSCTL->RCGC.UART &= ~(1 << 0);  /* disable UART0 module */
+      SYSCTL->RCGCUART &= ~(1 << 0);  /* disable UART0 module */
       nvicDisableVector(TIVA_UART0_NUMBER);
       return;
     }
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
index 3bfe485..4f2a968 100644
--- a/os/hal/ports/TIVA/TM4C129x/hal_lld.c
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
@@ -109,8 +109,8 @@ void tiva_clock_init(void)
    * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
    * the configure the desired VCO frequency setting.
    */
-  SYSCTL->PLLFREQ[1] = (0x04 << 0); // 5 - 1
-  SYSCTL->PLLFREQ[0] = (0x60 << 0) | PLLFREQ0_PLLPWR;
+  SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1
+  SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR;
 
   /*
    * 7. Write the MEMTIM0 register to correspond to the new system clock setting.
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
index 83331e0..35de5ce 100644
--- a/os/hal/ports/TIVA/TM4C129x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -3,7 +3,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \
-              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
index 18072a4..462a14f 100644
--- a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
+++ b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
@@ -534,109 +534,251 @@ typedef struct
  */
 typedef struct
 {
-  __I  uint32_t PDS;        /**< Power Domain Status */
-  __IO uint32_t MPC;        /**< Memory Power Control */
-} SYSCTL_PDSMPC_t;
-
-typedef struct
-{
-  uint32_t WD;                  /**< Watchdog Timer                          */
-  uint32_t TIMER;               /**< General-Purpose Timer                   */
-  uint32_t GPIO;                /**< General-Purpose Input/Output            */
-  uint32_t DMA;                 /**< Micro Direct Memory Access              */
-  uint32_t EPI;                 /**< EPI */
-  uint32_t HIB;                 /**< Hibernation                             */
-  uint32_t UART;                /**< Universal Asynchronous
-                                     Receiver/Transmitter                    */
-  uint32_t SSI;                 /**< Synchronous Serial Interface            */
-  uint32_t I2C;                 /**< Inter-Integrated Circuit                */
-  uint32_t _RESERVED0[1];   /**< Reserved                                */
-  uint32_t USB;                 /**< Universal Serial Bus                    */
-  uint32_t _RESERVED1[1];   /**< Reserved                                */
-  uint32_t EPHY;                /**< Ethernet PHY*/
-  uint32_t CAN;                 /**< Controller Area Network                 */
-  uint32_t ADC;                 /**< Analog-to-Digital Converter             */
-  uint32_t ACMP;                /**< Analog Comparator                       */
-  uint32_t PWM;                 /**< Pulse Width Modulator                   */
-  uint32_t QEI;                 /**< Quadrature Encoder Interface            */
-  uint32_t LPC;                 /**< Low Pin Count Interface */
-  uint32_t _RESERVED2[1];   /**< Reserved */
-  uint32_t PECI;                /**< Platform Environment Control Interface */
-  uint32_t FAN;                 /**< Fan Control  */
-  uint32_t EEPROM;              /**< EEPROM                                  */
-  uint32_t WTIMER;              /**< Wide General-Purpose Timer              */
-  uint32_t _RESERVED3[4];   /**< Reserved */
-  uint32_t RTS;                 /**< Remote Temperature Sensor */
-  uint32_t CCM;                 /**< CRC Module  */
-  uint32_t _RESERVED4[6];   /**< Reserved */
-  uint32_t LCD;                 /**< LCD  */
-  uint32_t _RESERVED5[1];   /**< Reserved */
-  uint32_t OWIRE;               /**< 1-Wire */
-  uint32_t EMAC;                /**< Ethernet MAC */
-  uint32_t PRB;                 /**< Power Regulator Bus  */
-  uint32_t HIM;                 /**< Human Interface Master  */
-  uint32_t _RESERVED6[24];  /**< Reserved */
-} SYSCTL_PERIPH_t;
-
-typedef struct
-{
-  __I  uint32_t DID[2];         /**< Device Identification 0 and 1           */
-  __I  uint32_t _RESERVED0[12]; /**< Reserved                                */
-  __IO uint32_t PBORCTL;        /**< Power-Temp Brown Out Control            */
-  __I  uint32_t _RESERVED1[5];  /**< Reserved                                */
+  __I  uint32_t DID0;           /**< Device Identification 0                 */
+  __I  uint32_t DID1;           /**< Device Identification 1                 */
+  __I  uint32_t RESERVED0[12];  /**< Reserved                                */
+  __IO uint32_t PBORCTL;        /**< Power-Temp Brown Out Control                 */
+  __I  uint32_t RESERVED1[5];   /**< Reserved                                */
   __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
   __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
   __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
   __IO uint32_t RESC;           /**< Reset Cause                             */
   __IO uint32_t PWRTC;          /**< Power-Temperature Cause */
   __IO uint32_t NMIC;           /**< NMI Cause Register */
-  __I  uint32_t _RESERVED2[5];  /**< Reserved */
+  __I  uint32_t RESERVED2[5];   /**< Reserved */
   __IO uint32_t MOSCCTL;        /**< Main Oscillator Control */
-  __I  uint32_t _RESERVED3[12]; /**< Reserved */
+  __I  uint32_t RESERVED3[12];  /**< Reserved */
   __IO uint32_t RSCLKCFG;       /**< Run and Sleep Mode Configuration Register */
-  __I  uint32_t _RESERVED4[3];
+  __I  uint32_t RESERVEDx[3];
   __IO uint32_t MEMTIM0;        /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
-  __I  uint32_t _RESERVED5[29]; /**< Reserved */
+  __I  uint32_t RESERVED4[29];  /**< Reserved */
   __IO uint32_t ALTCLKCFG;      /**< Alternate Clock Configuration */
-  __I  uint32_t _RESERVED6[2];  /**< Reserved                                */
+  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
   __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
   __IO uint32_t DIVSCLK;        /**< Divisor and Source Clock Configuration  */
   __I  uint32_t SYSPROP;        /**< System Properties                       */
   __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
   __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
-  __I  uint32_t _RESERVED7[2];  /**< Reserved                                */
-  __IO uint32_t PLLFREQ[2];     /**< PLL Frequency 0 and 1                   */
+  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
+  __IO uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
+  __IO uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
   __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
-  __I  uint32_t _RESERVED8[7];  /**< Reserved                                */
+  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
   __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
   __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
-  __I  uint32_t _RESERVED9[4];  /**< Reserved                                */
+  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
   __I  uint32_t NVMSTAT;        /**< Non-Volatile Memory Information */
-  __I  uint32_t _RESERVED10[4]; /**< Reserved */
+  __I  uint32_t RESERVED9[4];   /**< Reserved */
   __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
   __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
   __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
   __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
-  __I  uint32_t _RESERVED11[2]; /**< Reserved                                */
+  __I  uint32_t RESERVED10[2];  /**< Reserved                                */
   __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
-  __I  uint32_t _RESERVED12[2]; /**< Reserved */
+  __I  uint32_t RESERVED11[2];  /**< Reserved */
   __IO uint32_t RESBEHAVCTL;    /**< Reset Behavior Control Register */
-  __I  uint32_t _RESERVED13[6]; /**< Reserved */
+  __I  uint32_t RESERVED12[6];  /**< Reserved */
   __IO uint32_t HSSR;           /**< Hardware System Service Request */
-  __I  uint32_t _RESERVED14[34];/**< Reserved */
-  SYSCTL_PDSMPC_t USB;          /**< USB PDS/MPC */
-  SYSCTL_PDSMPC_t EMAC;         /**< EMAC PDS/MPC */
-  SYSCTL_PDSMPC_t LCD;          /**< LCD PDS/MPC */
-  SYSCTL_PDSMPC_t CAN[2];       /**< CAN 0 and 1 PDS/MPC */
-  __I  uint32_t _RESERVED15[22];/**< Reserved */
-  __I SYSCTL_PERIPH_t PP;       /**< Peripheral Present                      */
-  __I  uint32_t _RESERVED16[60];/**< Reserved */
-  __IO SYSCTL_PERIPH_t SR;      /**< Software Reset */
-  __IO SYSCTL_PERIPH_t RCGC;    /**< Run Mode Clock Gating Control           */
-  __IO SYSCTL_PERIPH_t SCGC;    /**< Sleep Mode Clock Gating Control         */
-  __IO SYSCTL_PERIPH_t DCGC;    /**< Deep-Sleep Mode Clock Gating Control    */
-  __IO SYSCTL_PERIPH_t PC;      /**< Power Control                           */
-  __IO SYSCTL_PERIPH_t PR;      /**< Peripheral Ready                        */
+  __I  uint32_t RESERVED[34];   /**< Reserved */
+  __I  uint32_t USBPDS;         /**< USB Power Domain Status */
+  __IO uint32_t USBMPC;         /**< USB Memory Power Control */
+  __I  uint32_t EMACPDS;        /**< Ethernet MAC Power Domain Status */
+  __IO uint32_t EMACMPC;        /**< Ethernet MAC Memory Power Control */
+  __I  uint32_t RESERVED13[2];  /**< Reserved */
+  __I  uint32_t CAN0PDS;        /**< CAN 0 Power Domain Status */
+  __IO uint32_t CAN0MPC;        /**< CAN 0 Memory Power Control */
+  __I  uint32_t CAN1PDS;        /**< CAN 1 Power Domain Status */
+  __IO uint32_t CAN1MPC;        /**< CAN 1 Memory Power Control */
+  __I  uint32_t RESERVED14[22]; /**< Reserved */
+  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
+  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
+  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
+  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
+  __I  uint32_t PPEPI;          /**< EPI Peripheral Present */
+  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
+  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
+  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
+  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
+  __I  uint32_t RESERVED15[1];  /**< Reserved                                */
+  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
+  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
+  __I  uint32_t PPEPHY;         /**< Ethernet PHY Peripheral Present */
+  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
+  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
+  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
+  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
+  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
+  __I  uint32_t PPLPC;          /**< Low Pin Count Interface Peripheral Present */
+  __I  uint32_t RESERVED17[1];  /**< Reserved */
+  __I  uint32_t PPPECI;         /**< Platform Environment Control Interface Peripheral Present */
+  __I  uint32_t PPFAN;          /**< Fan Control Peripheral Present */
+  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
+  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
+  __I  uint32_t RESERVED18[4];  /**< Reserved */
+  __I  uint32_t PPRTS;          /**< Remote Temperature Sensor Peripheral Present */
+  __I  uint32_t PPCCM;          /**< CRC Module Peripheral Present */
+  __I  uint32_t RESERVED19[6];  /**< Reserved */
+  __I  uint32_t PPLCD;          /**< LCD Peripheral Present */
+  __I  uint32_t RESERVED20[1];  /**< Reserved */
+  __I  uint32_t PPOWIRE;        /**< 1-Wire Peripheral Present */
+  __I  uint32_t PPEMAC;         /**< Ethernet MAC Peripheral Present */
+  __I  uint32_t PPPRB;          /**< Power Regulator Bus Peripheral Present */
+  __I  uint32_t PPHIM;          /**< Human Interface Master Peripheral Present */
+  __I  uint32_t RESERVED21[86]; /**< Reserved */
+  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
+  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
+  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
+  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
+  __IO uint32_t SREPI;          /**< EPI Software Reset */
+  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
+  __IO uint32_t SRUART;         /**< UART Software Reset                     */
+  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
+  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
+  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
+  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
+  __I  uint32_t RESERVED23[1];  /**< Reserved                                */
+  __IO uint32_t SREPHY;         /**< Ethernet PHY Software Reset */
+  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
+  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
+  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
+  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
+  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
+  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
+  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
+  __I  uint32_t RESERVED25[6];  /**< Reserved */
+  __IO uint32_t SRCCM;          /**< CRC Module Software Reset */
+  __I  uint32_t RESERVED26[9];  /**< Reserved */
+  __IO uint32_t SREMAC;         /**< Ethernet MAC Software Reset */
+  __I  uint32_t RESERVED27[24]; /**< Reserved                                */
+  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCEPI;        /**< EPI Run Mode Clock Gating Control */
+  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
+  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED28[1];  /**< Reserved                                */
+  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED29[1];  /**< Reserved                                */
+  __IO uint32_t RCGCEPHY;       /**< Ethernet PHY Run Mode Clock Gating Control */
+  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED30[4];  /**< Reserved                                */
+  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
+  __I  uint32_t RESERVED31[6];  /**< Reserved */
+  __IO uint32_t RCGCCCM;        /**< CRC Module Run Mode Clock Gating Control */
+  __I  uint32_t RESERVED32[9];  /**< Reserved */
+  __IO uint32_t RCGCEMAC;       /**< Ethernet MAC Run Mode Clock Gating Control */
+  __I  uint32_t RESERVED33[24]; /**< Reserved */
+  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCEPI;        /**< EPI Sleep Mode Clock Gating Control */
+  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED34[1];  /**< Reserved                                */
+  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED35[1];  /**< Reserved                                */
+  __IO uint32_t SCGCEPHY;       /**< Ethernet PHY Sleep Mode Clock Gating Control */
+  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED36[4];  /**< Reserved                                */
+  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
+  __I  uint32_t RESERVED37[6];  /**< Reserved */
+  __IO uint32_t SCGCCCM;        /**< CRC Module Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED38[9];  /**< Reserved */
+  __IO uint32_t SCGCEMAC;       /**< Ethernet MAC Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED39[24]; /**< Reserved                                */
+  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCEPI;        /**< EPI Deep-Sleep Mode Clock Gating Control */
+  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED40[1];  /**< Reserved                                */
+  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED41[1];  /**< Reserved                                */
+  __IO uint32_t DCGCEPHY;       /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
+  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED42[4];  /**< Reserved                                */
+  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __I  uint32_t RESERVED43[6];  /**< Reserved */
+  __IO uint32_t DCGCCCM;        /**< CRC Module Deep-Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED44[9];  /**< Reserved */
+  __IO uint32_t DCGCEMAC;       /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED45[24]; /**< Reserved                                */
+  __IO uint32_t PCWD;           /**< Watchdog Timer Power Control       */
+  __IO uint32_t PCTIMER;        /**< 16/32-Bit General-Purpose Timer Power Control       */
+  __IO uint32_t PCGPIO;         /**< General-Purpose Input/Output Power Control      */
+  __IO uint32_t PCDMA;          /**< Micro Direct Memory Access Power Control      */
+  __IO uint32_t PCEPI;          /**< External Peripheral Interface Power Control */
+  __IO uint32_t PCHIB;          /**< Hibernation Power Control       */
+  __IO uint32_t PCUART;         /**< Universal Asynchronous Receiver/Transmitter Power Control                   */
+  __IO uint32_t PCSSI;          /**< Synchronous Serial Interface Power Control       */
+  __IO uint32_t PCI2C;          /**< Inter-Integrated Circuit Power Control       */
+  __I  uint32_t RESERVED46[1];  /**< Reserved                                */
+  __IO uint32_t PCUSB;          /**< Universal Serial Bus Power Control       */
+  __I  uint32_t RESERVED47[1];  /**< Reserved                                */
+  __IO uint32_t PCEPHY;         /**< Ethernet PHY Power Control */
+  __IO uint32_t PCCAN;          /**< Controller Area Network Power Control       */
+  __IO uint32_t PCADC;          /**< Analog-to-Digital Converter Power Control       */
+  __IO uint32_t PCACMP;         /**< Analog Comparator Power Control      */
+  __IO uint32_t PCPWM;          /**< Pulse Width Modulator Power Control       */
+  __IO uint32_t PCQEI;          /**< Quadrature Encoder Interface Power Control       */
+  __I  uint32_t RESERVED48[4];  /**< Reserved                                */
+  __IO uint32_t PCEEPROM;       /**< EEPROM Power Control    */
+  __I  uint32_t RESERVED49[6];  /**< Reserved */
+  __IO uint32_t PCCCM;          /**< CRC Module Power Control */
+  __I  uint32_t RESERVED50[9];  /**< Reserved */
+  __IO uint32_t PCEMAC;         /**< Ethernet MAC Power Control */
+  __I  uint32_t RESERVED51[24]; /**< Reserved */
+  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
+  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
+  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
+  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
+  __IO uint32_t PREPI;          /**< EPI Peripheral Ready                                */
+  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
+  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
+  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
+  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
+  __I  uint32_t RESERVED52[1];  /**< Reserved                                */
+  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
+  __I  uint32_t RESERVED53[1];  /**< Reserved                                */
+  __IO uint32_t PREPHY;         /**< Ethernet PHY Peripheral Ready */
+  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
+  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
+  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
+  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
+  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
+  __I  uint32_t RESERVED54[4];  /**< Reserved                                */
+  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
+  __I  uint32_t RESERVED55[6];  /**< Reserved */
+  __IO uint32_t PRCCM;          /**< CRC Module Peripheral Ready               */
+  __I  uint32_t RESERVED56[9];  /**< Reserved */
+  __IO uint32_t PREMAC;         /**< Ethernet MAC Peripheral Ready */
 } SYSCTL_TypeDef;
 
 /**
@@ -723,6 +865,106 @@ typedef struct
 } WATCHDOG_TypeDef;
 
 /**
+ * @brief   Ethernet peripheral
+ */
+typedef struct {
+  __IO uint32_t CFG;            /**< Configuration                           */
+  __IO uint32_t FRAMEFLTR;      /**< Frame Filter                            */
+  __IO uint32_t HASHTBLH;       /**< Hash Table High                         */
+  __IO uint32_t HASHTBLL;       /**< Hash Table Low                          */
+  __IO uint32_t MIIADDR;        /**< MII Address                             */
+  __IO uint32_t MIIDATA;        /**< MII Data Register                       */
+  __IO uint32_t FLOWCTL;        /**< Flow Control                            */
+  __IO uint32_t VLANTG;         /**< VLAN Tag                                */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t STATUS;         /**< Status                                  */
+  __IO uint32_t RWUFF;          /**< Remote Wake-Up Frame Filter             */
+  __IO uint32_t PMTCTLSTAT;     /**< PMT Control and Status Register         */
+  __I  uint32_t RESERVED1[2];   /**< Reserved                                */
+  __IO uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __IO uint32_t ADDR0H;         /**< Address 0 High                          */
+  __IO uint32_t ADDR0L;         /**< Address 0 Low Register                  */
+  __IO uint32_t ADDR1H;         /**< Address 1 High                          */
+  __IO uint32_t ADDR1L;         /**< Address 1 Low                           */
+  __IO uint32_t ADDR2H;         /**< Address 2 High                          */
+  __IO uint32_t ADDR2L;         /**< Address 2 Low                           */
+  __IO uint32_t ADDR3H;         /**< Address 3 High                          */
+  __IO uint32_t ADDR3L;         /**< Address 3 Low                           */
+  __I  uint32_t RESERVED2[31];  /**< Reserved                                */
+  __IO uint32_t WDOGTO;         /**< Watchdog Timeout                        */
+  __I  uint32_t RESERVED3[8];   /**< Reserved                                */
+  __IO uint32_t MMCCTRL;        /**< MMC Control                             */
+  __IO uint32_t MMCRXRIS;       /**< MMC Receive Raw Interrupt Status        */
+  __IO uint32_t MMCTXRIS;       /**< MMC Transmit Raw Interrupt Status       */
+  __IO uint32_t MMCRXIM;        /**< MMC Receive Interrupt Mask              */
+  __IO uint32_t MMCTXIM;        /**< MMC Transmit Interrupt Mask             */
+  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
+  __IO uint32_t TXCNTGB;        /**< Transmit Frame Count for Good and Bad
+                                     Frames                                  */
+  __I  uint32_t RESERVED5[12];  /**< Reserved                                */
+  __IO uint32_t TXCNTSCOL;      /**< Transmit Frame Count for Frames
+                                     Transmitted after Single Collision      */
+  __IO uint32_t TXCNTMCOL;      /**< Transmit Frame Count for Frames
+                                     Transmitted after Multiple Collisions   */
+  __I  uint32_t RESERVED6[4];   /**< Reserved                                */
+  __IO uint32_t TXOCTCNTG;      /**< Transmit Octet Count Good               */
+  __I  uint32_t RESERVED7[6];   /**< Reserved                                */
+  __IO uint32_t RXCNTGB;        /**< Receive Frame Count for Good and Bad
+                                     Frames                                  */
+  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
+  __IO uint32_t RXCNTCRCERR;    /**< Receive Frame Count for CRC Error Frames*/
+  __IO uint32_t RXCNTALGNERR;   /**< Receive Frame Count for Alignment Error
+                                     Frames                                  */
+  __I  uint32_t RESERVED9[10];  /**< Reserved                                */
+  __IO uint32_t RXCNTGUNI;      /**< Receive Frame Count for Good Unicast
+                                     Frames                                  */
+  __I  uint32_t RESERVED10[239];/**< Reserved                                */
+  __IO uint32_t VLNINCREP;      /**< VLAN Tag Inclusion or Replacement       */
+  __IO uint32_t VLANHASH;       /**< VLAN Hash Table                         */
+  __I  uint32_t RESERVED11[93]; /**< Reserved                                */
+  __IO uint32_t TIMSTCTRL;      /**< Timestamp Control                       */
+  __IO uint32_t SUBSECINC;      /**< Sub-Second Increment                    */
+  __IO uint32_t TIMSEC;         /**< System Time - Seconds                   */
+  __IO uint32_t TIMNANO;        /**< System Time - Nanoseconds               */
+  __IO uint32_t TIMSECU;        /**< System Time - Seconds Update            */
+  __IO uint32_t TIMNANOU;       /**< System Time - Nanoseconds Update        */
+  __IO uint32_t TIMADD;         /**< Timestamp Addend                        */
+  __IO uint32_t TARGSEC;        /**< Target Time Seconds                     */
+  __IO uint32_t TARGNANO;       /**< Target Time Nanoseconds                 */
+  __IO uint32_t HWORDSEC;       /**< System Time-Higher Word Seconds         */
+  __IO uint32_t TIMSTAT;        /**< Timestamp Status                        */
+  __IO uint32_t PPSCTRL;        /**< PPS Control                             */
+  __I  uint32_t RESERVED12[12]; /**< Reserved                                */
+  __IO uint32_t PPS0INTVL;      /**< PPS0 Interval                           */
+  __IO uint32_t PPS0WIDTH;      /**< PPS0 Width                              */
+  __I  uint32_t RESERVED13[294];/**< Reserved                                */
+  __IO uint32_t DMABUSMOD;      /**< DMA Bus Mode                            */
+  __O  uint32_t TXPOLLD;        /**< Transmit Poll Demand                    */
+  __O  uint32_t RXPOLLD;        /**< Receive Poll Demand                     */
+  __IO uint32_t RXDLADDR;       /**< Receive Descriptor List Address         */
+  __IO uint32_t TXDLADDR;       /**< Transmit Descriptor List Address        */
+  __IO uint32_t DMARIS;         /**< DMA Interrupt Status                    */
+  __IO uint32_t DMAOPMODE;      /**< DMA Operation Mode                      */
+  __IO uint32_t DMAIM;          /**< DMA Interrupt Mask Register             */
+  __IO uint32_t MFBOC;          /**< Missed Frame and Buffer Overflow Counter*/
+  __IO uint32_t RXINTWDT;       /**< Receive Interrupt Watchdog Timer        */
+  __I  uint32_t RESERVED14[8];  /**< Reserved                                */
+  __IO uint32_t HOSTXDESC;      /**< Current Host Transmit Descriptor        */
+  __IO uint32_t HOSRXDESC;      /**< Current Host Receive Descriptor         */
+  __IO uint32_t HOSTXBA;        /**< Current Host Transmit Buffer Address    */
+  __IO uint32_t HOSRXBA;        /**< Current Host Receive Buffer Address     */
+  __I  uint32_t RESERVED15[218];/**< Reserved                                */
+  __IO uint32_t PP;             /**< Peripheral Property Register            */
+  __IO uint32_t PC;             /**< Peripheral Configuration Register       */
+  __IO uint32_t CC;             /**< Clock Configuration Register            */
+  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
+  __I  uint32_t PHYRIS;         /**< PHY Raw Interrupt Status                */
+  __IO uint32_t PHYIM;          /**< PHY Interrupt Mask                      */
+  __IO uint32_t PHYMISC;        /**< PHY Masked Interrupt Status and Clear   */
+} ETH_TypeDef;
+
+/**
  * @}
  */
 
@@ -796,6 +1038,8 @@ typedef struct
 #define QEI0_BASE   0x4002C000
 #define QEI1_BASE   0x4002D000
 
+#define ETH_BASE    0x400EC000
+
 /**
  * @}
  */
@@ -868,6 +1112,8 @@ typedef struct
 #define QEI0    ((QEI_TypeDef *)    QEI0_BASE)
 #define QEI1    ((QEI_TypeDef *)    QEI1_BASE)
 
+#define ETH     ((ETH_TypeDef *)  ETH_BASE)
+
 /**
  * @}
  */