Moved SDRAM defines out of example

2 files changed, 81 insertions, 80 deletions

diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h
index 83b78a6..7a04bdc 100644
--- a/os/hal/include/fsmc/sdram.h
+++ b/os/hal/include/fsmc/sdram.h
@@ -41,6 +41,85 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
+/*
+ *  FMC SDRAM Mode definition register defines
+ */
+#define FMC_SDCMR_MRD_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define FMC_SDCMR_MRD_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define FMC_SDCMR_MRD_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define FMC_SDCMR_MRD_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define FMC_SDCMR_MRD_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+/*
+ * FMC_ReadPipe_Delay
+ */
+#define FMC_ReadPipe_Delay_0               ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1               ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2               ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_Mask            ((uint32_t)0x00006000)
+
+/*
+ * FMC_Read_Burst
+ */
+#define FMC_Read_Burst_Disable             ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable              ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Mask                ((uint32_t)0x00001000)
+
+/*
+ * FMC_SDClock_Period
+ */
+#define FMC_SDClock_Disable                ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2               ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3               ((uint32_t)0x00000C00)
+#define FMC_SDClock_Period_Mask            ((uint32_t)0x00000C00)
+
+/*
+ * FMC_ColumnBits_Number
+ */
+#define FMC_ColumnBits_Number_8b           ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b           ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b          ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b          ((uint32_t)0x00000003)
+
+/*
+ * FMC_RowBits_Number
+ */
+#define FMC_RowBits_Number_11b             ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b             ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b             ((uint32_t)0x00000008)
+
+/*
+ * FMC_SDMemory_Data_Width
+ */
+#define FMC_SDMemory_Width_8b                ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b               ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b               ((uint32_t)0x00000020)
+
+/*
+ * FMC_InternalBank_Number
+ */
+#define FMC_InternalBank_Number_2          ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4          ((uint32_t)0x00000040)
+
+/*
+ * FMC_CAS_Latency
+ */
+#define FMC_CAS_Latency_1                  ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2                  ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3                  ((uint32_t)0x00000180)
+
+/*
+ * FMC_Write_Protection
+ */
+#define FMC_Write_Protection_Disable       ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable        ((uint32_t)0x00000200)
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -56,7 +135,7 @@
 #if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__)
 #define STM32_FSMC_USE_SDRAM1                  FALSE
 #else
-#define STM32_SDRAM1_MAP_BASE                        FSMC_Bank5_MAP_BASE
+#define STM32_SDRAM1_MAP_BASE                  FSMC_Bank5_MAP_BASE
 #endif
 
 /**
@@ -66,7 +145,7 @@
 #if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__)
 #define STM32_FSMC_USE_SDRAM2                  FALSE
 #else
-#define STM32_SDRAM2_MAP_BASE                        FSMC_Bank6_MAP_BASE
+#define STM32_SDRAM2_MAP_BASE                  FSMC_Bank6_MAP_BASE
 #endif
 
 /** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c
index 45e8db6..1ff7740 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c
@@ -32,84 +32,6 @@
  ******************************************************************************
  */
 
-/*
- *  FMC SDRAM Mode definition register defines
- */
-#define FMC_SDCMR_MRD_BURST_LENGTH_1             ((uint16_t)0x0000)
-#define FMC_SDCMR_MRD_BURST_LENGTH_2             ((uint16_t)0x0001)
-#define FMC_SDCMR_MRD_BURST_LENGTH_4             ((uint16_t)0x0002)
-#define FMC_SDCMR_MRD_BURST_LENGTH_8             ((uint16_t)0x0004)
-#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
-#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
-#define FMC_SDCMR_MRD_CAS_LATENCY_2              ((uint16_t)0x0020)
-#define FMC_SDCMR_MRD_CAS_LATENCY_3              ((uint16_t)0x0030)
-#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
-#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
-
-/*
- * FMC_ReadPipe_Delay
- */
-#define FMC_ReadPipe_Delay_0               ((uint32_t)0x00000000)
-#define FMC_ReadPipe_Delay_1               ((uint32_t)0x00002000)
-#define FMC_ReadPipe_Delay_2               ((uint32_t)0x00004000)
-#define FMC_ReadPipe_Delay_Mask            ((uint32_t)0x00006000)
-
-/*
- * FMC_Read_Burst
- */
-#define FMC_Read_Burst_Disable             ((uint32_t)0x00000000)
-#define FMC_Read_Burst_Enable              ((uint32_t)0x00001000)
-#define FMC_Read_Burst_Mask                ((uint32_t)0x00001000)
-
-/*
- * FMC_SDClock_Period
- */
-#define FMC_SDClock_Disable                ((uint32_t)0x00000000)
-#define FMC_SDClock_Period_2               ((uint32_t)0x00000800)
-#define FMC_SDClock_Period_3               ((uint32_t)0x00000C00)
-#define FMC_SDClock_Period_Mask            ((uint32_t)0x00000C00)
-
-/*
- * FMC_ColumnBits_Number
- */
-#define FMC_ColumnBits_Number_8b           ((uint32_t)0x00000000)
-#define FMC_ColumnBits_Number_9b           ((uint32_t)0x00000001)
-#define FMC_ColumnBits_Number_10b          ((uint32_t)0x00000002)
-#define FMC_ColumnBits_Number_11b          ((uint32_t)0x00000003)
-
-/*
- * FMC_RowBits_Number
- */
-#define FMC_RowBits_Number_11b             ((uint32_t)0x00000000)
-#define FMC_RowBits_Number_12b             ((uint32_t)0x00000004)
-#define FMC_RowBits_Number_13b             ((uint32_t)0x00000008)
-
-/*
- * FMC_SDMemory_Data_Width
- */
-#define FMC_SDMemory_Width_8b                ((uint32_t)0x00000000)
-#define FMC_SDMemory_Width_16b               ((uint32_t)0x00000010)
-#define FMC_SDMemory_Width_32b               ((uint32_t)0x00000020)
-
-/*
- * FMC_InternalBank_Number
- */
-#define FMC_InternalBank_Number_2          ((uint32_t)0x00000000)
-#define FMC_InternalBank_Number_4          ((uint32_t)0x00000040)
-
-/*
- * FMC_CAS_Latency
- */
-#define FMC_CAS_Latency_1                  ((uint32_t)0x00000080)
-#define FMC_CAS_Latency_2                  ((uint32_t)0x00000100)
-#define FMC_CAS_Latency_3                  ((uint32_t)0x00000180)
-
-/*
- * FMC_Write_Protection
- */
-#define FMC_Write_Protection_Disable       ((uint32_t)0x00000000)
-#define FMC_Write_Protection_Enable        ((uint32_t)0x00000200)
 
 #define SDRAM_SIZE       (8 * 1024 * 1024)
 #define SDRAM_START      ((void *)FSMC_Bank6_MAP_BASE)