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authorcpldcpu <cpldcpu@gmail.com>2015-05-30 12:28:47 +0200
committercpldcpu <cpldcpu@gmail.com>2015-05-30 12:28:47 +0200
commita7aa590a8965516ad0f0865be2c87b794127a8e0 (patch)
treefe4cade3d4ae0a2db082cb94fa847ffeea8c1258
parente67eb5000ccc6befd04cd1cb8115b5c06e45a76e (diff)
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firmware: Nanite841 config update
-rw-r--r--firmware/configuration/Nanite841/bootloaderconfig.h4
-rw-r--r--firmware/configuration/t841_default/bootloaderconfig.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/firmware/configuration/Nanite841/bootloaderconfig.h b/firmware/configuration/Nanite841/bootloaderconfig.h
index 7bf0a54..20be3f6 100644
--- a/firmware/configuration/Nanite841/bootloaderconfig.h
+++ b/firmware/configuration/Nanite841/bootloaderconfig.h
@@ -30,11 +30,11 @@
* "B", the registers PORTB, PINB and DDRB will be used.
*/
-#define USB_CFG_DMINUS_BIT 0
+#define USB_CFG_DMINUS_BIT 1
/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected.
* This may be any bit in the port.
*/
-#define USB_CFG_DPLUS_BIT 1
+#define USB_CFG_DPLUS_BIT 0
/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected.
* This may be any bit in the port, but must be configured as a pin change interrupt.
*/
diff --git a/firmware/configuration/t841_default/bootloaderconfig.h b/firmware/configuration/t841_default/bootloaderconfig.h
index 43da39d..6dfe795 100644
--- a/firmware/configuration/t841_default/bootloaderconfig.h
+++ b/firmware/configuration/t841_default/bootloaderconfig.h
@@ -11,7 +11,7 @@
* LED : PB2, Active Low
* OSCCAL : Revert to precalibrated value (8 MHz)
* Note: can use 12 MHz V-USB without PLL due to stable RC-osc in ATTiny841
- * Flash write time may be too
+ * Flash write time may be too low.
* Last Change: Mar 16,2014
*
* License: GNU GPL v2 (see License.txt