diff options
Diffstat (limited to 'sdram_test.vhd')
| -rw-r--r-- | sdram_test.vhd | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/sdram_test.vhd b/sdram_test.vhd new file mode 100644 index 0000000..156ca28 --- /dev/null +++ b/sdram_test.vhd @@ -0,0 +1,177 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library work; +use work.sdram_util.ALL; + +entity sdram is +port ( + clock_50 : in std_logic; + reset_n : in std_logic; + seven_seg : out std_logic_vector(7 downto 0); + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) +); +end entity; + +architecture rtl of sdram is + +component pllx2 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; + + + +component sdram_test_mcu is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + pio_0_d_export : out std_logic_vector(7 downto 0); -- export + sbb_0_reset_n : out std_logic -- reset_n + sbb_0_cs_n : out std_logic; -- cs_n + sbb_0_rnw : out std_logic; -- rnw + sbb_0_wait_n : in std_logic := 'X'; -- wait_n + sbb_0_addr : out std_logic_vector(15 downto 0); -- addr + sbb_0_data_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- data_in + sbb_0_data_out : out std_logic_vector(15 downto 0); -- data_out + ); +end component sdram_mcu; + +component sdram_ctrl is + port + ( + clock_100 : in std_logic; + reset_n : in std_logic; + + bus_cs_n : in std_logic; + bus_rnw : in std_logic; + + bus_wait_n : out std_logic; + + bus_addr : in addr_t; + bus_data_in : in data_t; + bus_data_out : out data_t; + + sdram_clk : out std_logic; + sdram_cke : out std_logic; + + sdram_cs_n : out std_logic; + + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout data_t; + sdram_dqm : out dqm_t; + + debug : out std_logic_vector(7 downto 0) + ); +end component; + +signal b_data_in8 : std_logic_vector(7 downto 0); +signal b_data_out8 : std_logic_vector(7 downto 0); +signal b_addr16: std_logic_vector(15 downto 0); + +signal b_addr : addr_t; +signal b_data_in : data_t; +signal b_data_out : data_t; +signal b_cs_n : std_logic; +signal b_rnw : std_logic; +signal b_wait_n : std_logic; + +signal pll_reset : std_logic; +signal mcu_clock : std_logic; +signal clock_100 : std_logic; +signal pll_locked : std_logic; +signal debug : std_logic_vector(7 downto 0); + +signal global_reset_n : std_logic; +signal b_reset_n : std_logic; + +signal buf8 : std_logic_vector(7 downto 0); + + +begin + + pll: pllx2 port map ( + pll_reset, + clock_50, + clock_100, + pll_locked ); + + mcu_clock <= clock_50; + + u0 : component sdram_mcu port map ( + clk_clk => mcu_clock, -- clk.clk + reset_reset_n => global_reset_n, -- reset.reset_n + pio_0_d_export => seven_seg, -- pio_0_d.export + sbb_0_reset_n => b_reset_n + sbb_0_cs_n => b_cs_n, -- ebb_0.cs_n + sbb_0_rnw => b_rnw, -- .rnw + sbb_0_wait_n => b_wait_n, -- .wait_n + sbb_0_addr => b_addr16, -- .addr + sbb_0_data_in => b_data_in, -- .data + sbb_0_data_out => b_data_out, -- .data + ); + + -- bodge buses together + + b_addr(15 downto 0) <= b_addr16; + b_addr(23 downto 16) <= (others => '0'); + + sdram_ctrl0: sdram_ctrl port map ( + clock_100 => clock_50, + reset_n => b_reset_n, + + bus_cs_n => b_cs_n, + bus_rnw => b_rnw, + + bus_wait_n => b_wait_n, + + bus_addr => b_addr, + bus_data_in => b_data_in, + bus_data_out => b_data_out, + + sdram_clk => sdram_clk, + sdram_cke => sdram_cke, + + sdram_cs_n => sdram_cs_n, + sdram_cas_n => sdram_cas_n, + sdram_ras_n => sdram_ras_n, + sdram_we_n => sdram_we_n, + + sdram_addr => sdram_addr, + sdram_ba => sdram_ba, + + sdram_dq => sdram_dq, + sdram_dqm => sdram_dqm, + + debug => debug + ); + + pll_reset <= '0'; + global_reset_n <= reset_n and pll_locked; + +end architecture; |