diff options
Diffstat (limited to 'sdram_ctrl.vhd')
| -rw-r--r-- | sdram_ctrl.vhd | 41 |
1 files changed, 19 insertions, 22 deletions
diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd index b89ece5..d41b1b6 100644 --- a/sdram_ctrl.vhd +++ b/sdram_ctrl.vhd @@ -2,18 +2,12 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; +library work; +use work.sdram_util.ALL; + -- a simple dram controller (no pipelineing) -- that looks like a slow static ram -subtype uint3_t is integer range 0 to 7; -subtype uint4_t is integer range 0 to 15; -subtype uint13_t is integer range 0 to 8191; -subtype cs_n_t is std_logic_vector(0 downto 0); -subtype addr_t is std_logic_vector(23 downto 0); -subtype data_t is std_logic_vector(15 downto 0); -subtype dqm_t is std_logic_vector(1 downto 0); - - entity sdram_ctrl is port ( @@ -21,13 +15,13 @@ entity sdram_ctrl is reset_n : in std_logic; bus_cs_n : in std_logic; - bus_rd_n : in std_logic; - bus_wr_n : in std_logic; + bus_rnw : in std_logic; bus_wait_n : out std_logic; bus_addr : in addr_t; - bus_data : inout data_t; + bus_data_in : in data_t; + bus_data_out : out data_t; sdram_clk : out std_logic; sdram_cke : out std_logic; @@ -42,13 +36,14 @@ entity sdram_ctrl is sdram_ba : out std_logic_vector(1 downto 0); sdram_dq : inout data_t; - sdram_dqm : out dqm_t; + sdram_dqm : out dqm_t ); end entity; architecture rtl of sdram_ctrl is + signal clock : std_logic; -- bits in the MEM_CMD register RAS_N CAS_N WE_N @@ -138,16 +133,16 @@ architecture rtl of sdram_ctrl is signal r_data_valid: std_logic_vector(2 downto 0); -- bus logic - signal request_post: std_logic; + signal post_request: std_logic; -- bus fsm signal b_state : std_logic_vector(4 downto 0); - constant B_ST_WAIT_CS_LOW : std_logic_vector(4 downto 0):="00001"; + constant B_ST_WAIT_CS_N_LOW : std_logic_vector(4 downto 0):="00001"; constant B_ST_LODGE_REQUEST : std_logic_vector(4 downto 0):="00010"; constant B_ST_WAIT_ACK : std_logic_vector(4 downto 0):="00100"; constant B_ST_WAIT_DATA : std_logic_vector(4 downto 0):="01000"; - constant B_ST_WAIT_CS_HIGH : std_logic_vector(4 downto 0):="10000"; + constant B_ST_WAIT_CS_N_HIGH : std_logic_vector(4 downto 0):="10000"; -- convert boolean to active high logic function b2l_ah(constant val : in boolean) return std_logic is begin @@ -476,11 +471,14 @@ begin sdram_addr <= mem_addr; sdram_ba <= mem_bank; + sdram_dq_tristate: process(mem_oe,mem_data_out) begin if l2b_ah(mem_oe) then sdram_dq <= mem_data_out; else sdram_dq <= (others => 'Z' ); end if; + end process; + mem_data_in <= sdram_dq; sdram_dqm <= mem_dqm; @@ -490,20 +488,19 @@ begin if l2b_al(reset_n) then r_data_valid <= (others => '0'); elsif rising_edge(clock) then - r_data_valid(1 downto 0)=r_data_valid(2 downto 1); + r_data_valid(1 downto 0)<=r_data_valid(2 downto 1); r_data_valid(2) <= b2l_ah(mem_cmd = MEM_CMD_READ); end if; end process; - bus: process (reset_n,clock,b_state,bus_cs_n,bus_rnw,bus_addr,bus_data,ack_request,r_data_valid) begin + bus_fsm: process (reset_n,clock,b_state,bus_cs_n,bus_rnw,bus_addr,bus_data_in,ack_request,r_data_valid) begin if l2b_al(reset_n) then - request_pending <= '0'; bus_data_out <= (others => '0'); request_data <= (others => '0'); request_addr <= (others => '0'); request_rnw <= '0'; - request_cs_n <= CS_N_NONE; + request_cs_n <= MEM_CS_N_NONE; request_dqm <= "00"; b_state <= B_ST_WAIT_CS_N_LOW; elsif rising_edge(clock) then @@ -517,7 +514,7 @@ begin request_rnw <= '0'; -- send to first chip and all bytes - request_cs_n <= "0" (others => '1'); + request_cs_n <= "0"; -- (others => '1'); request_dqm <= "00"; bus_wait_n <= '0'; @@ -544,7 +541,7 @@ begin bus_wait_n <= '1'; b_state <= B_ST_WAIT_CS_N_HIGH; end if; - elsif b_state = B_ST_WAIT_CS_N_HIGH: + elsif b_state = B_ST_WAIT_CS_N_HIGH then if not l2b_al(bus_cs_n) then b_state <=B_ST_WAIT_CS_N_LOW; end if; |