diff options
Diffstat (limited to 'sdram.vhd')
| -rw-r--r-- | sdram.vhd | 60 |
1 files changed, 32 insertions, 28 deletions
@@ -47,11 +47,11 @@ component sdram_mcu is reset_reset_n : in std_logic := 'X'; -- reset_n pio_0_d_export : out std_logic_vector(7 downto 0); -- export ebb_0_cs_n : out std_logic; -- cs_n - ebb_0_rd_n : out std_logic; -- rd_n - ebb_0_wr_n : out std_logic; -- wr_n + ebb_0_rnw : out std_logic; -- rnw ebb_0_wait_n : in std_logic := 'X'; -- wait_n ebb_0_addr : out std_logic_vector(15 downto 0); -- addr - ebb_0_data : inout std_logic_vector(7 downto 0) := (others => 'X') -- data + ebb_0_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_in + ebb_0_data_out : out std_logic_vector(7 downto 0) -- data_out ); end component sdram_mcu; @@ -87,11 +87,12 @@ component sdram_ctrl is ); end component; +signal b_data_in8 : std_logic_vector(7 downto 0); +signal b_data_out8 : std_logic_vector(7 downto 0); +signal b_addr16: std_logic_vector(15 downto 0); signal b_addr : addr_t; -signal b_data_in8 : std_logic_vector(7 downto 0); signal b_data_in : data_t; -signal b_data_out8 : std_logic_vector(7 downto 0); signal b_data_out : data_t; signal b_cs_n : std_logic; signal b_rnw : std_logic; @@ -119,44 +120,47 @@ begin ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n ebb_0_rnw => b_rnw, -- .rnw ebb_0_wait_n => b_wait_n, -- .wait_n - ebb_0_addr => b_addr, -- .addr + ebb_0_addr => b_addr16, -- .addr ebb_0_data_in => b_data_in8, -- .data ebb_0_data_out => b_data_out8 -- .data ); - b_data_in(7 downto 0) <= b_data_in8; - b_data_in(15 downto 8) <= (others => '0'); + -- bodge buses together + + b_data_in(7 downto 0) <= b_data_out8; + b_data_in(15 downto 8) <= (others =>'0'); - b_data_out8 <= b_data_out(7 downto 0); + b_data_in8 <= b_data_out(7 downto 0); + b_addr(15 downto 0) <= b_addr16; + b_addr(23 downto 16) <= (others => '0'); sdram_ctrl0: sdram_ctrl port map ( - clock_100, - global_reset_n, + clock_100 => clock_100, + reset_n => global_reset_n, - b_cs_n, - b_rnw, + bus_cs_n => b_cs_n, + bus_rnw => b_rnw, - b_wait_n, - sdram_cke, + bus_wait_n => b_wait_n, - b_addr, - b_data_in, - b_data_out, + bus_addr => b_addr, + bus_data_in => b_data_in, + bus_data_out => b_data_out, - sdram_clk, - sdram_cke, + sdram_clk => sdram_clk, + sdram_cke => sdram_cke, - sdram_cs_n, - sdram_cas_n, - sdram_ras_n, - sdram_we_n, + sdram_cs_n => sdram_cs_n, + sdram_cas_n => sdram_cas_n, + sdram_ras_n => sdram_ras_n, + sdram_we_n => sdram_we_n, - sdram_addr, - sdram_ba, + sdram_addr => sdram_addr, + sdram_ba => sdram_ba, - sdram_dq, - sdram_dqm + sdram_dq => sdram_dq, + sdram_dqm => sdram_dqm ); pll_reset <= '0'; |